dm355 interrupt and edma event mux support

Generalize the new mux_cfg code to support interrupt and
EDMA event muxing on dm355.  Move the MMC0 event mux logic
to the device setup code, away from clock enable code where
it doesn't belong.  Mux the EDMA error interrupts.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

arch/arm/mach-davinci/devices.c

@@ -186,6 +186,9 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
 
 			/* expose all 6 MMC0 signals:  CLK, CMD, DATA[0..3] */
 			davinci_cfg_reg(DM355_MMCSD0);
+
+			/* enable RX EDMA */
+			davinci_cfg_reg(DM355_EVT26_MMC0_RX);
 		}
 		pdev = &davinci_mmcsd0_device;
 		clockname = cpu_is_davinci_dm355() ? "MMCSDCLK0" : "MMCSDCLK";

arch/arm/mach-davinci/dma.c

@@ -21,21 +21,24 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  * ----------------------------------------------------------------------------
- *
  */
+#include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
+
 #include <asm/io.h>
+
+#include <mach/cpu.h>
 #include <mach/memory.h>
-#include <linux/kernel.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-
 #include <mach/edma.h>
+#include <mach/mux.h>
+
 /**************************************************************************\
 * Register Overlay Structure for PARAMENTRY
 \**************************************************************************/
@@ -781,6 +784,13 @@ int __init arch_dma_init(void)
 	for (i = 0; i < DAVINCI_EDMA_NUM_PARAMENTRY * PARM_SIZE; i += 4)
 		edma_write(EDMA_PARM + i, 0);
 
+	if (cpu_is_davinci_dm355()) {
+		/* NOTE conflicts with SPI1_INT{0,1} and SPI2_INT0 */
+		davinci_cfg_reg(DM355_INT_EDMA_CC);
+		davinci_cfg_reg(DM355_INT_EDMA_TC0_ERR);
+		davinci_cfg_reg(DM355_INT_EDMA_TC1_ERR);
+	}
+
 	/* Everything lives on transfer controller 1 until otherwise specified.
 	 * This way, long transfers on the low priority queue
 	 * started by the codec engine will not cause audio defects.

arch/arm/mach-davinci/include/mach/mux.h

@@ -28,6 +28,8 @@
 #define PINMUX2			(DAVINCI_SYSTEM_MODULE_BASE + 0x08)
 #define PINMUX3			(DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
 #define PINMUX4			(DAVINCI_SYSTEM_MODULE_BASE + 0x10)
+#define INTMUX			(DAVINCI_SYSTEM_MODULE_BASE + 0x18)
+#define EVTMUX			(DAVINCI_SYSTEM_MODULE_BASE + 0x1c)
 
 struct mux_config {
 	char *name;
@@ -119,7 +121,7 @@ enum davinci_dm355_index {
 	DM355_I2C_SDA,
 	DM355_I2C_SCL,
 
-	/* ASP function */
+	/* ASP0 function */
 	DM355_MCBSP0_BDX,
 	DM355_MCBSP0_X,
 	DM355_MCBSP0_BFSX,
@@ -131,6 +133,16 @@ enum davinci_dm355_index {
 	DM355_SPI0_SDI,
 	DM355_SPI0_SDENA0,
 	DM355_SPI0_SDENA1,
+
+	/* IRQ muxing */
+	DM355_INT_EDMA_CC,
+	DM355_INT_EDMA_TC0_ERR,
+	DM355_INT_EDMA_TC1_ERR,
+
+	/* EDMA event muxing */
+	DM355_EVT8_ASP1_TX,
+	DM355_EVT9_ASP1_RX,
+	DM355_EVT26_MMC0_RX,
 };
 
 #ifdef CONFIG_DAVINCI_MUX

arch/arm/mach-davinci/mux_cfg.c

@@ -34,6 +34,28 @@
 			.mode = mux_mode,				\
 		},
 
+#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg)	\
+[soc##_##desc] = {							\
+			.name =  #desc,					\
+			.debug = dbg,					\
+			.mux_reg_name = "INTMUX",			\
+			.mux_reg = INTMUX,				\
+			.mask_offset = mode_offset,			\
+			.mask = mode_mask,				\
+			.mode = mux_mode,				\
+		},
+
+#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg)	\
+[soc##_##desc] = {							\
+			.name =  #desc,					\
+			.debug = dbg,					\
+			.mux_reg_name = "EVTMUX",			\
+			.mux_reg = EVTMUX,				\
+			.mask_offset = mode_offset,			\
+			.mask = mode_mask,				\
+			.mode = mux_mode,				\
+		},
+
 /*
  *	soc	description	mux  mode   mode  mux	 dbg
  *				reg  offset mask  mode
@@ -117,6 +139,14 @@ MUX_CFG(DM355,	MCBSP0_BFSR,	3,   5,     1,	  1,	 false)
 MUX_CFG(DM355,	SPI0_SDI,	4,   1,     1,    0,	 false)
 MUX_CFG(DM355,	SPI0_SDENA0,	4,   0,     1,    0,	 false)
 MUX_CFG(DM355,	SPI0_SDENA1,	3,   28,    1,    1,	 false)
+
+INT_CFG(DM355,  INT_EDMA_CC,	      2,    1,    1,     false)
+INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
+INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
+
+EVT_CFG(DM355,  EVT8_ASP1_TX,	      0,    1,    0,     false)
+EVT_CFG(DM355,  EVT9_ASP1_RX,	      1,    1,    0,     false)
+EVT_CFG(DM355,  EVT26_MMC0_RX,	      2,    1,    0,     false)
 };
 
 void __init davinci_mux_init(void)

arch/arm/mach-davinci/psc.c

@@ -100,12 +100,6 @@ static void dm355_psc_mux(unsigned int id)
 		tmp &= ~(BIT(1) | BIT(0));
 		davinci_writel(tmp, DM355_EDMA_EVTMUX);
 		break;
-	case DAVINCI_LPSC_MMC_SD:	/* MMC0 */
-		/* support EMDA for MMC0 RX */
-		tmp = davinci_readl(DM355_EDMA_EVTMUX);
-		tmp &= ~BIT(2);
-		davinci_writel(tmp, DM355_EDMA_EVTMUX);
-		break;
 	case DAVINCI_LPSC_SPI:			/* SPI0 */
 		/* expose SPI0_SDI
 		 * NOTE: SPIO_SDENA0 and/or SPIO_SDENA1