Commit ddb598f9 authored by Hari Kanigeri's avatar Hari Kanigeri

SYSLINK:proc-add l4entries and fix checkpatch warnings

This patch handles the following
        - Adds the missing L4 peripheral mapping
        - Fixes the checkpatch warnings in proc4430
        - Fixes the prints to remove the tabs.
        - Cosmetic changes in the code
Signed-off-by: default avatarHari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: default avatarSuman Anna <&lt;s-anna@ti.com>
parent 822883d0
...@@ -135,6 +135,21 @@ struct memory_entry { ...@@ -135,6 +135,21 @@ struct memory_entry {
static const struct mmu_entry l4_map[] = { static const struct mmu_entry l4_map[] = {
/* Mailbox 4KB*/ /* Mailbox 4KB*/
{L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB}, {L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB},
/* I2C 4KB each */
{L4_PERIPHERAL_I2C1, DSPVA_PERIPHERAL_I2C1, HW_PAGE_SIZE_4KB},
{L4_PERIPHERAL_I2C2, DSPVA_PERIPHERAL_I2C2, HW_PAGE_SIZE_4KB},
{L4_PERIPHERAL_I2C3, DSPVA_PERIPHERAL_I2C3, HW_PAGE_SIZE_4KB},
/* DMA 4KB */
{L4_PERIPHERAL_DMA, DSPVA_PERIPHERAL_DMA, HW_PAGE_SIZE_4KB},
/* GPIO Banks 4KB each */
{L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1, HW_PAGE_SIZE_4KB},
{L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2, HW_PAGE_SIZE_4KB},
{L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3, HW_PAGE_SIZE_4KB},
/* GPTimers 4KB each */
{L4_PERIPHERAL_GPTIMER3, DSPVA_PERIPHERAL_GPTIMER3, HW_PAGE_SIZE_4KB},
{L4_PERIPHERAL_GPTIMER4, DSPVA_PERIPHERAL_GPTIMER4, HW_PAGE_SIZE_4KB},
{L4_PERIPHERAL_GPTIMER9, DSPVA_PERIPHERAL_GPTIMER9, HW_PAGE_SIZE_4KB},
{L4_PERIPHERAL_GPTIMER11, DSPVA_PERIPHERAL_GPTIMER11, HW_PAGE_SIZE_4KB},
}; };
static const struct memory_entry l3_memory_regions[] = { static const struct memory_entry l3_memory_regions[] = {
......
...@@ -1021,10 +1021,10 @@ int ducati_mmu_init(u32 a_phy_addr) ...@@ -1021,10 +1021,10 @@ int ducati_mmu_init(u32 a_phy_addr)
hw_mmu_victim_numset(ducati_mmu_linear_addr, hw_mmu_victim_numset(ducati_mmu_linear_addr,
mmu_index_next); mmu_index_next);
printk(KERN_ALERT " Programming Ducati memory regions\n");
printk(KERN_ALERT "================================\n");
for (i = 0; i < num_l3_mem_entries; i++) { for (i = 0; i < num_l3_mem_entries; i++) {
printk(KERN_ALERT " Programming memory region at [VA = 0x%x] \ printk(KERN_ALERT "VA = [0x%x] of size [0x%x] at PA = [0x%x]\n",
of size [0x%x] at [PA = 0x%x]",
l3_memory_regions[i].ul_virt_addr, l3_memory_regions[i].ul_virt_addr,
l3_memory_regions[i].ul_size, phys_addr); l3_memory_regions[i].ul_size, phys_addr);
if (l3_memory_regions[i].ul_virt_addr == DUCATI_SHARED_IPC_ADDR) if (l3_memory_regions[i].ul_virt_addr == DUCATI_SHARED_IPC_ADDR)
...@@ -1040,8 +1040,8 @@ int ducati_mmu_init(u32 a_phy_addr) ...@@ -1040,8 +1040,8 @@ int ducati_mmu_init(u32 a_phy_addr)
tiler_totalsize = DUCATIVA_TILER_VIEW0_LEN; tiler_totalsize = DUCATIVA_TILER_VIEW0_LEN;
phys_addr = L3_TILER_VIEW0_ADDR; phys_addr = L3_TILER_VIEW0_ADDR;
printk(KERN_ALERT " Programming TILER memory region at \ printk(KERN_ALERT " Programming TILER memory region at "
[VA = 0x%x] of size [0x%x] at [PA = 0x%x]", "[VA = 0x%x] of size [0x%x] at [PA = 0x%x]\n",
tiler_mapbeg, tiler_totalsize, phys_addr); tiler_mapbeg, tiler_totalsize, phys_addr);
ret_val = add_entry_ext(&phys_addr, &tiler_mapbeg, tiler_totalsize); ret_val = add_entry_ext(&phys_addr, &tiler_mapbeg, tiler_totalsize);
if (WARN_ON(ret_val < 0)) if (WARN_ON(ret_val < 0))
......
...@@ -595,22 +595,19 @@ long hw_mmu_tlb_dump(const u32 base_address, bool shw_inv_entries) ...@@ -595,22 +595,19 @@ long hw_mmu_tlb_dump(const u32 base_address, bool shw_inv_entries)
>> MMU_MMU_LOCK_CurrentVictim_OFFSET)); >> MMU_MMU_LOCK_CurrentVictim_OFFSET));
for (i = 0; i < NUM_TLB_ENTRIES; i++) { for (i = 0; i < NUM_TLB_ENTRIES; i++) {
mmu_lck_crnt_vctmwite32(base_address, i); mmu_lck_crnt_vctmwite32(base_address, i);
cam = MMUMMU_CAMReadRegister32(base_address); cam = MMUMMU_CAMReadRegister32(base_address);
ram = MMUMMU_RAMReadRegister32(base_address); ram = MMUMMU_RAMReadRegister32(base_address);
if ((cam & 0x4) != 0) { if ((cam & 0x4) != 0) {
printk(KERN_ALERT "TLB Entry [0x%x]: VA = 0x%x"
printk(KERN_ALERT "TLB Entry [0x%x]: VA = 0x%x PA = 0x%x" "PA = 0x%x Protected = 0x%x\n)",
"Protected = 0x%x\n)",
i, (cam & MMU_ADDR_MASK), (ram & MMU_ADDR_MASK), i, (cam & MMU_ADDR_MASK), (ram & MMU_ADDR_MASK),
(cam & 0x8) ? 1 : 0); (cam & 0x8) ? 1 : 0);
} else if (shw_inv_entries != false) { } else if (shw_inv_entries != false)
printk(KERN_ALERT "TLB Entry [0x%x]: <INVALID>\n", i); printk(KERN_ALERT "TLB Entry [0x%x]: <INVALID>\n", i);
} }
}
mmu_lck_write_reg32(base_address, lockSave); mmu_lck_write_reg32(base_address, lockSave);
return RET_OK; return RET_OK;
} }
......
...@@ -198,10 +198,10 @@ static int proc4430_drv_ioctl(struct inode *inode, struct file *filp, ...@@ -198,10 +198,10 @@ static int proc4430_drv_ioctl(struct inode *inode, struct file *filp,
if (WARN_ON(retval < 0)) if (WARN_ON(retval < 0))
goto func_exit; goto func_exit;
/* Copy the contents of mem_entries from user-side */ /* Copy the contents of mem_entries from user-side */
if(params.num_mem_entries) { if (params.num_mem_entries) {
entries = vmalloc(params.num_mem_entries * \ entries = vmalloc(params.num_mem_entries * \
sizeof(struct proc4430_mem_entry)); sizeof(struct proc4430_mem_entry));
if(WARN_ON(!entries)) if (WARN_ON(!entries))
goto func_exit; goto func_exit;
retval = copy_from_user((void *) (entries), retval = copy_from_user((void *) (entries),
(const void *)(params.mem_entries), (const void *)(params.mem_entries),
...@@ -221,7 +221,7 @@ static int proc4430_drv_ioctl(struct inode *inode, struct file *filp, ...@@ -221,7 +221,7 @@ static int proc4430_drv_ioctl(struct inode *inode, struct file *filp,
(const void *)&src_args, (const void *)&src_args,
sizeof(struct proc4430_cmd_args_create)); sizeof(struct proc4430_cmd_args_create));
/* Free the memory created */ /* Free the memory created */
if(params.num_mem_entries) if (params.num_mem_entries)
vfree(entries); vfree(entries);
} }
break; break;
......
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