Commit d99241c8 authored by Madhusudhan Chikkature Rajashekar's avatar Madhusudhan Chikkature Rajashekar Committed by Tony Lindgren

RE: [PATCH] Add WDT support for OMAP3430

Add watchdog timer support for TI OMAP3430.

Fix clk_put functions mismatch in the release fn which would crash the kernel if
the WDT test is run multiple times with "CONFIG_WATCHDOG_NOWAYOUT" disabled.

Fix the shutdown function.Check for wdt users before calling disable.
Signed-off-by: default avatarMadhusudhan Chikkature <madhu.cr@ti.com>

Updated for path change to drivers/watchdog.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent b57e9338
......@@ -595,6 +595,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_OMAP_WATCHDOG=y
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
......
......@@ -437,7 +437,9 @@ static inline void omap_init_uwire(void) {}
#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP34XX)
#define OMAP_WDT_BASE 0x48314000
#elif defined(CONFIG_ARCH_OMAP24XX)
#ifdef CONFIG_ARCH_OMAP2430
/* WDT2 */
......
......@@ -173,10 +173,10 @@ config EP93XX_WATCHDOG
config OMAP_WATCHDOG
tristate "OMAP Watchdog"
depends on ARCH_OMAP16XX || ARCH_OMAP24XX
depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
help
Support for TI OMAP1610/OMAP1710/OMAP2420 watchdog. Say 'Y' here to
enable the OMAP1610/OMAP1710 watchdog timer.
Support for TI OMAP1610/OMAP1710/OMAP2420/OMAP3430 watchdog. Say 'Y'
here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430 watchdog timer.
config PNX4008_WATCHDOG
tristate "PNX4008 Watchdog"
......
/*
* linux/drivers/char/watchdog/omap_wdt.c
* linux/drivers/watchdog/omap_wdt.c
*
* Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
*
* Author: MontaVista Software, Inc.
* <gdavis@mvista.com> or <source@mvista.com>
......@@ -39,59 +39,71 @@
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/clk.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/hardware.h>
#include <asm/bitops.h>
#include <asm/arch/prcm.h>
#include "omap_wdt.h"
static struct platform_device *omap_wdt_dev;
static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
static int omap_wdt_users;
static struct clk *armwdt_ck = NULL;
static struct clk *mpu_wdt_ick = NULL;
static struct clk *mpu_wdt_fck = NULL;
static unsigned int wdt_trgr_pattern = 0x1234;
struct omap_wdt_dev {
void __iomem *base; /* physical */
struct device *dev;
int omap_wdt_users;
struct clk *armwdt_ck;
struct clk *mpu_wdt_ick;
struct clk *mpu_wdt_fck;
struct resource *mem;
struct miscdevice omap_wdt_miscdev;
};
static void omap_wdt_ping(void)
static void omap_wdt_ping(struct omap_wdt_dev *wdev)
{
void __iomem *base = wdev->base;
/* wait for posted write to complete */
while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
cpu_relax();
wdt_trgr_pattern = ~wdt_trgr_pattern;
omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
omap_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
/* wait for posted write to complete */
while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
cpu_relax();
/* reloaded WCRR from WLDR */
}
static void omap_wdt_enable(void)
static void omap_wdt_enable(struct omap_wdt_dev *wdev)
{
void __iomem *base;
base = wdev->base;
/* Sequence to enable the watchdog */
omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
omap_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
cpu_relax();
omap_writel(0x4444, OMAP_WATCHDOG_SPR);
while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
omap_writel(0x4444, base + OMAP_WATCHDOG_SPR);
while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
cpu_relax();
}
static void omap_wdt_disable(void)
static void omap_wdt_disable(struct omap_wdt_dev *wdev)
{
void __iomem *base;
base = wdev->base;
/* sequence required to disable watchdog */
omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
omap_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
cpu_relax();
omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
omap_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
cpu_relax();
}
......@@ -104,15 +116,17 @@ static void omap_wdt_adjust_timeout(unsigned new_timeout)
timer_margin = new_timeout;
}
static void omap_wdt_set_timeout(void)
static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
{
u32 pre_margin = GET_WLDR_VAL(timer_margin);
void __iomem *base;
base = wdev->base;
/* just count up at 32 KHz */
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
cpu_relax();
omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
omap_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
cpu_relax();
}
......@@ -122,55 +136,57 @@ static void omap_wdt_set_timeout(void)
static int omap_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
struct omap_wdt_dev *wdev;
void __iomem *base;
wdev = platform_get_drvdata(omap_wdt_dev);
base = wdev->base;
if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
return -EBUSY;
if (cpu_is_omap16xx())
clk_enable(armwdt_ck); /* Enable the clock */
clk_enable(wdev->armwdt_ck); /* Enable the clock */
if (cpu_is_omap24xx()) {
clk_enable(mpu_wdt_ick); /* Enable the interface clock */
clk_enable(mpu_wdt_fck); /* Enable the functional clock */
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
clk_enable(wdev->mpu_wdt_ick); /* Enable the interface clock */
clk_enable(wdev->mpu_wdt_fck); /* Enable the functional clock */
}
/* initialize prescaler */
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
cpu_relax();
omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
omap_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
cpu_relax();
omap_wdt_set_timeout();
omap_wdt_enable();
file->private_data = (void *) wdev;
omap_wdt_set_timeout(wdev);
omap_wdt_enable(wdev);
return nonseekable_open(inode, file);
}
static int omap_wdt_release(struct inode *inode, struct file *file)
{
struct omap_wdt_dev *wdev;
wdev = file->private_data;
/*
* Shut off the timer unless NOWAYOUT is defined.
*/
#ifndef CONFIG_WATCHDOG_NOWAYOUT
omap_wdt_disable();
if (cpu_is_omap16xx()) {
clk_disable(armwdt_ck); /* Disable the clock */
clk_put(armwdt_ck);
armwdt_ck = NULL;
}
omap_wdt_disable(wdev);
if (cpu_is_omap24xx()) {
clk_disable(mpu_wdt_ick); /* Disable the clock */
clk_disable(mpu_wdt_fck); /* Disable the clock */
clk_put(mpu_wdt_ick);
clk_put(mpu_wdt_fck);
mpu_wdt_ick = NULL;
mpu_wdt_fck = NULL;
if (cpu_is_omap16xx())
clk_disable(wdev->armwdt_ck); /* Disable the clock */
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
clk_disable(wdev->mpu_wdt_ick); /* Disable the clock */
clk_disable(wdev->mpu_wdt_fck); /* Disable the clock */
}
#else
printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
#endif
omap_wdt_users = 0;
wdev->omap_wdt_users = 0;
return 0;
}
......@@ -178,9 +194,11 @@ static ssize_t
omap_wdt_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
struct omap_wdt_dev *wdev;
wdev = file->private_data;
/* Refresh LOAD_TIME. */
if (len)
omap_wdt_ping();
omap_wdt_ping(wdev);
return len;
}
......@@ -188,12 +206,14 @@ static int
omap_wdt_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
struct omap_wdt_dev *wdev;
int new_margin;
static struct watchdog_info ident = {
.identity = "OMAP Watchdog",
.options = WDIOF_SETTIMEOUT,
.firmware_version = 0,
};
wdev = file->private_data;
switch (cmd) {
default:
......@@ -211,22 +231,23 @@ omap_wdt_ioctl(struct inode *inode, struct file *file,
return put_user(omap_prcm_get_reset_sources(),
(int __user *)arg);
case WDIOC_KEEPALIVE:
omap_wdt_ping();
omap_wdt_ping(wdev);
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_margin, (int __user *)arg))
return -EFAULT;
omap_wdt_adjust_timeout(new_margin);
omap_wdt_disable();
omap_wdt_set_timeout();
omap_wdt_enable();
omap_wdt_disable(wdev);
omap_wdt_set_timeout(wdev);
omap_wdt_enable(wdev);
omap_wdt_ping();
omap_wdt_ping(wdev);
/* Fall */
case WDIOC_GETTIMEOUT:
return put_user(timer_margin, (int __user *)arg);
}
return 0;
}
static const struct file_operations omap_wdt_fops = {
......@@ -237,96 +258,146 @@ static const struct file_operations omap_wdt_fops = {
.release = omap_wdt_release,
};
static struct miscdevice omap_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &omap_wdt_fops
};
static int __init omap_wdt_probe(struct platform_device *pdev)
{
struct resource *res, *mem;
int ret;
struct omap_wdt_dev *wdev;
/* reserve static register mappings */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
if (omap_wdt_dev)
return -EBUSY;
mem = request_mem_region(res->start, res->end - res->start + 1,
pdev->name);
if (mem == NULL)
return -EBUSY;
platform_set_drvdata(pdev, mem);
omap_wdt_users = 0;
wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
if (!wdev) {
ret = -ENOMEM;
goto fail;
}
wdev->omap_wdt_users = 0;
wdev->mem = mem;
if (cpu_is_omap16xx()) {
armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
if (IS_ERR(armwdt_ck)) {
ret = PTR_ERR(armwdt_ck);
armwdt_ck = NULL;
wdev->armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
if (IS_ERR(wdev->armwdt_ck)) {
ret = PTR_ERR(wdev->armwdt_ck);
wdev->armwdt_ck = NULL;
goto fail;
}
}
if (cpu_is_omap24xx()) {
mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
if (IS_ERR(mpu_wdt_ick)) {
ret = PTR_ERR(mpu_wdt_ick);
mpu_wdt_ick = NULL;
wdev->mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
if (IS_ERR(wdev->mpu_wdt_ick)) {
ret = PTR_ERR(wdev->mpu_wdt_ick);
wdev->mpu_wdt_ick = NULL;
goto fail;
}
wdev->mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
if (IS_ERR(wdev->mpu_wdt_fck)) {
ret = PTR_ERR(wdev->mpu_wdt_fck);
wdev->mpu_wdt_fck = NULL;
goto fail;
}
}
if (cpu_is_omap34xx()) {
wdev->mpu_wdt_ick = clk_get(&pdev->dev, "wdt2_ick");
if (IS_ERR(wdev->mpu_wdt_ick)) {
ret = PTR_ERR(wdev->mpu_wdt_ick);
wdev->mpu_wdt_ick = NULL;
goto fail;
}
mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
if (IS_ERR(mpu_wdt_fck)) {
ret = PTR_ERR(mpu_wdt_fck);
mpu_wdt_fck = NULL;
wdev->mpu_wdt_fck = clk_get(&pdev->dev, "wdt2_fck");
if (IS_ERR(wdev->mpu_wdt_fck)) {
ret = PTR_ERR(wdev->mpu_wdt_fck);
wdev->mpu_wdt_fck = NULL;
goto fail;
}
}
wdev->base = (void __iomem *) (mem->start);
platform_set_drvdata(pdev, wdev);
omap_wdt_disable();
omap_wdt_disable(wdev);
omap_wdt_adjust_timeout(timer_margin);
omap_wdt_miscdev.parent = &pdev->dev;
ret = misc_register(&omap_wdt_miscdev);
wdev->omap_wdt_miscdev.parent = &pdev->dev;
wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
wdev->omap_wdt_miscdev.name = "watchdog";
wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
ret = misc_register(&(wdev->omap_wdt_miscdev));
if (ret)
goto fail;
pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
omap_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
timer_margin);
/* autogate OCP interface clock */
omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
omap_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);
omap_wdt_dev = pdev;
return 0;
fail:
if (armwdt_ck)
clk_put(armwdt_ck);
if (mpu_wdt_ick)
clk_put(mpu_wdt_ick);
if (mpu_wdt_fck)
clk_put(mpu_wdt_fck);
release_resource(mem);
if (wdev) {
platform_set_drvdata(pdev, NULL);
if (wdev->armwdt_ck)
clk_put(wdev->armwdt_ck);
if (wdev->mpu_wdt_ick)
clk_put(wdev->mpu_wdt_ick);
if (wdev->mpu_wdt_fck)
clk_put(wdev->mpu_wdt_fck);
kfree(wdev);
}
if (mem) {
release_resource(mem);
}
return ret;
}
static void omap_wdt_shutdown(struct platform_device *pdev)
{
omap_wdt_disable();
struct omap_wdt_dev *wdev;
wdev = platform_get_drvdata(pdev);
if (wdev->omap_wdt_users)
omap_wdt_disable(wdev);
}
static int omap_wdt_remove(struct platform_device *pdev)
{
struct resource *mem = platform_get_drvdata(pdev);
misc_deregister(&omap_wdt_miscdev);
release_resource(mem);
if (armwdt_ck)
clk_put(armwdt_ck);
if (mpu_wdt_ick)
clk_put(mpu_wdt_ick);
if (mpu_wdt_fck)
clk_put(mpu_wdt_fck);
struct omap_wdt_dev *wdev;
wdev = platform_get_drvdata(pdev);
misc_deregister(&(wdev->omap_wdt_miscdev));
release_resource(wdev->mem);
platform_set_drvdata(pdev, NULL);
if (wdev->armwdt_ck) {
clk_put(wdev->armwdt_ck);
wdev->armwdt_ck = NULL;
}
if (wdev->mpu_wdt_ick) {
clk_put(wdev->mpu_wdt_ick);
wdev->mpu_wdt_ick = NULL;
}
if (wdev->mpu_wdt_fck) {
clk_put(wdev->mpu_wdt_fck);
wdev->mpu_wdt_fck = NULL;
}
kfree(wdev);
omap_wdt_dev = NULL;
return 0;
}
......@@ -340,16 +411,20 @@ static int omap_wdt_remove(struct platform_device *pdev)
static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
if (omap_wdt_users)
omap_wdt_disable();
struct omap_wdt_dev *wdev;
wdev = platform_get_drvdata(pdev);
if (wdev->omap_wdt_users)
omap_wdt_disable(wdev);
return 0;
}
static int omap_wdt_resume(struct platform_device *pdev)
{
if (omap_wdt_users) {
omap_wdt_enable();
omap_wdt_ping();
struct omap_wdt_dev *wdev;
wdev = platform_get_drvdata(pdev);
if (wdev->omap_wdt_users) {
omap_wdt_enable(wdev);
omap_wdt_ping(wdev);
}
return 0;
}
......
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