Davinci resizer driver

drivers/char/Kconfig

@@ -1071,6 +1071,13 @@ config HPET_MMAP
 	  exposed to the user.  If this applies to your hardware,
 	  say N here.
 
+config DAVINCI_RESIZER
+        tristate "DaVinci Resizer Driver"
+        default n
+	depends on ARCH_DAVINCI
+        help
+                DaVinci Resizer Driver.
+
 config HANGCHECK_TIMER
 	tristate "Hangcheck timer"
 	depends on X86 || IA64 || PPC64 || S390

drivers/char/Makefile

@@ -112,6 +112,9 @@ obj-$(CONFIG_PS3_FLASH)		+= ps3flash.o
 obj-$(CONFIG_JS_RTC)		+= js-rtc.o
 js-rtc-y = rtc.o
 
+davinci_rsz_driver-objs         := davinci_resizer_hw.o davinci_resizer.o
+obj-$(CONFIG_DAVINCI_RESIZER)   += davinci_rsz_driver.o
+
 # Files generated that shall be removed upon make clean
 clean-files := consolemap_deftbl.c defkeymap.c
 

drivers/char/davinci_resizer_hw.c

+/* *
+ * Copyright (C) 2006 Texas Instruments Inc
+ *
+ * This program is free software you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307  USA
+ */
+/* davinci_resizer_hw.c file */
+
+/*Header files*/
+#include <linux/autoconf.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/kernel.h>	/*     printk() */
+#include <linux/device.h>
+#include <linux/slab.h>		/*     kmalloc() */
+#include <linux/fs.h>		/*     everything... */
+#include <linux/errno.h>	/*     error codes     */
+#include <linux/types.h>	/*     size_t */
+#include <linux/mm.h>
+#include <linux/kdev_t.h>
+#include <linux/cdev.h>
+#include <linux/string.h>
+#include <linux/tty.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/err.h>
+#include <linux/proc_fs.h>
+#include <linux/sysctl.h>
+
+#ifdef CONFIG_PREEMPT_RT
+#include <linux/completion.h>
+#endif
+
+#include <asm/page.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+
+#include "davinci_resizer_hw.h"
+#include "davinci_resizer.h"
+
+extern struct device *rsz_device;
+
+/*
+ * functions definition
+ */
+void rsz_hardware_setup(channel_config_t * rsz_conf_chan);
+int rsz_enable(channel_config_t * rsz_conf_chan);
+int rsz_writebuffer_status(void);
+
+/*
+=====================rsz_hardware_setup===========================
+ Function	to set hardware	configuration registers
+*/
+
+void rsz_hardware_setup(channel_config_t * rsz_conf_chan)
+{
+	/* Counter to set the value     of horizonatl and vertical coeff */
+	int coeffcounter;
+	/* for getting the coefficient offset */
+	int coeffoffset = ZERO;
+
+	dev_dbg(rsz_device, "entering %s\n", __FUNCTION__);
+
+	/* clear the VPSS_PCR register buffer overflow bits     */
+	regw(0x003c0000, VPSS_PCR);
+
+	/* setting the hardware register rszcnt */
+	regw(rsz_conf_chan->register_config.rsz_cnt, RSZ_CNT);
+
+	dev_dbg(rsz_device, "RSZ CNT : %x	regr = %x \n",
+		rsz_conf_chan->register_config.rsz_cnt, regr(RSZ_CNT));
+
+	/* setting the hardware register instart */
+	regw(rsz_conf_chan->register_config.rsz_in_start, IN_START);
+
+	dev_dbg(rsz_device, "In START	%x regr	= %x\n",
+		rsz_conf_chan->register_config.rsz_in_start, regr(IN_START));
+
+	/* setting the hardware register insize */
+	regw(rsz_conf_chan->register_config.rsz_in_size, IN_SIZE);
+
+	dev_dbg(rsz_device, "In size %x regr = %x\n",
+		rsz_conf_chan->register_config.rsz_in_size, regr(IN_SIZE));
+	/* setting the hardware register outsize */
+	regw(rsz_conf_chan->register_config.rsz_out_size, OUT_SIZE);
+
+	dev_dbg(rsz_device, "out	size %x	regr = %x\n",
+		rsz_conf_chan->register_config.rsz_out_size, regr(OUT_SIZE));
+
+	/* setting the hardware register inaddress */
+	regw(rsz_conf_chan->register_config.rsz_sdr_inadd, SDR_INADD);
+
+	dev_dbg(rsz_device, "in address %x regr =	%x\n",
+		rsz_conf_chan->register_config.rsz_sdr_inadd, regr(SDR_INADD));
+	/* setting the hardware register in     offset */
+	regw(rsz_conf_chan->register_config.rsz_sdr_inoff, SDR_INOFF);
+
+	dev_dbg(rsz_device, "in offset %x	regr = %x\n",
+		rsz_conf_chan->register_config.rsz_sdr_inoff, regr(SDR_INOFF));
+	/* setting the hardware register in     offset */
+	/* setting the hardware register out address */
+	regw(rsz_conf_chan->register_config.rsz_sdr_outadd, SDR_OUTADD);
+
+	dev_dbg(rsz_device, "out	addrsess %x	regr = %x\n",
+		rsz_conf_chan->register_config.rsz_sdr_outadd,
+		regr(SDR_OUTADD));
+
+	/* setting the hardware register in     offset */
+	/* setting the hardware register out offset */
+	regw(rsz_conf_chan->register_config.rsz_sdr_outoff, SDR_OUTOFF);
+
+	dev_dbg(rsz_device, "out	offset %x regr = %x\n",
+		rsz_conf_chan->register_config.rsz_sdr_outoff,
+		regr(SDR_OUTOFF));
+
+	/* setting the hardware register yehn */
+	regw(rsz_conf_chan->register_config.rsz_yehn, YENH);
+
+	dev_dbg(rsz_device, "yehn	 %x	regr = %x\n",
+		rsz_conf_chan->register_config.rsz_yehn, regr(YENH));
+
+	/* setting the hardware registers     of coefficients */
+	for (coeffcounter = ZERO; coeffcounter < MAX_COEF_COUNTER;
+	     coeffcounter++) {
+		regw(rsz_conf_chan->register_config.
+		     rsz_coeff_horz[coeffcounter], ((HFILT10 + coeffoffset)));
+
+		regw(rsz_conf_chan->register_config.
+		     rsz_coeff_vert[coeffcounter], ((VFILT10 + coeffoffset)));
+		coeffoffset = coeffoffset + COEFF_ADDRESS_OFFSET;
+	}
+
+	dev_dbg(rsz_device, "leaving %s\n", __FUNCTION__);
+
+}
+
+/*
+=====================rsz_enable===========================
+ Function to enable	the	resizer
+*/
+int rsz_enable(channel_config_t * rsz_conf_chan)
+{
+
+	dev_dbg(rsz_device, "entering %s\n", __FUNCTION__);
+
+	/* Eanbling the resizer the setting enable bit */
+	rsz_conf_chan->register_config.rsz_pcr =
+	    BITSET(rsz_conf_chan->register_config.rsz_pcr, SET_ENABLE_BIT);
+
+	regw(rsz_conf_chan->register_config.rsz_pcr, PCR);
+
+	dev_dbg(rsz_device, "the value of pcr is %x \n", regr(PCR));
+
+	regw(0x003c0000, VPSS_PCR);
+
+	dev_dbg(rsz_device, "leaving %s\n", __FUNCTION__);
+
+	return SUCESS;
+}
+
+int rsz_writebuffer_status(void)
+{
+	dev_dbg(rsz_device, "VPSS_PCR: %x\n", regr(VPSS_PCR));
+	return ((regr(VPSS_PCR) >> 18) & 0xF);
+}

drivers/char/davinci_resizer_hw.h

+/* *
+ * Copyright (C) 2006 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+/* davinci_resizer_hw.h file */
+#ifndef	DAVINCI_RESIZER_HW
+#define	DAVINCI_RESIZER_HW
+
+/* Register	offset mapping*/
+#define	RESIZER_IOBASE_VADDR	IO_ADDRESS(0x01C70C00)
+#define	PID					0x0000
+#define	PCR					0x0004
+#define	RSZ_CNT					0x0008
+#define	OUT_SIZE				0x000C
+#define	IN_START				0x0010
+#define	IN_SIZE					0x0014
+#define	SDR_INADD				0x0018
+#define	SDR_INOFF				0x001C
+#define	SDR_OUTADD				0x0020
+#define	SDR_OUTOFF				0x0024
+#define	HFILT10					0x0028
+#define	VFILT10					0x0068
+#define	COEFF_ADDRESS_OFFSET			0x04
+#define	YENH					0x00A8
+
+#define	VPSS_PCR				(0x3404-0x0C00)
+#define	SDR_REQ_EXP				(0x3508-0x0C00)
+
+/* Register	read/write */
+#define	regw(val,reg)		outl(val,((reg)+ RESIZER_IOBASE_VADDR))
+#define	regr(reg)		inl((reg)+RESIZER_IOBASE_VADDR)
+
+#endif