Commit cbd347ad authored by Alexander Duyck's avatar Alexander Duyck Committed by David S. Miller

igb: remove unused defines

This patch removes all of the unused defines from the .h files contained in
igb.  For some defines there was a use and so I plugged them into the correct
locations.
Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bc1cbd34
...@@ -58,9 +58,6 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); ...@@ -58,9 +58,6 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
E1000_EICR_RX_QUEUE2 | \ E1000_EICR_RX_QUEUE2 | \
E1000_EICR_RX_QUEUE3) E1000_EICR_RX_QUEUE3)
#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
/* Receive Descriptor - Advanced */ /* Receive Descriptor - Advanced */
...@@ -95,12 +92,6 @@ union e1000_adv_rx_desc { ...@@ -95,12 +92,6 @@ union e1000_adv_rx_desc {
#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
#define E1000_RXDADV_HDRBUFLEN_SHIFT 5 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
/* RSS Hash results */
/* RSS Packet Types as indicated in the receive descriptor */
#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
/* Transmit Descriptor - Advanced */ /* Transmit Descriptor - Advanced */
union e1000_adv_tx_desc { union e1000_adv_tx_desc {
struct { struct {
...@@ -150,10 +141,7 @@ struct e1000_adv_tx_context_desc { ...@@ -150,10 +141,7 @@ struct e1000_adv_tx_context_desc {
#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
/* Direct Cache Access (DCA) definitions */ /* Direct Cache Access (DCA) definitions */
#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
......
This diff is collapsed.
...@@ -82,13 +82,8 @@ enum e1000_mng_mode { ...@@ -82,13 +82,8 @@ enum e1000_mng_mode {
#define E1000_FWSM_MODE_MASK 0xE #define E1000_FWSM_MODE_MASK 0xE
#define E1000_FWSM_MODE_SHIFT 1 #define E1000_FWSM_MODE_SHIFT 1
#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
#define E1000_HICR_EN 0x01 /* Enable bit - RO */
/* Driver sets this bit when done to put command in RAM */
#define E1000_HICR_C 0x02
extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
......
...@@ -39,9 +39,6 @@ static s32 igb_wait_autoneg(struct e1000_hw *hw); ...@@ -39,9 +39,6 @@ static s32 igb_wait_autoneg(struct e1000_hw *hw);
/* Cable length tables */ /* Cable length tables */
static const u16 e1000_m88_cable_length_table[] = static const u16 e1000_m88_cable_length_table[] =
{ 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
(sizeof(e1000_m88_cable_length_table) / \
sizeof(e1000_m88_cable_length_table[0]))
static const u16 e1000_igp_2_cable_length_table[] = static const u16 e1000_igp_2_cable_length_table[] =
{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
......
...@@ -73,7 +73,6 @@ ...@@ -73,7 +73,6 @@
#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
/* IEEE 1588 TIMESYNCH */ /* IEEE 1588 TIMESYNCH */
...@@ -178,7 +177,6 @@ enum { ...@@ -178,7 +177,6 @@ enum {
: (0x0E018 + ((_n) * 0x40))) : (0x0E018 + ((_n) * 0x40)))
#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \
: (0x0E028 + ((_n) * 0x40))) : (0x0E028 + ((_n) * 0x40)))
#define E1000_TARC(_n) (0x03840 + (_n << 8))
#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \
...@@ -301,9 +299,7 @@ enum { ...@@ -301,9 +299,7 @@ enum {
#define E1000_MANC 0x05820 /* Management Control - RW */ #define E1000_MANC 0x05820 /* Management Control - RW */
#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
#define E1000_HOST_IF 0x08800 /* Host Interface */
#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
#define E1000_CCMCTL 0x05B48 /* CCM Control Register */ #define E1000_CCMCTL 0x05B48 /* CCM Control Register */
#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
...@@ -311,9 +307,7 @@ enum { ...@@ -311,9 +307,7 @@ enum {
#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
#define E1000_SWSM 0x05B50 /* SW Semaphore */ #define E1000_SWSM 0x05B50 /* SW Semaphore */
#define E1000_FWSM 0x05B54 /* FW Semaphore */ #define E1000_FWSM 0x05B54 /* FW Semaphore */
#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
#define E1000_HICR 0x08F00 /* Host Inteface Control */
/* RSS registers */ /* RSS registers */
#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
...@@ -322,14 +316,6 @@ enum { ...@@ -322,14 +316,6 @@ enum {
#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
/* MSI-X Allocation Register (_i) - RW */ /* MSI-X Allocation Register (_i) - RW */
#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4))
/* MSI-X Table entry addr low reg 0 - RW */
#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10))
/* MSI-X Table entry addr upper reg 0 - RW */
#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10))
/* MSI-X Table entry message reg 0 - RW */
#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10))
/* MSI-X Table entry vector ctrl reg 0 - RW */
#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10))
/* Redirection Table - RW Array */ /* Redirection Table - RW Array */
#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) #define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
......
...@@ -40,17 +40,9 @@ ...@@ -40,17 +40,9 @@
struct igb_adapter; struct igb_adapter;
/* Interrupt defines */
#define IGB_MIN_DYN_ITR 3000
#define IGB_MAX_DYN_ITR 96000
/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648 #define IGB_START_ITR 648
#define IGB_DYN_ITR_PACKET_THRESHOLD 2
#define IGB_DYN_ITR_LENGTH_LOW 200
#define IGB_DYN_ITR_LENGTH_HIGH 1000
/* TX/RX descriptor defines */ /* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD 256 #define IGB_DEFAULT_TXD 256
#define IGB_MIN_TXD 80 #define IGB_MIN_TXD 80
...@@ -92,8 +84,6 @@ struct igb_adapter; ...@@ -92,8 +84,6 @@ struct igb_adapter;
#define IGB_RXBUFFER_512 512 #define IGB_RXBUFFER_512 512
#define IGB_RXBUFFER_1024 1024 #define IGB_RXBUFFER_1024 1024
#define IGB_RXBUFFER_2048 2048 #define IGB_RXBUFFER_2048 2048
#define IGB_RXBUFFER_4096 4096
#define IGB_RXBUFFER_8192 8192
#define IGB_RXBUFFER_16384 16384 #define IGB_RXBUFFER_16384 16384
/* Packet Buffer allocations */ /* Packet Buffer allocations */
...@@ -286,10 +276,9 @@ struct igb_adapter { ...@@ -286,10 +276,9 @@ struct igb_adapter {
}; };
#define IGB_FLAG_HAS_MSI (1 << 0) #define IGB_FLAG_HAS_MSI (1 << 0)
#define IGB_FLAG_MSI_ENABLE (1 << 1) #define IGB_FLAG_DCA_ENABLED (1 << 1)
#define IGB_FLAG_DCA_ENABLED (1 << 2) #define IGB_FLAG_QUAD_PORT_A (1 << 2)
#define IGB_FLAG_QUAD_PORT_A (1 << 3) #define IGB_FLAG_NEED_CTX_IDX (1 << 3)
#define IGB_FLAG_NEED_CTX_IDX (1 << 4)
enum e1000_state_t { enum e1000_state_t {
__IGB_TESTING, __IGB_TESTING,
......
...@@ -1366,8 +1366,7 @@ static int igb_setup_desc_rings(struct igb_adapter *adapter) ...@@ -1366,8 +1366,7 @@ static int igb_setup_desc_rings(struct igb_adapter *adapter)
wr32(E1000_RDH(0), 0); wr32(E1000_RDH(0), 0);
wr32(E1000_RDT(0), 0); wr32(E1000_RDT(0), 0);
rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 | rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
E1000_RCTL_RDMTS_HALF |
(adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
wr32(E1000_RCTL, rctl); wr32(E1000_RCTL, rctl);
wr32(E1000_SRRCTL(0), 0); wr32(E1000_SRRCTL(0), 0);
...@@ -1855,9 +1854,6 @@ static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) ...@@ -1855,9 +1854,6 @@ static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
return 0; return 0;
} }
/* toggle LED 4 times per second = 2 "blinks" per second */
#define IGB_ID_INTERVAL (HZ/4)
/* bit defines for adapter->led_status */ /* bit defines for adapter->led_status */
#define IGB_LED_ON 0 #define IGB_LED_ON 0
......
...@@ -1305,7 +1305,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, ...@@ -1305,7 +1305,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
hw->fc.original_type = e1000_fc_default; hw->fc.original_type = e1000_fc_default;
hw->fc.type = e1000_fc_default; hw->fc.type = e1000_fc_default;
adapter->itr_setting = 3; adapter->itr_setting = IGB_DEFAULT_ITR;
adapter->itr = IGB_START_ITR; adapter->itr = IGB_START_ITR;
igb_validate_mdi_setting(hw); igb_validate_mdi_setting(hw);
...@@ -1366,7 +1366,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, ...@@ -1366,7 +1366,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
dev_info(&pdev->dev, "DCA enabled\n"); dev_info(&pdev->dev, "DCA enabled\n");
/* Always use CB2 mode, difference is masked /* Always use CB2 mode, difference is masked
* in the CB driver. */ * in the CB driver. */
wr32(E1000_DCA_CTRL, 2); wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
igb_setup_dca(adapter); igb_setup_dca(adapter);
} }
#endif #endif
...@@ -1498,7 +1498,7 @@ static void __devexit igb_remove(struct pci_dev *pdev) ...@@ -1498,7 +1498,7 @@ static void __devexit igb_remove(struct pci_dev *pdev)
dev_info(&pdev->dev, "DCA disabled\n"); dev_info(&pdev->dev, "DCA disabled\n");
dca_remove_requester(&pdev->dev); dca_remove_requester(&pdev->dev);
adapter->flags &= ~IGB_FLAG_DCA_ENABLED; adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
wr32(E1000_DCA_CTRL, 1); wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
} }
#endif #endif
...@@ -3058,8 +3058,6 @@ static int igb_maybe_stop_tx(struct net_device *netdev, ...@@ -3058,8 +3058,6 @@ static int igb_maybe_stop_tx(struct net_device *netdev,
return __igb_maybe_stop_tx(netdev, tx_ring, size); return __igb_maybe_stop_tx(netdev, tx_ring, size);
} }
#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
static int igb_xmit_frame_ring_adv(struct sk_buff *skb, static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
struct net_device *netdev, struct net_device *netdev,
struct igb_ring *tx_ring) struct igb_ring *tx_ring)
...@@ -3586,7 +3584,7 @@ static int __igb_notify_dca(struct device *dev, void *data) ...@@ -3586,7 +3584,7 @@ static int __igb_notify_dca(struct device *dev, void *data)
break; break;
/* Always use CB2 mode, difference is masked /* Always use CB2 mode, difference is masked
* in the CB driver. */ * in the CB driver. */
wr32(E1000_DCA_CTRL, 2); wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
if (dca_add_requester(dev) == 0) { if (dca_add_requester(dev) == 0) {
adapter->flags |= IGB_FLAG_DCA_ENABLED; adapter->flags |= IGB_FLAG_DCA_ENABLED;
dev_info(&adapter->pdev->dev, "DCA enabled\n"); dev_info(&adapter->pdev->dev, "DCA enabled\n");
...@@ -3601,7 +3599,7 @@ static int __igb_notify_dca(struct device *dev, void *data) ...@@ -3601,7 +3599,7 @@ static int __igb_notify_dca(struct device *dev, void *data)
dca_remove_requester(dev); dca_remove_requester(dev);
dev_info(&adapter->pdev->dev, "DCA disabled\n"); dev_info(&adapter->pdev->dev, "DCA disabled\n");
adapter->flags &= ~IGB_FLAG_DCA_ENABLED; adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
wr32(E1000_DCA_CTRL, 1); wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
} }
break; break;
} }
......
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