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Commit c24bb5b9 authored by Ramesh Gupta's avatar Ramesh Gupta Committed by Hari Kanigeri
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OMAP4 syslink ducati header file format 

This patch fixes coding style issues.
Signed-off-by: default avatarRamesh Gupta G <grgupta@ti.com>
parent f137f09f
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Showing with 124 additions and 276 deletions
arch/arm/plat-omap/include/syslink/MMUAccInt.h
View file @ c24bb5b9
/*
* MMUAccInt.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
* Syslink ducati driver support for OMAP Processors.
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Copyright (C) 2008-2009 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -20,159 +20,159 @@
/* Register offset address definitions */
#define MMU_MMU_REVISION_OFFSET 0x0
#define MMU_MMU_SYSCONFIG_OFFSET 0x10
#define MMU_MMU_SYSSTATUS_OFFSET 014
#define MMU_MMU_IRQSTATUS_OFFSET 0x18
#define MMU_MMU_IRQENABLE_OFFSET 0x1c
#define MMU_MMU_WALKING_ST_OFFSET 0x40
#define MMU_MMU_CNTL_OFFSET 0x44
#define MMU_MMU_FAULT_AD_OFFSET 0x48
#define MMU_MMU_TTB_OFFSET 0x4c
#define MMU_MMU_LOCK_OFFSET 0x50
#define MMU_MMU_LD_TLB_OFFSET 0x54
#define MMU_MMU_CAM_OFFSET 0x58
#define MMU_MMU_RAM_OFFSET 0x5c
#define MMU_MMU_GFLUSH_OFFSET 0x60
#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64
#define MMU_MMU_READ_CAM_OFFSET 0x68
#define MMU_MMU_READ_RAM_OFFSET 0x6c
#define MMU_MMU_EMU_FAULT_AD_OFFSET 0x70
#define MMU_MMU_REVISION_OFFSET 0x0
#define MMU_MMU_SYSCONFIG_OFFSET 0x10
#define MMU_MMU_SYSSTATUS_OFFSET 014
#define MMU_MMU_IRQSTATUS_OFFSET 0x18
#define MMU_MMU_IRQENABLE_OFFSET 0x1c
#define MMU_MMU_WALKING_ST_OFFSET 0x40
#define MMU_MMU_CNTL_OFFSET 0x44
#define MMU_MMU_FAULT_AD_OFFSET 0x48
#define MMU_MMU_TTB_OFFSET 0x4c
#define MMU_MMU_LOCK_OFFSET 0x50
#define MMU_MMU_LD_TLB_OFFSET 0x54
#define MMU_MMU_CAM_OFFSET 0x58
#define MMU_MMU_RAM_OFFSET 0x5c
#define MMU_MMU_GFLUSH_OFFSET 0x60
#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64
#define MMU_MMU_READ_CAM_OFFSET 0x68
#define MMU_MMU_READ_RAM_OFFSET 0x6c
#define MMU_MMU_EMU_FAULT_AD_OFFSET 0x70
/* Bitfield mask and offset declarations */
#define MMU_MMU_REVISION_Rev_MASK 0xff
#define MMU_MMU_REVISION_Rev_OFFSET 0
#define MMU_MMU_REVISION_Rev_MASK 0xff
#define MMU_MMU_REVISION_Rev_OFFSET 0
#define MMU_MMU_SYSCONFIG_ClockActivity_MASK 0x300
#define MMU_MMU_SYSCONFIG_ClockActivity_OFFSET 8
#define MMU_MMU_SYSCONFIG_ClockActivity_MASK 0x300
#define MMU_MMU_SYSCONFIG_ClockActivity_OFFSET 8
#define MMU_MMU_SYSCONFIG_IdleMode_MASK 0x18
#define MMU_MMU_SYSCONFIG_IdleMode_OFFSET 3
#define MMU_MMU_SYSCONFIG_IdleMode_MASK 0x18
#define MMU_MMU_SYSCONFIG_IdleMode_OFFSET 3
#define MMU_MMU_SYSCONFIG_SoftReset_MASK 0x2
#define MMU_MMU_SYSCONFIG_SoftReset_OFFSET 1
#define MMU_MMU_SYSCONFIG_SoftReset_MASK 0x2
#define MMU_MMU_SYSCONFIG_SoftReset_OFFSET 1
#define MMU_MMU_SYSCONFIG_AutoIdle_MASK 0x1
#define MMU_MMU_SYSCONFIG_AutoIdle_OFFSET 0
#define MMU_MMU_SYSCONFIG_AutoIdle_MASK 0x1
#define MMU_MMU_SYSCONFIG_AutoIdle_OFFSET 0
#define MMU_MMU_SYSSTATUS_ResetDone_MASK 0x1
#define MMU_MMU_SYSSTATUS_ResetDone_OFFSET 0
#define MMU_MMU_SYSSTATUS_ResetDone_MASK 0x1
#define MMU_MMU_SYSSTATUS_ResetDone_OFFSET 0
#define MMU_MMU_IRQSTATUS_MultiHitFault_MASK 0x10
#define MMU_MMU_IRQSTATUS_MultiHitFault_OFFSET 4
#define MMU_MMU_IRQSTATUS_MultiHitFault_MASK 0x10
#define MMU_MMU_IRQSTATUS_MultiHitFault_OFFSET 4
#define MMU_MMU_IRQSTATUS_TableWalkFault_MASK 0x8
#define MMU_MMU_IRQSTATUS_TableWalkFault_OFFSET 3
#define MMU_MMU_IRQSTATUS_TableWalkFault_MASK 0x8
#define MMU_MMU_IRQSTATUS_TableWalkFault_OFFSET 3
#define MMU_MMU_IRQSTATUS_EMUMiss_MASK 0x4
#define MMU_MMU_IRQSTATUS_EMUMiss_OFFSET 2
#define MMU_MMU_IRQSTATUS_EMUMiss_MASK 0x4
#define MMU_MMU_IRQSTATUS_EMUMiss_OFFSET 2
#define MMU_MMU_IRQSTATUS_TranslationFault_MASK 0x2
#define MMU_MMU_IRQSTATUS_TranslationFault_OFFSET 1
#define MMU_MMU_IRQSTATUS_TranslationFault_MASK 0x2
#define MMU_MMU_IRQSTATUS_TranslationFault_OFFSET 1
#define MMU_MMU_IRQSTATUS_TLBMiss_MASK 0x1
#define MMU_MMU_IRQSTATUS_TLBMiss_OFFSET 0
#define MMU_MMU_IRQSTATUS_TLBMiss_MASK 0x1
#define MMU_MMU_IRQSTATUS_TLBMiss_OFFSET 0
#define MMU_MMU_IRQENABLE_MultiHitFault_MASK 0x10
#define MMU_MMU_IRQENABLE_MultiHitFault_OFFSET 4
#define MMU_MMU_IRQENABLE_MultiHitFault_MASK 0x10
#define MMU_MMU_IRQENABLE_MultiHitFault_OFFSET 4
#define MMU_MMU_IRQENABLE_TableWalkFault_MASK 0x8
#define MMU_MMU_IRQENABLE_TableWalkFault_OFFSET 3
#define MMU_MMU_IRQENABLE_TableWalkFault_MASK 0x8
#define MMU_MMU_IRQENABLE_TableWalkFault_OFFSET 3
#define MMU_MMU_IRQENABLE_EMUMiss_MASK 0x4
#define MMU_MMU_IRQENABLE_EMUMiss_OFFSET 2
#define MMU_MMU_IRQENABLE_EMUMiss_MASK 0x4
#define MMU_MMU_IRQENABLE_EMUMiss_OFFSET 2
#define MMU_MMU_IRQENABLE_TranslationFault_MASK 0x2
#define MMU_MMU_IRQENABLE_TranslationFault_OFFSET 1
#define MMU_MMU_IRQENABLE_TranslationFault_MASK 0x2
#define MMU_MMU_IRQENABLE_TranslationFault_OFFSET 1
#define MMU_MMU_IRQENABLE_TLBMiss_MASK 0x1
#define MMU_MMU_IRQENABLE_TLBMiss_OFFSET 0
#define MMU_MMU_IRQENABLE_TLBMiss_MASK 0x1
#define MMU_MMU_IRQENABLE_TLBMiss_OFFSET 0
#define MMU_MMU_WALKING_ST_TWLRunning_MASK 0x1
#define MMU_MMU_WALKING_ST_TWLRunning_OFFSET 0
#define MMU_MMU_WALKING_ST_TWLRunning_MASK 0x1
#define MMU_MMU_WALKING_ST_TWLRunning_OFFSET 0
#define MMU_MMU_CNTL_EmuTLBUpdate_MASK 0x8
#define MMU_MMU_CNTL_EmuTLBUpdate_OFFSET 3
#define MMU_MMU_CNTL_EmuTLBUpdate_MASK 0x8
#define MMU_MMU_CNTL_EmuTLBUpdate_OFFSET 3
#define MMU_MMU_CNTL_TWLEnable_MASK 0x4
#define MMU_MMU_CNTL_TWLEnable_OFFSET 2
#define MMU_MMU_CNTL_TWLEnable_MASK 0x4
#define MMU_MMU_CNTL_TWLEnable_OFFSET 2
#define MMU_MMU_CNTL_MMUEnable_MASK 0x2
#define MMU_MMU_CNTL_MMUEnable_OFFSET 1
#define MMU_MMU_CNTL_MMUEnable_MASK 0x2
#define MMU_MMU_CNTL_MMUEnable_OFFSET 1
#define MMU_MMU_FAULT_AD_FaultAddress_MASK 0xffffffff
#define MMU_MMU_FAULT_AD_FaultAddress_OFFSET 0
#define MMU_MMU_FAULT_AD_FaultAddress_OFFSET 0
#define MMU_MMU_TTB_TTBAddress_MASK 0xffffff00
#define MMU_MMU_TTB_TTBAddress_OFFSET 8
#define MMU_MMU_LOCK_BaseValue_MASK 0xfc00
#define MMU_MMU_LOCK_BaseValue_OFFSET 10
#define MMU_MMU_LOCK_BaseValue_OFFSET 10
#define MMU_MMU_LOCK_CurrentVictim_MASK 0x3f0
#define MMU_MMU_LOCK_CurrentVictim_OFFSET 4
#define MMU_MMU_LOCK_CurrentVictim_MASK 0x3f0
#define MMU_MMU_LOCK_CurrentVictim_OFFSET 4
#define MMU_MMU_LD_TLB_LdTLBItem_MASK 0x1
#define MMU_MMU_LD_TLB_LdTLBItem_OFFSET 0
#define MMU_MMU_LD_TLB_LdTLBItem_MASK 0x1
#define MMU_MMU_LD_TLB_LdTLBItem_OFFSET 0
#define MMU_MMU_CAM_VATag_MASK 0xfffff000
#define MMU_MMU_CAM_VATag_OFFSET 12
#define MMU_MMU_CAM_VATag_MASK 0xfffff000
#define MMU_MMU_CAM_VATag_OFFSET 12
#define MMU_MMU_CAM_P_MASK 0x8
#define MMU_MMU_CAM_P_OFFSET 3
#define MMU_MMU_CAM_P_MASK 0x8
#define MMU_MMU_CAM_P_OFFSET 3
#define MMU_MMU_CAM_V_MASK 0x4
#define MMU_MMU_CAM_V_OFFSET 2
#define MMU_MMU_CAM_V_MASK 0x4
#define MMU_MMU_CAM_V_OFFSET 2
#define MMU_MMU_CAM_PageSize_MASK 0x3
#define MMU_MMU_CAM_PageSize_OFFSET 0
#define MMU_MMU_CAM_PageSize_MASK 0x3
#define MMU_MMU_CAM_PageSize_OFFSET 0
#define MMU_MMU_RAM_PhysicalAddress_MASK 0xfffff000
#define MMU_MMU_RAM_PhysicalAddress_OFFSET 12
#define MMU_MMU_RAM_PhysicalAddress_MASK 0xfffff000
#define MMU_MMU_RAM_PhysicalAddress_OFFSET 12
#define MMU_MMU_RAM_Endianness_MASK 0x200
#define MMU_MMU_RAM_Endianness_OFFSET 9
#define MMU_MMU_RAM_Endianness_MASK 0x200
#define MMU_MMU_RAM_Endianness_OFFSET 9
#define MMU_MMU_RAM_ElementSize_MASK 0x180
#define MMU_MMU_RAM_ElementSize_OFFSET 7
#define MMU_MMU_RAM_ElementSize_MASK 0x180
#define MMU_MMU_RAM_ElementSize_OFFSET 7
#define MMU_MMU_RAM_Mixed_MASK 0x40
#define MMU_MMU_RAM_Mixed_OFFSET 6
#define MMU_MMU_RAM_Mixed_MASK 0x40
#define MMU_MMU_RAM_Mixed_OFFSET 6
#define MMU_MMU_GFLUSH_GlobalFlush_MASK 0x1
#define MMU_MMU_GFLUSH_GlobalFlush_OFFSET 0
#define MMU_MMU_GFLUSH_GlobalFlush_MASK 0x1
#define MMU_MMU_GFLUSH_GlobalFlush_OFFSET 0
#define MMU_MMU_FLUSH_ENTRY_FlushEntry_MASK 0x1
#define MMU_MMU_FLUSH_ENTRY_FlushEntry_OFFSET 0
#define MMU_MMU_FLUSH_ENTRY_FlushEntry_MASK 0x1
#define MMU_MMU_FLUSH_ENTRY_FlushEntry_OFFSET 0
#define MMU_MMU_READ_CAM_VATag_MASK 0xfffff000
#define MMU_MMU_READ_CAM_VATag_OFFSET 12
#define MMU_MMU_READ_CAM_VATag_MASK 0xfffff000
#define MMU_MMU_READ_CAM_VATag_OFFSET 12
#define MMU_MMU_READ_CAM_P_MASK 0x8
#define MMU_MMU_READ_CAM_P_OFFSET 3
#define MMU_MMU_READ_CAM_P_MASK 0x8
#define MMU_MMU_READ_CAM_P_OFFSET 3
#define MMU_MMU_READ_CAM_V_MASK 0x4
#define MMU_MMU_READ_CAM_V_OFFSET 2
#define MMU_MMU_READ_CAM_V_MASK 0x4
#define MMU_MMU_READ_CAM_V_OFFSET 2
#define MMU_MMU_READ_CAM_PageSize_MASK 0x3
#define MMU_MMU_READ_CAM_PageSize_OFFSET 0
#define MMU_MMU_READ_CAM_PageSize_MASK 0x3
#define MMU_MMU_READ_CAM_PageSize_OFFSET 0
#define MMU_MMU_READ_RAM_PhysicalAddress_MASK 0xfffff000
#define MMU_MMU_READ_RAM_PhysicalAddress_OFFSET 12
#define MMU_MMU_READ_RAM_PhysicalAddress_MASK 0xfffff000
#define MMU_MMU_READ_RAM_PhysicalAddress_OFFSET 12
#define MMU_MMU_READ_RAM_Endianness_MASK 0x200
#define MMU_MMU_READ_RAM_Endianness_OFFSET 9
#define MMU_MMU_READ_RAM_Endianness_MASK 0x200
#define MMU_MMU_READ_RAM_Endianness_OFFSET 9
#define MMU_MMU_READ_RAM_ElementSize_MASK 0x180
#define MMU_MMU_READ_RAM_ElementSize_OFFSET 7
#define MMU_MMU_READ_RAM_ElementSize_MASK 0x180
#define MMU_MMU_READ_RAM_ElementSize_OFFSET 7
#define MMU_MMU_READ_RAM_Mixed_MASK 0x40
#define MMU_MMU_READ_RAM_Mixed_OFFSET 6
#define MMU_MMU_READ_RAM_Mixed_MASK 0x40
#define MMU_MMU_READ_RAM_Mixed_OFFSET 6
#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_MASK 0xffffffff
#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_OFFSET 0
#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_MASK 0xffffffff
#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_OFFSET 0
#endif /* _MMU_ACC_INT_H */
/* EOF */
......
arch/arm/plat-omap/include/syslink/MMURegAcM.h
View file @ c24bb5b9
/*
* MMURegAcM.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
* Notify driver support for OMAP Processors.
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Copyright (C) 2008-2009 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -14,7 +14,6 @@
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _MMU_REG_ACM_H
#define _MMU_REG_ACM_H
......@@ -24,9 +23,9 @@
#include "MMUAccInt.h"
/*****************************************************************************
/*
* EXPORTED DEFINITIONS
******************************************************************************
*
*/
#if defined(USE_LEVEL_1_MACROS)
......@@ -36,9 +35,6 @@
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_SYSCONFIG_OFFSET))
/********************************************************************/
#define MMUMMU_SYSCONFIGWriteRegister32(base_address, value)\
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
......@@ -46,13 +42,9 @@
WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
}
#define MMUMMU_SYSCONFIGClockActivityGet32(var)\
((u32)(((var) & MMU_MMU_SYSCONFIG_ClockActivity_MASK) >> MMU_MMU_SYSCONFIG_ClockActivity_OFFSET))
((u32)(((var) & MMU_MMU_SYSCONFIG_ClockActivity_MASK)\
>> MMU_MMU_SYSCONFIG_ClockActivity_OFFSET))
#define mmu_sisconf_auto_idle_set32(var, value)\
((((var) & ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK)) |\
......@@ -63,9 +55,6 @@
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_IRQSTATUS_OFFSET))
/********************************************************************/
#define MMUMMU_IRQSTATUSWriteRegister32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
......@@ -78,9 +67,6 @@
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_IRQENABLE_OFFSET))
/********************************************************************/
#define MMUMMU_IRQENABLEWriteRegister32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
......@@ -88,15 +74,10 @@
WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
}
/********************************************************************/
#define MMUMMU_IRQENABLETableWalkFaultSet32(var, value)\
((((var) & ~(MMU_MMU_IRQENABLE_TableWalkFault_MASK)) |\
(((value) << MMU_MMU_IRQENABLE_TableWalkFault_OFFSET) &\
MMU_MMU_IRQENABLE_TableWalkFault_MASK)))
/********************************************************************/
#define MMUMMU_IRQENABLETranslationFaultRead32(base_address)\
((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\
......@@ -111,18 +92,12 @@
MMU_MMU_IRQENABLE_TranslationFault_MASK)))
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissRead32(base_address)\
((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\
MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
MMU_MMU_IRQENABLE_TLBMiss_OFFSET))
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissReadIsTrMissIntM32(base_address)\
((MMUMMU_IRQENABLETLBMissTrMissIntM == (MMUMMU_IRQENABLETLBMissE)\
(((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\
......@@ -130,9 +105,6 @@
MMU_MMU_IRQENABLE_TLBMiss_OFFSET)))
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissReadIsTrMissGInt32(base_address)\
((MMUMMU_IRQENABLETLBMissTrMissGInt == (MMUMMU_IRQENABLETLBMissE)\
(((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\
......@@ -140,32 +112,21 @@
MMU_MMU_IRQENABLE_TLBMiss_OFFSET)))
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissGet32(var)\
((u32)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >> MMU_MMU_IRQENABLE_TLBMiss_OFFSET))
/********************************************************************/
((u32)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK)\
>> MMU_MMU_IRQENABLE_TLBMiss_OFFSET))
#define MMUMMU_IRQENABLETLBMissIsTrMissIntM32(var)\
((MMUMMU_IRQENABLETLBMissTrMissIntM == (MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
((MMUMMU_IRQENABLETLBMissTrMissIntM == \
(MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
MMU_MMU_IRQENABLE_TLBMiss_OFFSET)))
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissIsTrMissGInt32(var)\
((MMUMMU_IRQENABLETLBMissTrMissGInt == (MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
((MMUMMU_IRQENABLETLBMissTrMissGInt ==\
(MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
MMU_MMU_IRQENABLE_TLBMiss_OFFSET)))
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissWrite32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
......@@ -179,9 +140,6 @@
}
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissWriteTrMissIntM32(base_address)\
{\
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
......@@ -194,9 +152,6 @@
}
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissWriteTrMissGInt32(base_address)\
{\
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
......@@ -209,9 +164,6 @@
}
/********************************************************************/
#define MMUMMU_IRQENABLETLBMissSet32(var, value)\
((((var) & ~(MMU_MMU_IRQENABLE_TLBMiss_MASK)) |\
(((value) << MMU_MMU_IRQENABLE_TLBMiss_OFFSET) &\
......@@ -261,32 +213,19 @@
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FAULT_AD_OFFSET))
/********************************************************************/
#define MMUMMU_FAULT_ADFaultAddressRead32(base_address)\
((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_FAULT_AD_OFFSET)))) &\
MMU_MMU_FAULT_AD_FaultAddress_MASK) >>\
MMU_MMU_FAULT_AD_FaultAddress_OFFSET))
/********************************************************************/
#define MMUMMU_FAULT_ADFaultAddressGet32(var)\
((u32)(((var) & MMU_MMU_FAULT_AD_FaultAddress_MASK) >> MMU_MMU_FAULT_AD_FaultAddress_OFFSET))
/********************************************************************/
((u32)(((var) & MMU_MMU_FAULT_AD_FaultAddress_MASK)\
>> MMU_MMU_FAULT_AD_FaultAddress_OFFSET))
#define MMUMMU_TTBReadRegister32(base_address)\
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_TTB_OFFSET))
/********************************************************************/
#define MMUMMU_TTBWriteRegister32(base_address, value)\
{\
const u32 offset = MMU_MMU_TTB_OFFSET;\
......@@ -294,24 +233,14 @@
WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
}
/********************************************************************/
#define MMUMMU_TTBTTBAddressRead32(base_address)\
((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_TTB_OFFSET)))) &\
MMU_MMU_TTB_TTBAddress_MASK) >>\
MMU_MMU_TTB_TTBAddress_OFFSET))
/********************************************************************/
#define MMUMMU_TTBTTBAddressGet32(var)\
((u32)(((var) & MMU_MMU_TTB_TTBAddress_MASK) >> MMU_MMU_TTB_TTBAddress_OFFSET))
/********************************************************************/
((u32)(((var) & MMU_MMU_TTB_TTBAddress_MASK)\
>> MMU_MMU_TTB_TTBAddress_OFFSET))
#define MMUMMU_TTBTTBAddressWrite32(base_address, value)\
......@@ -326,26 +255,15 @@
WR_MEM_32_VOLATILE(base_address+offset, newValue);\
}
/********************************************************************/
#define MMUMMU_TTBTTBAddressSet32(var, value)\
((((var) & ~(MMU_MMU_TTB_TTBAddress_MASK)) |\
(((value) << MMU_MMU_TTB_TTBAddress_OFFSET) &\
MMU_MMU_TTB_TTBAddress_MASK)))
/********************************************************************/
#define mmu_lckread_reg_32(base_address)\
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_LOCK_OFFSET))
/********************************************************************/
#define mmu_lck_write_reg32(base_address, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
......@@ -354,23 +272,13 @@
}
/********************************************************************/
#define MMUMMU_LOCKBaseValueRead32(base_address)\
((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
MMU_MMU_LOCK_BaseValue_MASK) >>\
MMU_MMU_LOCK_BaseValue_OFFSET))
/********************************************************************/
#define MMUMMU_LOCKBaseValueGet32(var)\
((u32)(((var) & MMU_MMU_LOCK_BaseValue_MASK) >> MMU_MMU_LOCK_BaseValue_OFFSET))
/********************************************************************/
((u32)(((var) & MMU_MMU_LOCK_BaseValue_MASK)\
>> MMU_MMU_LOCK_BaseValue_OFFSET))
#define MMUMMU_LOCKBaseValueWrite32(base_address, value)\
......@@ -386,32 +294,20 @@
}
/********************************************************************/
#define MMUMMU_LOCKBaseValueSet32(var, value)\
((((var) & ~(MMU_MMU_LOCK_BaseValue_MASK)) |\
(((value) << MMU_MMU_LOCK_BaseValue_OFFSET) &\
MMU_MMU_LOCK_BaseValue_MASK)))
/********************************************************************/
#define MMUMMU_LOCKCurrentVictimRead32(base_address)\
((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
MMU_MMU_LOCK_CurrentVictim_MASK) >>\
MMU_MMU_LOCK_CurrentVictim_OFFSET))
/********************************************************************/
#define MMUMMU_LOCKCurrentVictimGet32(var)\
((u32)(((var) & MMU_MMU_LOCK_CurrentVictim_MASK) >> MMU_MMU_LOCK_CurrentVictim_OFFSET))
/********************************************************************/
((u32)(((var) & MMU_MMU_LOCK_CurrentVictim_MASK)\
>> MMU_MMU_LOCK_CurrentVictim_OFFSET))
#define mmu_lck_crnt_vctmwite32(base_address, value)\
......@@ -427,25 +323,15 @@
}
/********************************************************************/
#define MMUMMU_LOCKCurrentVictimSet32(var, value)\
((((var) & ~(MMU_MMU_LOCK_CurrentVictim_MASK)) |\
(((value) << MMU_MMU_LOCK_CurrentVictim_OFFSET) &\
MMU_MMU_LOCK_CurrentVictim_MASK)))
/********************************************************************/
#define MMUMMU_LD_TLBReadRegister32(base_address)\
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_LD_TLB_OFFSET))
/********************************************************************/
#define mmu_ld_tlbwrt_reg32(base_address, value)\
{\
const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
......@@ -453,41 +339,27 @@
WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
}
/********************************************************************/
#define MMUMMU_LD_TLBLdTLBItemRead32(base_address)\
((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LD_TLB_OFFSET)))) &\
MMU_MMU_LD_TLB_LdTLBItem_MASK) >>\
MMU_MMU_LD_TLB_LdTLBItem_OFFSET))
#define MMUMMU_CAMReadRegister32(base_address)\
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_CAM_OFFSET))
/********************************************************************/
#define MMUMMU_CAMWriteRegister32(base_address, value)\
{\
const u32 offset = MMU_MMU_CAM_OFFSET;\
register u32 newValue = (value);\
WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
}
/********************************************************************/
#define MMUMMU_RAMReadRegister32(base_address)\
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_RAM_OFFSET))
/********************************************************************/
#define MMUMMU_RAMWriteRegister32(base_address, value)\
{\
const u32 offset = MMU_MMU_RAM_OFFSET;\
......@@ -495,9 +367,6 @@
WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
}
/********************************************************************/
#define MMUMMU_GFLUSHGlobalFlushWrite32(base_address, value)\
{\
const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
......@@ -510,10 +379,6 @@
WR_MEM_32_VOLATILE(base_address+offset, newValue);\
}
/********************************************************************/
#define MMUMMU_GFLUSHGlobalFlushWritenft_w32(base_address)\
{\
const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
......@@ -525,10 +390,6 @@
WR_MEM_32_VOLATILE(base_address+offset, data);\
}
/********************************************************************/
#define MMUMMU_GFLUSHGlobalFlushWriteflush_w32(base_address)\
{\
const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
......@@ -541,26 +402,15 @@
}
/********************************************************************/
#define MMUMMU_GFLUSHGlobalFlushSet32(var, value)\
((((var) & ~(MMU_MMU_GFLUSH_GlobalFlush_MASK)) |\
(((value) << MMU_MMU_GFLUSH_GlobalFlush_OFFSET) &\
MMU_MMU_GFLUSH_GlobalFlush_MASK)))
/********************************************************************/
#define MMUMMU_FLUSH_ENTRYReadRegister32(base_address)\
(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FLUSH_ENTRY_OFFSET))
/********************************************************************/
#define MMUMMU_FLUSH_ENTRYWriteRegister32(base_address, value)\
{\
const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
......@@ -572,8 +422,6 @@
#endif /* USE_LEVEL_1_MACROS */
#endif /* _MMU_REG_ACM_H */
/* EOF */
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