Commit c1dcfd9d authored by Scott Wood's avatar Scott Wood Committed by Kumar Gala

[POWERPC] cpm_uart: sparse fixes

Mostly a bunch of direct access to in/out conversions, plus a few
cast removals, __iomem annotations, and miscellaneous cleanup.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 7ae87036
......@@ -56,14 +56,14 @@ struct uart_cpm_port {
u16 rx_fifosize;
u16 tx_nrfifos;
u16 tx_fifosize;
smc_t *smcp;
smc_uart_t *smcup;
scc_t *sccp;
scc_uart_t *sccup;
volatile cbd_t *rx_bd_base;
volatile cbd_t *rx_cur;
volatile cbd_t *tx_bd_base;
volatile cbd_t *tx_cur;
smc_t __iomem *smcp;
smc_uart_t __iomem *smcup;
scc_t __iomem *sccp;
scc_uart_t __iomem *sccup;
cbd_t __iomem *rx_bd_base;
cbd_t __iomem *rx_cur;
cbd_t __iomem *tx_bd_base;
cbd_t __iomem *tx_cur;
unsigned char *tx_buf;
unsigned char *rx_buf;
u32 flags;
......@@ -106,34 +106,36 @@ void scc4_lineif(struct uart_cpm_port *pinfo);
/*
virtual to phys transtalion
*/
static inline unsigned long cpu2cpm_addr(void* addr, struct uart_cpm_port *pinfo)
static inline unsigned long cpu2cpm_addr(void *addr,
struct uart_cpm_port *pinfo)
{
int offset;
u32 val = (u32)addr;
u32 mem = (u32)pinfo->mem_addr;
/* sane check */
if (likely((val >= (u32)pinfo->mem_addr)) &&
(val<((u32)pinfo->mem_addr + pinfo->mem_size))) {
offset = val - (u32)pinfo->mem_addr;
return pinfo->dma_addr+offset;
if (likely(val >= mem && val < mem + pinfo->mem_size)) {
offset = val - mem;
return pinfo->dma_addr + offset;
}
/* something nasty happened */
BUG();
return 0;
}
static inline void *cpm2cpu_addr(unsigned long addr, struct uart_cpm_port *pinfo)
static inline void *cpm2cpu_addr(unsigned long addr,
struct uart_cpm_port *pinfo)
{
int offset;
u32 val = addr;
u32 dma = (u32)pinfo->dma_addr;
/* sane check */
if (likely((val >= pinfo->dma_addr) &&
(val<(pinfo->dma_addr + pinfo->mem_size)))) {
offset = val - (u32)pinfo->dma_addr;
return (void*)(pinfo->mem_addr+offset);
if (likely(val >= dma && val < dma + pinfo->mem_size)) {
offset = val - dma;
return pinfo->mem_addr + offset;
}
/* something nasty happened */
BUG();
return 0;
return NULL;
}
......
This diff is collapsed.
......@@ -179,7 +179,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
* pinfo->rx_fifosize);
pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
pinfo->rx_bd_base = (cbd_t __iomem __force *)dp_mem;
pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
return 0;
......
......@@ -27,18 +27,18 @@ static inline void cpm_set_brg(int brg, int baud)
cpm_setbrg(brg, baud);
}
static inline void cpm_set_scc_fcr(volatile scc_uart_t * sup)
static inline void cpm_set_scc_fcr(scc_uart_t __iomem * sup)
{
sup->scc_genscc.scc_rfcr = SMC_EB;
sup->scc_genscc.scc_tfcr = SMC_EB;
out_8(&sup->scc_genscc.scc_rfcr, SMC_EB);
out_8(&sup->scc_genscc.scc_tfcr, SMC_EB);
}
static inline void cpm_set_smc_fcr(volatile smc_uart_t * up)
static inline void cpm_set_smc_fcr(smc_uart_t __iomem * up)
{
up->smc_rfcr = SMC_EB;
up->smc_tfcr = SMC_EB;
out_8(&up->smc_rfcr, SMC_EB);
out_8(&up->smc_tfcr, SMC_EB);
}
#define DPRAM_BASE ((unsigned char *)cpm_dpram_addr(0))
#define DPRAM_BASE ((u8 __iomem __force *)cpm_dpram_addr(0))
#endif
......@@ -278,7 +278,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
* pinfo->rx_fifosize);
pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
pinfo->rx_bd_base = (cbd_t __iomem __force *)dp_mem;
pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
return 0;
......@@ -289,7 +289,7 @@ void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
pinfo->rx_fifosize) +
L1_CACHE_ALIGN(pinfo->tx_nrfifos *
pinfo->tx_fifosize), pinfo->mem_addr,
pinfo->tx_fifosize), (void __force *)pinfo->mem_addr,
pinfo->dma_addr);
cpm_dpfree(pinfo->dp_addr);
......
......@@ -27,18 +27,18 @@ static inline void cpm_set_brg(int brg, int baud)
cpm_setbrg(brg, baud);
}
static inline void cpm_set_scc_fcr(volatile scc_uart_t * sup)
static inline void cpm_set_scc_fcr(scc_uart_t __iomem *sup)
{
sup->scc_genscc.scc_rfcr = CPMFCR_GBL | CPMFCR_EB;
sup->scc_genscc.scc_tfcr = CPMFCR_GBL | CPMFCR_EB;
out_8(&sup->scc_genscc.scc_rfcr, CPMFCR_GBL | CPMFCR_EB);
out_8(&sup->scc_genscc.scc_tfcr, CPMFCR_GBL | CPMFCR_EB);
}
static inline void cpm_set_smc_fcr(volatile smc_uart_t * up)
static inline void cpm_set_smc_fcr(smc_uart_t __iomem *up)
{
up->smc_rfcr = CPMFCR_GBL | CPMFCR_EB;
up->smc_tfcr = CPMFCR_GBL | CPMFCR_EB;
out_8(&up->smc_rfcr, CPMFCR_GBL | CPMFCR_EB);
out_8(&up->smc_tfcr, CPMFCR_GBL | CPMFCR_EB);
}
#define DPRAM_BASE ((unsigned char *)cpm_dpram_addr(0))
#define DPRAM_BASE ((u8 __iomem __force *)cpm_dpram_addr(0))
#endif
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