davinci: add arch_ioremap() which uses existing static mapping

Add arch-specific ioremap() which uses any existing static mappings
in place of doing a new mapping.  From now on, drivers should always
use ioremap() instead of IO_ADDRESS().

In addition, remove the davinci_[read|write]* macros in favor of using
ioremap + io[read|write]*.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

arch/arm/mach-davinci/id.c

@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-#define JTAG_ID_BASE		0x01c40028
+#define JTAG_ID_BASE		IO_ADDRESS(0x01c40028)
 
 static unsigned int davinci_revision;
 
@@ -58,7 +58,7 @@ static u16 __init davinci_get_part_no(void)
 {
 	u32 dev_id, part_no;
 
-	dev_id = davinci_readl(JTAG_ID_BASE);
+	dev_id = __raw_readl(JTAG_ID_BASE);
 
 	part_no = ((dev_id >> 12) & 0xffff);
 
@@ -72,7 +72,7 @@ static u8 __init davinci_get_variant(void)
 {
 	u32 variant;
 
-	variant = davinci_readl(JTAG_ID_BASE);
+	variant = __raw_readl(JTAG_ID_BASE);
 
 	variant = (variant >> 28) & 0xf;
 

arch/arm/mach-davinci/include/mach/io.h

@@ -41,22 +41,12 @@
 #else
 #define IOMEM(x)                ((void __force __iomem *)(x))
 
-/*
- * Functions to access the DaVinci IO region
- *
- * NOTE: - Use davinci_read/write[bwl] for physical register addresses
- *	 - Use __raw_read/write[bwl]() for virtual register addresses
- *	 - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
- *	 - DO NOT use hardcoded virtual addresses to allow changing the
- *	   IO address space again if needed
- */
-#define davinci_readb(a)	__raw_readb(IO_ADDRESS(a))
-#define davinci_readw(a)	__raw_readw(IO_ADDRESS(a))
-#define davinci_readl(a)	__raw_readl(IO_ADDRESS(a))
+#define __arch_ioremap(p, s, t)	davinci_ioremap(p, s, t)
+#define __arch_iounmap(v)	davinci_iounmap(v)
 
-#define davinci_writeb(v, a)	__raw_writeb(v, IO_ADDRESS(a))
-#define davinci_writew(v, a)	__raw_writew(v, IO_ADDRESS(a))
-#define davinci_writel(v, a)	__raw_writel(v, IO_ADDRESS(a))
+void __iomem *davinci_ioremap(unsigned long phys, size_t size,
+			      unsigned int type);
+void davinci_iounmap(volatile void __iomem *addr);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ASM_ARCH_IO_H */

arch/arm/mach-davinci/include/mach/mux.h

@@ -22,19 +22,19 @@
 #include <mach/dm644x.h>
 
 /* System module registers */
-#define PINMUX0			(DAVINCI_SYSTEM_MODULE_BASE + 0x00)
-#define PINMUX1			(DAVINCI_SYSTEM_MODULE_BASE + 0x04)
+#define PINMUX0			0x00
+#define PINMUX1			0x04
 /* dm355 only */
-#define PINMUX2			(DAVINCI_SYSTEM_MODULE_BASE + 0x08)
-#define PINMUX3			(DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
-#define PINMUX4			(DAVINCI_SYSTEM_MODULE_BASE + 0x10)
-#define INTMUX			(DAVINCI_SYSTEM_MODULE_BASE + 0x18)
-#define EVTMUX			(DAVINCI_SYSTEM_MODULE_BASE + 0x1c)
+#define PINMUX2			0x08
+#define PINMUX3			0x0c
+#define PINMUX4			0x10
+#define INTMUX			0x18
+#define EVTMUX			0x1c
 
 struct mux_config {
 	char *name;
 	const char *mux_reg_name;
-	const unsigned int mux_reg;
+	const unsigned char mux_reg;
 	const unsigned char mask_offset;
 	const unsigned char mask;
 	const unsigned char mode;

arch/arm/mach-davinci/io.c

@@ -51,3 +51,27 @@ void __init davinci_map_common_io(void)
 	 */
 	davinci_check_revision();
 }
+
+#define BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
+#define XLATE(p, pst, vst)	((void __iomem *)((p) - (pst) + (vst)))
+
+/*
+ * Intercept ioremap() requests for addresses in our fixed mapping regions.
+ */
+void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
+{
+	if (BETWEEN(p, IO_PHYS, IO_SIZE))
+		return XLATE(p, IO_PHYS, IO_VIRT);
+
+	return __arm_ioremap(p, size, type);
+}
+EXPORT_SYMBOL(davinci_ioremap);
+
+void davinci_iounmap(volatile void __iomem *addr)
+{
+	unsigned long virt = (unsigned long)addr;
+
+	if (virt >= VMALLOC_START && virt < VMALLOC_END)
+		__iounmap(addr);
+}
+EXPORT_SYMBOL(davinci_iounmap);

arch/arm/mach-davinci/irq.c

@@ -44,14 +44,16 @@
 
 const u8 *davinci_def_priorities;
 
+#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
+
 static inline unsigned int davinci_irq_readl(int offset)
 {
-	return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
+	return __raw_readl(INTC_BASE + offset);
 }
 
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
-	davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
+	__raw_writel(value, INTC_BASE + offset);
 }
 
 /* Disable interrupt */

arch/arm/mach-davinci/mux.c

@@ -40,7 +40,7 @@ int __init davinci_mux_register(const struct mux_config *pins,
 int __init_or_module davinci_cfg_reg(const unsigned long index)
 {
 	static DEFINE_SPINLOCK(mux_spin_lock);
-
+	void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
 	unsigned long flags;
 	const struct mux_config *cfg;
 	unsigned int reg_orig = 0, reg = 0;
@@ -68,7 +68,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 		unsigned	tmp1, tmp2;
 
 		spin_lock_irqsave(&mux_spin_lock, flags);
-		reg_orig = davinci_readl(cfg->mux_reg);
+		reg_orig = __raw_readl(base + cfg->mux_reg);
 
 		mask = (cfg->mask << cfg->mask_offset);
 		tmp1 = reg_orig & mask;
@@ -80,7 +80,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 		if (tmp1 != tmp2)
 			warn = 1;
 
-		davinci_writel(reg, cfg->mux_reg);
+		__raw_writel(reg, base + cfg->mux_reg);
 		spin_unlock_irqrestore(&mux_spin_lock, flags);
 	}
 

arch/arm/mach-davinci/psc.c

@@ -46,13 +46,15 @@ static void (*davinci_psc_mux)(unsigned int id);
 
 static void dm6446_psc_mux(unsigned int id)
 {
+	void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
+
 	switch (id) {
 	case DAVINCI_LPSC_MMC_SD:
 		/* VDD power manupulations are done in U-Boot for CPMAC
 		 * so applies to MMC as well
 		 */
 		/*Set up the pull regiter for MMC */
-		davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
+		__raw_writel(0, base + VDD3P3V_PWDN);
 		davinci_cfg_reg(DM644X_MSTK);
 		break;
 	case DAVINCI_LPSC_I2C:
@@ -70,14 +72,15 @@ static void dm6446_psc_mux(unsigned int id)
 	}
 }
 
-#define DM355_ARM_PINMUX3	(DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
-#define DM355_ARM_PINMUX4	(DAVINCI_SYSTEM_MODULE_BASE + 0x10)
-#define DM355_ARM_INTMUX	(DAVINCI_SYSTEM_MODULE_BASE + 0x18)
-#define DM355_EDMA_EVTMUX	(DAVINCI_SYSTEM_MODULE_BASE + 0x1c)
+#define DM355_ARM_PINMUX3	0x0c
+#define DM355_ARM_PINMUX4	0x10
+#define DM355_ARM_INTMUX	0x18
+#define DM355_EDMA_EVTMUX	0x1c
 
 static void dm355_psc_mux(unsigned int id)
 {
 	u32	tmp;
+	void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
 
 	/* REVISIT mixing pinmux with PSC setup seems pretty dubious,
 	 * especially in cases like ASP0 where there are valid partial
@@ -90,15 +93,15 @@ static void dm355_psc_mux(unsigned int id)
 		/* our ASoC code currently doesn't use these IRQs */
 #if 0
 		/* deliver ASP1_XINT and ASP1_RINT */
-		tmp = davinci_readl(DM355_ARM_INTMUX);
+		tmp = __raw_readl(base + DM355_ARM_INTMUX);
 		tmp |= BIT(6) | BIT(5);
-		davinci_writel(tmp, DM355_ARM_INTMUX);
+		__raw_writel(tmp, base + DM355_ARM_INTMUX);
 #endif
 
 		/* support EDMA for ASP1_RX and ASP1_TX */
-		tmp = davinci_readl(DM355_EDMA_EVTMUX);
+		tmp = __raw_readl(base + DM355_EDMA_EVTMUX);
 		tmp &= ~(BIT(1) | BIT(0));
-		davinci_writel(tmp, DM355_EDMA_EVTMUX);
+		__raw_writel(tmp, base + DM355_EDMA_EVTMUX);
 		break;
 	case DAVINCI_LPSC_SPI:			/* SPI0 */
 		/* expose SPI0_SDI
@@ -119,46 +122,45 @@ static void nop_psc_mux(unsigned int id)
 void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
 {
 	u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
+	void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
 
 	if (id == DAVINCI_LPSC_NONE)
 		return;
 
-	mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
+	mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
 	if (enable)
 		mdctl |= 0x00000003;	/* Enable Module */
 	else
 		mdctl &= 0xFFFFFFF2;	/* Disable Module */
-	davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
+	__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
 
-	pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT);
+	pdstat = __raw_readl(psc_base + PDSTAT);
 	if ((pdstat & 0x00000001) == 0) {
-		pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+		pdctl1 = __raw_readl(psc_base + PDCTL1);
 		pdctl1 |= 0x1;
-		davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+		__raw_writel(pdctl1, psc_base + PDCTL1);
 
 		ptcmd = 1 << domain;
-		davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
+		__raw_writel(ptcmd, psc_base + PTCMD);
 
 		do {
-			epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-					      EPCPR);
+			epcpr = __raw_readl(psc_base + EPCPR);
 		} while ((((epcpr >> domain) & 1) == 0));
 
-		pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+		pdctl1 = __raw_readl(psc_base + PDCTL1);
 		pdctl1 |= 0x100;
-		davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+		__raw_writel(pdctl1, psc_base + PDCTL1);
 
 		do {
-			ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
+			ptstat = __raw_readl(psc_base +
 					       PTSTAT);
 		} while (!(((ptstat >> domain) & 1) == 0));
 	} else {
 		ptcmd = 1 << domain;
-		davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
+		__raw_writel(ptcmd, psc_base + PTCMD);
 
 		do {
-			ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-					       PTSTAT);
+			ptstat = __raw_readl(psc_base + PTSTAT);
 		} while (!(((ptstat >> domain) & 1) == 0));
 	}
 
@@ -168,8 +170,7 @@ void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
 		mdstat_mask = 0x2;
 
 	do {
-		mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-				       MDSTAT + 4 * id);
+		mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
 	} while (!((mdstat & 0x0000001F) == mdstat_mask));
 
 	if (enable)

arch/arm/mach-davinci/serial.c

@@ -39,38 +39,38 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 					   int offset)
 {
 	offset <<= up->regshift;
-	return (unsigned int)__raw_readl(up->membase + offset);
+	return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset);
 }
 
 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 				    int value)
 {
 	offset <<= p->regshift;
-	__raw_writel(value, p->membase + offset);
+	__raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
 }
 
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
-		.membase	= (char *)IO_ADDRESS(DAVINCI_UART0_BASE),
-		.mapbase	= (unsigned long)DAVINCI_UART0_BASE,
+		.mapbase	= DAVINCI_UART0_BASE,
 		.irq		= IRQ_UARTINT0,
-		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 	},
 	{
-		.membase	= (char *)IO_ADDRESS(DAVINCI_UART1_BASE),
-		.mapbase	= (unsigned long)DAVINCI_UART1_BASE,
+		.mapbase	= DAVINCI_UART1_BASE,
 		.irq		= IRQ_UARTINT1,
-		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 	},
 	{
-		.membase	= (char *)IO_ADDRESS(DAVINCI_UART2_BASE),
-		.mapbase	= (unsigned long)DAVINCI_UART2_BASE,
+		.mapbase	= DAVINCI_UART2_BASE,
 		.irq		= IRQ_UARTINT2,
-		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+				  UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 	},
@@ -121,24 +121,22 @@ void __init davinci_serial_init(struct davinci_uart_config *info)
 	for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) {
 		struct plat_serial8250_port *p = serial_platform_data + i;
 
+		if (!(info->enabled_uarts & (1 << i))) {
+			p->flags = 0;
+			continue;
+		}
+
 		if (cpu_is_davinci_dm646x()) {
 			p->iotype = UPIO_MEM32;
 		}
 
 		if (cpu_is_davinci_dm355()) {
 			if (i == 2) {
-				p->membase = (char *)
-					IO_ADDRESS(DM355_UART2_BASE);
 				p->mapbase = (unsigned long)DM355_UART2_BASE;
 				p->irq = IRQ_DM355_UARTINT2;
 			}
 		}
 
-		if (!(info->enabled_uarts & (1 << i))) {
-			p->flags = 0;
-			continue;
-		}
-
 		sprintf(name, "uart%d", i);
 		uart_clk = clk_get(dev, name);
 		p->uartclk = clk_get_rate(uart_clk);

arch/arm/mach-davinci/time.c

@@ -104,9 +104,9 @@ struct timer_s {
 	unsigned int id;
 	unsigned long period;
 	unsigned long opts;
-	unsigned long reg_base;
-	unsigned long tim_reg;
-	unsigned long prd_reg;
+	void __iomem *base;
+	unsigned long tim_off;
+	unsigned long prd_off;
 	unsigned long enamode_shift;
 	struct irqaction irqaction;
 };
@@ -119,15 +119,15 @@ static struct timer_s timers[];
 
 static int timer32_config(struct timer_s *t)
 {
-	u32 tcr = davinci_readl(t->reg_base + TCR);
+	u32 tcr = __raw_readl(t->base + TCR);
 
 	/* disable timer */
 	tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
-	davinci_writel(tcr, t->reg_base + TCR);
+	__raw_writel(tcr, t->base + TCR);
 
 	/* reset counter to zero, set new period */
-	davinci_writel(0, t->tim_reg);
-	davinci_writel(t->period, t->prd_reg);
+	__raw_writel(0, t->base + t->tim_off);
+	__raw_writel(t->period, t->base + t->prd_off);
 
 	/* Set enable mode */
 	if (t->opts & TIMER_OPTS_ONESHOT) {
@@ -136,13 +136,13 @@ static int timer32_config(struct timer_s *t)
 		tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
 	}
 
-	davinci_writel(tcr, t->reg_base + TCR);
+	__raw_writel(tcr, t->base + TCR);
 	return 0;
 }
 
 static inline u32 timer32_read(struct timer_s *t)
 {
-	return davinci_readl(t->tim_reg);
+	return __raw_readl(t->base + t->tim_off);
 }
 
 static irqreturn_t timer_interrupt(int irq, void *dev_id)
@@ -181,51 +181,54 @@ static struct timer_s timers[] = {
 
 static void __init timer_init(void)
 {
-	u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
+	u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
 	int i;
 
 	/* Global init of each 64-bit timer as a whole */
 	for(i=0; i<2; i++) {
-		u32 tgcr, base = bases[i];
+		u32 tgcr;
+		void __iomem *base = IO_ADDRESS(phys_bases[i]);
 
 		/* Disabled, Internal clock source */
-		davinci_writel(0, base + TCR);
+		__raw_writel(0, base + TCR);
 
 		/* reset both timers, no pre-scaler for timer34 */
 		tgcr = 0;
-		davinci_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base + TGCR);
 
 		/* Set both timers to unchained 32-bit */
 		tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
-		davinci_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base + TGCR);
 
 		/* Unreset timers */
 		tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
 			(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-		davinci_writel(tgcr, base + TGCR);
+		__raw_writel(tgcr, base + TGCR);
 
 		/* Init both counters to zero */
-		davinci_writel(0, base + TIM12);
-		davinci_writel(0, base + TIM34);
+		__raw_writel(0, base + TIM12);
+		__raw_writel(0, base + TIM34);
 	}
 
 	/* Init of each timer as a 32-bit timer */
 	for (i=0; i< ARRAY_SIZE(timers); i++) {
 		struct timer_s *t = &timers[i];
+		u32 phys_base;
 
 		if (t->name) {
 			t->id = i;
-			t->reg_base = (IS_TIMER1(t->id) ?
+			phys_base = (IS_TIMER1(t->id) ?
 			       DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE);
+			t->base = IO_ADDRESS(phys_base);
 
 			if (IS_TIMER_BOT(t->id)) {
 				t->enamode_shift = 6;
-				t->tim_reg = t->reg_base + TIM12;
-				t->prd_reg = t->reg_base + PRD12;
+				t->tim_off = TIM12;
+				t->prd_off = PRD12;
 			} else {
 				t->enamode_shift = 22;
-				t->tim_reg = t->reg_base + TIM34;
-				t->prd_reg = t->reg_base + PRD34;
+				t->tim_off = TIM34;
+				t->prd_off = PRD34;
 			}
 
 			/* Register interrupt */
@@ -353,42 +356,43 @@ struct sys_timer davinci_timer = {
 
 /* reset board using watchdog timer */
 void davinci_watchdog_reset(void) {
-	u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE;
+	u32 tgcr, wdtcr;
+	void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
 
 	/* disable, internal clock source */
-	davinci_writel(0, base + TCR);
+	__raw_writel(0, base + TCR);
 
 	/* reset timer, set mode to 64-bit watchdog, and unreset */
 	tgcr = 0;
-	davinci_writel(tgcr, base + TCR);
+	__raw_writel(tgcr, base + TCR);
 	tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
 	tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
 		(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-	davinci_writel(tgcr, base + TCR);
+	__raw_writel(tgcr, base + TCR);
 
 	/* clear counter and period regs */
-	davinci_writel(0, base + TIM12);
-	davinci_writel(0, base + TIM34);
-	davinci_writel(0, base + PRD12);
-	davinci_writel(0, base + PRD34);
+	__raw_writel(0, base + TIM12);
+	__raw_writel(0, base + TIM34);
+	__raw_writel(0, base + PRD12);
+	__raw_writel(0, base + PRD34);
 
 	/* enable */
-	wdtcr = davinci_readl(base + WDTCR);
+	wdtcr = __raw_readl(base + WDTCR);
 	wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
-	davinci_writel(wdtcr, base + WDTCR);
+	__raw_writel(wdtcr, base + WDTCR);
 
 	/* put watchdog in pre-active state */
 	wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
 		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
-	davinci_writel(wdtcr, base + WDTCR);
+	__raw_writel(wdtcr, base + WDTCR);
 
 	/* put watchdog in active state */
 	wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
 		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
-	davinci_writel(wdtcr, base + WDTCR);
+	__raw_writel(wdtcr, base + WDTCR);
 
 	/* write an invalid value to the WDKEY field to trigger
 	 * a watchdog reset */
 	wdtcr = 0x00004000;
-	davinci_writel(wdtcr, base + WDTCR);
+	__raw_writel(wdtcr, base + WDTCR);
 }

drivers/video/davincifb.c

@@ -53,18 +53,18 @@
  */
 static __inline__ u32 dispc_reg_in(u32 reg)
 {
-	return davinci_readl(reg);
+	return ioread32(IO_ADDRESS(reg));
 }
 static __inline__ u32 dispc_reg_out(u32 reg, u32 val)
 {
-	davinci_writel(val, reg);
+	iowrite32(val, IO_ADDRESS(reg));
 	return (val);
 }
 static __inline__ u32 dispc_reg_merge(u32 reg, u32 val, u32 mask)
 {
-	u32 new_val = (davinci_readl(reg) & ~mask) | (val & mask);
+	u32 new_val = (ioread32(IO_ADDRESS(reg)) & ~mask) | (val & mask);
 
-	davinci_writel(new_val, reg);
+	iowrite32(new_val, IO_ADDRESS(reg));
 	return (new_val);
 }