syslink IPC support for OMAP4

This patch provides the preliminary framework for
IPC support to OMAP4 processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Arun M G <arunmg@ti.com>
Signed-off-by: Ramesh Gupta G <grgupta@ti.com>
Signed-off-by: Jayan John <x00jayan@ti.com>
Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: Arun Radhakrishnan <x0051460@ti.com>

arch/arm/Kconfig

@@ -1477,6 +1477,8 @@ source "drivers/uio/Kconfig"
 
 source "drivers/staging/Kconfig"
 
+source "drivers/dsp/syslink/Kconfig"
+
 endmenu
 
 source "fs/Kconfig"

arch/arm/plat-omap/include/syslink/EasiGlobal.h

+/*
+ * EasiGlobal.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef __EASIGLOBAL_H
+#define __EASIGLOBAL_H
+#include <linux/types.h>
+
+/*
+ * DEFINE:        READ_ONLY, WRITE_ONLY &  READ_WRITE
+ *
+ * DESCRIPTION: Defines used to describe register types for EASI-checker tests.
+ */
+
+#define READ_ONLY    1
+#define WRITE_ONLY   2
+#define READ_WRITE   3
+
+/*
+ * MACRO:        _DEBUG_LEVEL_1_EASI
+ *
+ * DESCRIPTION:  A MACRO which can be used to indicate that a particular beach
+ *               register access function was called.
+ *
+ * NOTE:         We currently dont use this functionality.
+ */
+#define _DEBUG_LEVEL_1_EASI(easiNum)     ((void)0)
+
+#endif	/* __EASIGLOBAL_H */
+

arch/arm/plat-omap/include/syslink/GlobalTypes.h

+/*
+ * GlobalTypes.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef __GLOBALTYPES_H
+#define __GLOBALTYPES_H
+
+#define  REG volatile
+
+/*
+ * Definition: RET_CODE_BASE
+ *
+ * DESCRIPTION:  Base value for return code offsets
+ *
+ *
+ */
+#define RET_CODE_BASE        0
+
+/*
+ * TYPE: ReturnCode_t
+ *
+ * DESCRIPTION:  Return codes to be returned by all library functions
+ *
+ *
+ */
+enum ReturnCode_label {
+RET_OK = 0,
+RET_FAIL = -1,
+RET_BAD_NULL_PARAM = -2,
+RET_PARAM_OUT_OF_RANGE = -3,
+RET_INVALID_ID = -4,
+RET_EMPTY = -5,
+RET_FULL = -6,
+RET_TIMEOUT = -7,
+RET_INVALID_OPERATION = -8,
+/* Add new error codes at end of above list */
+RET_NUM_RET_CODES     /* this should ALWAYS be LAST entry */
+};
+
+
+
+/*
+ * MACRO: RD_MEM_32_VOLATILE, WR_MEM_32_VOLATILE
+ *
+ * DESCRIPTION:  32 bit register access macros
+ *
+ *
+ */
+#define RD_MEM_32_VOLATILE(addr) \
+((unsigned long)(*((REG unsigned long *)(addr))))
+
+#define WR_MEM_32_VOLATILE(addr, data) \
+(*((REG unsigned long *)(addr)) = (unsigned long)(data))
+
+
+
+
+#ifdef CHECK_INPUT_PARAMS
+/*
+ * MACRO: CHECK_INPUT_PARAMS
+ *
+ * DESCRIPTION:  Checks an input code and returns a specified value if code is
+ *               invalid value, also writes spy value if error found.
+ *
+ * NOTE:         Can be disabled to save HW cycles.
+ *
+ *
+ */
+#define CHECK_INPUT_PARAM(actualValue, invalidValue,  \
+returnCodeIfMismatch, spyCodeIfMisMatch) do {\
+	if ((invalidValue) == (actualValue)) {\
+		RES_Set((spyCodeIfMisMatch));\
+		return returnCodeIfMismatch; \
+	} \
+} while (0)
+
+/*
+ * MACRO: CHECK_INPUT_RANGE
+ *
+ * DESCRIPTION:  Checks an input value and returns a specified value if not in
+ *               specified range, also writes spy value if error found.
+ *
+* NOTE:         Can be disabled to save HW cycles.
+ *
+ *
+ */
+#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue, \
+returnCodeIfMismatch, spyCodeIfMisMatch) do {\
+	if (((actualValue) < (minValidValue)) || \
+		((actualValue) > (maxValidValue))) {\
+		RES_Set((spyCodeIfMisMatch));\
+		return returnCodeIfMismatch; \
+	} \
+} while (0)
+
+/*
+ * MACRO: CHECK_INPUT_RANGE_MIN0
+ * 
+ * DESCRIPTION:  Checks an input value and returns a
+ * specified value if not in
+ * specified range, also writes spy value if error found.
+ * The minimum
+ * value is 0.
+ * 
+ * NOTE:         Can be disabled to save HW cycles.
+ * 
+ *
+ */
+#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue, \
+returnCodeIfMismatch, spyCodeIfMisMatch) do {\
+	if ((actualValue) > (maxValidValue)) {\
+		RES_Set((spyCodeIfMisMatch));\
+		return returnCodeIfMismatch; \
+	} \
+} while (0)
+
+#else
+
+#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\
+spyCodeIfMisMatch)
+
+#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue, \
+returnCodeIfMismatch)
+
+#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue, \
+returnCodeIfMismatch, spyCodeIfMisMatch)
+
+#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue , \
+maxValidValue, returnCodeIfMismatch)
+
+#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue, \
+returnCodeIfMismatch, spyCodeIfMisMatch)
+
+#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, \
+maxValidValue, returnCodeIfMismatch)
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif	/* __GLOBALTYPES_H */

arch/arm/plat-omap/include/syslink/MLBAccInt.h

+/*
+ * MLBAccInt.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef _MLB_ACC_INT_H
+#define _MLB_ACC_INT_H
+
+/* Mappings of level 1 EASI function numbers to function names */
+
+#define EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32   (MLB_BASE_EASIL1 + 3)
+#define EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32  (MLB_BASE_EASIL1 + 4)
+#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32   (MLB_BASE_EASIL1 + 7)
+#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32  (MLB_BASE_EASIL1 + 17)
+#define EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32 (MLB_BASE_EASIL1 + 29)
+#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32 \
+						(MLB_BASE_EASIL1 + 33)
+#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32   (MLB_BASE_EASIL1 + 39)
+#define EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32  (MLB_BASE_EASIL1 + 44)
+#define EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32 \
+						(MLB_BASE_EASIL1 + 50)
+#define EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32  \
+						(MLB_BASE_EASIL1 + 51)
+#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32  \
+						(MLB_BASE_EASIL1 + 56)
+#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32 \
+						(MLB_BASE_EASIL1 + 57)
+#define EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32  \
+						(MLB_BASE_EASIL1 + 60)
+#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32  \
+						(MLB_BASE_EASIL1 + 62)
+#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32 \
+						(MLB_BASE_EASIL1 + 63)
+#define EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32    \
+						(MLB_BASE_EASIL1 + 192)
+#define EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32   \
+						(MLB_BASE_EASIL1 + 193)
+
+/* Register set MAILBOX_MESSAGE___REGSET_0_15 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET    (u32)(0x0040)
+#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP   (u32)(0x0004)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_MESSAGE___REGSET_0_15 */
+
+#define MLB_MAILBOX_MESSAGE___0_15_OFFSET   (u32)(0x0)
+
+
+/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET  (u32)(0x0080)
+#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP   (u32)(0x0004)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_FIFOSTATUS___REGSET_0_15 */
+
+#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET    (u32)(0x0)
+
+
+/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET  (u32)(0x00c0)
+#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP    (u32)(0x0004)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_MSGSTATUS___REGSET_0_15 */
+
+#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET    (u32)(0x0)
+
+
+/* Register set MAILBOX_IRQSTATUS___REGSET_0_3 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET        (u32)(0x0100)
+#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP          (u32)(0x0008)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_IRQSTATUS___REGSET_0_3 */
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET        (u32)(0x0)
+
+
+/* Register set MAILBOX_IRQENABLE___REGSET_0_3 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET     (u32)(0x0104)
+#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP     (u32)(0x0008)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_IRQENABLE___REGSET_0_3 */
+
+#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET          (u32)(0x0)
+
+
+/* Register offset address definitions */
+
+#define MLB_MAILBOX_SYSCONFIG_OFFSET            (u32)(0x10)
+#define MLB_MAILBOX_SYSSTATUS_OFFSET            (u32)(0x14)
+
+
+/* Bitfield mask and offset declarations */
+
+#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK        (u32)(0x18)
+#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET      (u32)(3)
+#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK        (u32)(0x2)
+#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET      (u32)(1)
+#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK          (u32)(0x1)
+#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET        (u32)(0)
+#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK         (u32)(0x1)
+#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET         (u32)(0)
+#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK   (u32)(0x1)
+#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET  (u32)(0)
+#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK    (u32)(0x7f)
+#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET    (u32)(0)
+
+#endif /* _MLB_ACC_INT_H */

arch/arm/plat-omap/include/syslink/MLBRegAcM.h

+/*
+ * MLBRegAcM.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _MLB_REG_ACM_H
+#define _MLB_REG_ACM_H
+
+#include <syslink/GlobalTypes.h>
+#include <syslink/EasiGlobal.h>
+#include <syslink/MLBAccInt.h>
+
+#if defined(USE_LEVEL_1_MACROS)
+
+#define MLBMAILBOX_SYSCONFIGReadRegister32(base_address)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+ \
+MLB_MAILBOX_SYSCONFIG_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGWriteRegister32(base_address, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\
+	WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\
+} while(0)
+
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(base_address)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32),\
+(((RD_MEM_32_VOLATILE((((u32)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(base_address, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(base_address)) +\
+				offset);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\
+} while(0)
+
+
+#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(base_address, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register u32 data =\
+	RD_MEM_32_VOLATILE(((u32)(base_address))+offset);\
+	register u32 newValue = ((u32)(value));\
+	printk(KERN_ALERT "In SYSCONFIG MACOR line %i    file %s",  \
+	__LINE__, __FILE__);\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32);\
+	printk(KERN_ALERT "******************BEFORE DATA WRITE");\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\
+	printk(KERN_ALERT "line %i    file %s", __LINE__, __FILE__);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\
+	newValue |= data;\
+	printk(KERN_ALERT "line %i    file %s", __LINE__, __FILE__);\
+	WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\
+	printk(KERN_ALERT "line %i    file %s", __LINE__, __FILE__);\
+} while(0)
+
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(base_address)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32),\
+(((RD_MEM_32_VOLATILE((((u32)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(base_address, value)\
+{\
+	const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register u32 data =\
+	RD_MEM_32_VOLATILE(((u32)(base_address))+offset);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\
+}
+
+
+#define MLBMAILBOX_SYSSTATUSResetDoneRead32(base_address)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32),\
+(((RD_MEM_32_VOLATILE((((u32)(base_address))+\
+(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\
+MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
+MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))
+
+
+#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_MESSAGE___0_15_OFFSET+(\
+(bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP))))
+
+
+#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(base_address, bank, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
+	MLB_MAILBOX_MESSAGE___0_15_OFFSET +\
+	((bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32);\
+	WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\
+}while(0)
+
+
+#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(\
+EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
+((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP))))
+
+
+#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(\
+EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32),\
+(((RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
+((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\
+MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\
+MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET))
+
+
+#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(\
+EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32),\
+(((RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+\
+((bank)*MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\
+MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\
+MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET))
+
+
+#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\
+((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP))))
+
+
+#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(base_address, bank, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32);\
+	WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\
+} while(0)
+
+
+#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\
+((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP))))
+
+
+#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(base_address, bank, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32);\
+	WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\
+} while(0)
+
+
+#endif	/* USE_LEVEL_1_MACROS */
+
+#endif /* _MLB_REG_ACM_H */

arch/arm/plat-omap/include/syslink/MMUAccInt.h

+/*
+ * MMUAccInt.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _MMU_ACC_INT_H
+#define _MMU_ACC_INT_H
+
+
+/* Register offset address definitions */
+
+#define MMU_MMU_REVISION_OFFSET                                                 0x0
+#define MMU_MMU_SYSCONFIG_OFFSET                                                0x10
+#define MMU_MMU_SYSSTATUS_OFFSET                                                014
+#define MMU_MMU_IRQSTATUS_OFFSET                                                0x18
+#define MMU_MMU_IRQENABLE_OFFSET                                                0x1c
+#define MMU_MMU_WALKING_ST_OFFSET                                               0x40
+#define MMU_MMU_CNTL_OFFSET                                                     0x44
+#define MMU_MMU_FAULT_AD_OFFSET                                                 0x48
+#define MMU_MMU_TTB_OFFSET                                                      0x4c
+#define MMU_MMU_LOCK_OFFSET                                                     0x50
+#define MMU_MMU_LD_TLB_OFFSET                                                   0x54
+#define MMU_MMU_CAM_OFFSET                                                      0x58
+#define MMU_MMU_RAM_OFFSET                                                      0x5c
+#define MMU_MMU_GFLUSH_OFFSET                                                   0x60
+#define MMU_MMU_FLUSH_ENTRY_OFFSET                                              0x64
+#define MMU_MMU_READ_CAM_OFFSET                                                 0x68
+#define MMU_MMU_READ_RAM_OFFSET                                                 0x6c
+#define MMU_MMU_EMU_FAULT_AD_OFFSET                                             0x70
+
+
+/* Bitfield mask and offset declarations */
+
+#define MMU_MMU_REVISION_Rev_MASK                                               0xff
+#define MMU_MMU_REVISION_Rev_OFFSET                                             0
+
+#define MMU_MMU_SYSCONFIG_ClockActivity_MASK                                    0x300
+#define MMU_MMU_SYSCONFIG_ClockActivity_OFFSET                                  8
+
+#define MMU_MMU_SYSCONFIG_IdleMode_MASK                                         0x18
+#define MMU_MMU_SYSCONFIG_IdleMode_OFFSET                                       3
+
+#define MMU_MMU_SYSCONFIG_SoftReset_MASK                                        0x2
+#define MMU_MMU_SYSCONFIG_SoftReset_OFFSET                                      1
+
+#define MMU_MMU_SYSCONFIG_AutoIdle_MASK                                         0x1
+#define MMU_MMU_SYSCONFIG_AutoIdle_OFFSET                                       0
+
+#define MMU_MMU_SYSSTATUS_ResetDone_MASK                                        0x1
+#define MMU_MMU_SYSSTATUS_ResetDone_OFFSET                                      0
+
+#define MMU_MMU_IRQSTATUS_MultiHitFault_MASK                                    0x10
+#define MMU_MMU_IRQSTATUS_MultiHitFault_OFFSET                                  4
+
+#define MMU_MMU_IRQSTATUS_TableWalkFault_MASK                                   0x8
+#define MMU_MMU_IRQSTATUS_TableWalkFault_OFFSET                                 3
+
+#define MMU_MMU_IRQSTATUS_EMUMiss_MASK                                          0x4
+#define MMU_MMU_IRQSTATUS_EMUMiss_OFFSET                                        2
+
+#define MMU_MMU_IRQSTATUS_TranslationFault_MASK                                 0x2
+#define MMU_MMU_IRQSTATUS_TranslationFault_OFFSET                               1
+
+#define MMU_MMU_IRQSTATUS_TLBMiss_MASK                                          0x1
+#define MMU_MMU_IRQSTATUS_TLBMiss_OFFSET                                        0
+
+#define MMU_MMU_IRQENABLE_MultiHitFault_MASK                                    0x10
+#define MMU_MMU_IRQENABLE_MultiHitFault_OFFSET                                  4
+
+#define MMU_MMU_IRQENABLE_TableWalkFault_MASK                                   0x8
+#define MMU_MMU_IRQENABLE_TableWalkFault_OFFSET                                 3
+
+#define MMU_MMU_IRQENABLE_EMUMiss_MASK                                          0x4
+#define MMU_MMU_IRQENABLE_EMUMiss_OFFSET                                        2
+
+#define MMU_MMU_IRQENABLE_TranslationFault_MASK                                 0x2
+#define MMU_MMU_IRQENABLE_TranslationFault_OFFSET                               1
+
+#define MMU_MMU_IRQENABLE_TLBMiss_MASK                                          0x1
+#define MMU_MMU_IRQENABLE_TLBMiss_OFFSET                                        0
+
+#define MMU_MMU_WALKING_ST_TWLRunning_MASK                                      0x1
+#define MMU_MMU_WALKING_ST_TWLRunning_OFFSET                                    0
+
+#define MMU_MMU_CNTL_EmuTLBUpdate_MASK                                          0x8
+#define MMU_MMU_CNTL_EmuTLBUpdate_OFFSET                                        3
+
+#define MMU_MMU_CNTL_TWLEnable_MASK                                             0x4
+#define MMU_MMU_CNTL_TWLEnable_OFFSET                                           2
+
+#define MMU_MMU_CNTL_MMUEnable_MASK                                             0x2
+#define MMU_MMU_CNTL_MMUEnable_OFFSET                                           1
+
+#define MMU_MMU_FAULT_AD_FaultAddress_MASK	0xffffffff
+#define MMU_MMU_FAULT_AD_FaultAddress_OFFSET                                    0
+
+#define MMU_MMU_TTB_TTBAddress_MASK	0xffffff00
+#define MMU_MMU_TTB_TTBAddress_OFFSET	8
+
+#define MMU_MMU_LOCK_BaseValue_MASK	0xfc00
+#define MMU_MMU_LOCK_BaseValue_OFFSET                                           10
+
+#define MMU_MMU_LOCK_CurrentVictim_MASK                                         0x3f0
+#define MMU_MMU_LOCK_CurrentVictim_OFFSET                                       4
+
+#define MMU_MMU_LD_TLB_LdTLBItem_MASK                                           0x1
+#define MMU_MMU_LD_TLB_LdTLBItem_OFFSET                                         0
+
+#define MMU_MMU_CAM_VATag_MASK                                                  0xfffff000
+#define MMU_MMU_CAM_VATag_OFFSET                                                12
+
+#define MMU_MMU_CAM_P_MASK                                                      0x8
+#define MMU_MMU_CAM_P_OFFSET                                                    3
+
+#define MMU_MMU_CAM_V_MASK                                                      0x4
+#define MMU_MMU_CAM_V_OFFSET                                                    2
+
+#define MMU_MMU_CAM_PageSize_MASK                                               0x3
+#define MMU_MMU_CAM_PageSize_OFFSET                                             0
+
+#define MMU_MMU_RAM_PhysicalAddress_MASK                                        0xfffff000
+#define MMU_MMU_RAM_PhysicalAddress_OFFSET                                      12
+
+#define MMU_MMU_RAM_Endianness_MASK                                             0x200
+#define MMU_MMU_RAM_Endianness_OFFSET                                           9
+
+#define MMU_MMU_RAM_ElementSize_MASK                                            0x180
+#define MMU_MMU_RAM_ElementSize_OFFSET                                          7
+
+#define MMU_MMU_RAM_Mixed_MASK                                                  0x40
+#define MMU_MMU_RAM_Mixed_OFFSET                                                6
+
+#define MMU_MMU_GFLUSH_GlobalFlush_MASK                                         0x1
+#define MMU_MMU_GFLUSH_GlobalFlush_OFFSET                                       0
+
+#define MMU_MMU_FLUSH_ENTRY_FlushEntry_MASK                                     0x1
+#define MMU_MMU_FLUSH_ENTRY_FlushEntry_OFFSET                                   0
+
+#define MMU_MMU_READ_CAM_VATag_MASK                                             0xfffff000
+#define MMU_MMU_READ_CAM_VATag_OFFSET                                           12
+
+#define MMU_MMU_READ_CAM_P_MASK                                                 0x8
+#define MMU_MMU_READ_CAM_P_OFFSET                                               3
+
+#define MMU_MMU_READ_CAM_V_MASK                                                 0x4
+#define MMU_MMU_READ_CAM_V_OFFSET                                               2
+
+#define MMU_MMU_READ_CAM_PageSize_MASK                                          0x3
+#define MMU_MMU_READ_CAM_PageSize_OFFSET                                        0
+
+#define MMU_MMU_READ_RAM_PhysicalAddress_MASK                                   0xfffff000
+#define MMU_MMU_READ_RAM_PhysicalAddress_OFFSET                                 12
+
+#define MMU_MMU_READ_RAM_Endianness_MASK                                        0x200
+#define MMU_MMU_READ_RAM_Endianness_OFFSET                                      9
+
+#define MMU_MMU_READ_RAM_ElementSize_MASK                                       0x180
+#define MMU_MMU_READ_RAM_ElementSize_OFFSET                                     7
+
+#define MMU_MMU_READ_RAM_Mixed_MASK                                             0x40
+#define MMU_MMU_READ_RAM_Mixed_OFFSET                                           6
+
+#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_MASK                               0xffffffff
+#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_OFFSET                             0
+
+#endif /* _MMU_ACC_INT_H */
+/* EOF */
+

arch/arm/plat-omap/include/syslink/Makefile

+#   ============================================================================
+#   @file   Makefile
+#
+#   @path   $(DSPLINK)/gpp/src/ldrv/
+#
+#   @desc   This file is a standard interface to the make scripts.
+#           Usually no change is required in this file.
+#
+#   @ver    1.51.00.08
+#   ============================================================================
+#   Copyright (c) Texas Instruments Incorporated 2002-2008
+#
+#   Use of this software is controlled by the terms and conditions found in the
+#   license agreement under which this software has been supplied or provided.
+#   ============================================================================
+
+
+#   ============================================================================
+#   Set the device type (GPP/DSP)
+#   ============================================================================
+
+export DEVICETYPE := GPP
+export MEMSPACE   := KRNL
+
+
+#   ============================================================================
+#   Get the directory separator used on the development host.
+#   ============================================================================
+
+ifneq ("$(ComSpec)", "")
+    ifeq ("$(OSTYPE)", "cygwin")
+        DIRSEP ?=/
+    else
+        DIRSEP ?=\\
+    endif
+else
+    DIRSEP ?= /
+endif
+
+
+#   ============================================================================
+#   Start the build process
+#   ============================================================================
+
+include $(NOTIFY)$(DIRSEP)make$(DIRSEP)start.mk

arch/arm/plat-omap/include/syslink/OsalSemaphore.h

+/*!
+ *  @file	OsalSemaphore.h
+ *
+ *  @brief	Kernel utils Semaphore interface definitions.
+ *
+ *		This abstracts the Semaphore interface in Kernel code and
+ *		is implemented using the wait queues. It has interfaces
+ *		for creating, destroying, waiting and triggering the Semaphores.
+ *
+ *  @date	04-02-2009
+ *
+ *  @internal   04-02-2009, Harshit Srivastava, Revision 0001:
+ *		[1] Original version.
+ *		Apr 18, 2009, Mugdha Kamoolkar, Revision 0002:
+ *		[1] Minor updates.
+ */
+
+
+#ifndef OSALSEMAPHORE_H_0xF6D6
+#define OSALSEMAPHORE_H_0xF6D6
+
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* OSAL and utils */
+
+/*!
+ *  @def	OSALSEMAPHORE_MODULEID
+ *  @brief  Module ID for OsalSemaphore OSAL module.
+ */
+#define OSALSEMAPHORE_MODULEID		(u16) 0xF6D6
+
+/* =============================================================================
+ *  All success and failure codes for the module
+ * =============================================================================
+ */
+/*!
+* @def   OSALSEMAPHORE_STATUSCODEBASE
+* @brief Stauts code base for MEMORY module.
+*/
+#define OSALSEMAPHORE_STATUSCODEBASE	(OSALSEMAPHORE_MODULEID << 12)
+
+/*!
+* @def   OSALSEMAPHORE_MAKE_FAILURE
+* @brief Convert to failure code.
+*/
+#define OSALSEMAPHORE_MAKE_FAILURE(x)	((int) (0x80000000 \
+					+ (OSALSEMAPHORE_STATUSCODEBASE + (x))))
+/*!
+* @def   OSALSEMAPHORE_MAKE_SUCCESS
+* @brief Convert to success code.
+*/
+#define OSALSEMAPHORE_MAKE_SUCCESS(x)	(OSALSEMAPHORE_STATUSCODEBASE + (x))
+
+/*!
+* @def   OSALSEMAPHORE_E_MEMORY
+* @brief Indicates OsalSemaphore alloc/free failure.
+*/
+#define OSALSEMAPHORE_E_MEMORY		OSALSEMAPHORE_MAKE_FAILURE(1)
+
+/*!
+* @def   OSALSEMAPHORE_E_INVALIDARG
+* @brief Invalid argument provided
+*/
+#define OSALSEMAPHORE_E_INVALIDARG	OSALSEMAPHORE_MAKE_FAILURE(2)
+
+/*!
+* @def   OSALSEMAPHORE_E_FAIL
+* @brief Generic failure
+*/
+#define OSALSEMAPHORE_E_FAIL		OSALSEMAPHORE_MAKE_FAILURE(3)
+
+/*!
+* @def   OSALSEMAPHORE_E_TIMEOUT
+* @brief A timeout occurred
+*/
+#define OSALSEMAPHORE_E_TIMEOUT		OSALSEMAPHORE_MAKE_FAILURE(4)
+
+/*!
+ *  @def	OSALSEMAPHORE_E_HANDLE
+ *  @brief  Invalid handle provided
+ */
+#define OSALSEMAPHORE_E_HANDLE		OSALSEMAPHORE_MAKE_FAILURE(5)
+
+/*!
+ *  @def	OSALSEMAPHORE_E_WAITNONE
+ *  @brief  WAIT_NONE timeout value was provided, but semaphore was not
+ *	  available.
+ */
+#define OSALSEMAPHORE_E_WAITNONE	OSALSEMAPHORE_MAKE_FAILURE(6)
+
+/*!
+* @def   OSALSEMAPHORE_SUCCESS
+* @brief Operation successfully completed
+*/
+#define OSALSEMAPHORE_SUCCESS		OSALSEMAPHORE_MAKE_SUCCESS(0)
+
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+/*!
+ *  @def	OSALSEMAPHORE_WAIT_FOREVER
+ *  @brief  Indicates forever wait for APIs that can wait.
+ */
+#define OSALSEMAPHORE_WAIT_FOREVER	(~((u32) 0))
+
+/*!
+ *  @def	OSALSEMAPHORE_WAIT_NONE
+ *  @brief  Indicates zero wait for APIs that can wait.
+ */
+#define OSALSEMAPHORE_WAIT_NONE		((u32) 0)
+
+/*!
+ *  @def	OSALSEMAPHORE_TYPE_VALUE
+ *  @brief  Returns the value of semaphore type (binary/counting)
+ */
+#define OSALSEMAPHORE_TYPE_VALUE(type)	(type & 0x0000FFFF)
+
+/*!
+ *  @def	OSALSEMAPHORE_INTTYPE_VALUE
+ *  @brief  Returns the value of semaphore interruptability type
+ */
+#define OSALSEMAPHORE_INTTYPE_VALUE(type)	(type & 0xFFFF0000)
+
+/*!
+ *  @brief  Declaration for the OsalSemaphore object handle.
+ *	  Definition of OsalSemaphore_Object is not exposed.
+ */
+typedef struct OsalSemaphore_Object *OsalSemaphore_Handle;
+
+/*!
+ *  @brief   Enumerates the types of semaphores
+ */
+typedef enum {
+	OsalSemaphore_Type_Binary = 0x00000000,
+	/*!< Binary semaphore */
+	OsalSemaphore_Type_Counting = 0x00000001,
+	/*!< Counting semaphore */
+	OsalSemaphore_Type_EndValue = 0x00000002
+	/*!< End delimiter indicating start of invalid values for this enum */
+} OsalSemaphore_Type;
+
+/*!
+ *  @brief   Enumerates the interruptible/non-interruptible types.
+ */
+typedef enum {
+	OsalSemaphore_IntType_Interruptible = 0x00000000,
+	/*!< Waits on this mutex are interruptible */
+	OsalSemaphore_IntType_Noninterruptible = 0x00010000,
+	/*!< Waits on this mutex are non-interruptible */
+	OsalSemaphore_IntType_EndValue = 0x00020000
+	/*!< End delimiter indicating start of invalid values for this enum */
+} OsalSemaphore_IntType;
+
+
+/* =============================================================================
+ *  APIs
+ * =============================================================================
+ */
+/* Creates the semaphore object. */
+OsalSemaphore_Handle OsalSemaphore_create(u32 semType);
+
+/* Deletes the semaphore object */
+int OsalSemaphore_delete(OsalSemaphore_Handle *semHandle);
+
+/* Wait on the said Semaphore in the kernel thread context */
+int OsalSemaphore_pend(OsalSemaphore_Handle semHandle, u32 timeout);
+
+/* Signal the semaphore and make it available for other threads. */
+int OsalSemaphore_post(OsalSemaphore_Handle semHandle);
+
+#endif /* ifndef OSALSEMAPHORE_H_0xF6D6 */

arch/arm/plat-omap/include/syslink/_bitops.h

+/** ============================================================================
+ *  @file   _bitops.h
+ *
+ *  @path   $(DSPLINK)/gpp/inc/
+ *
+ *  @desc   Defines generic macros for bitwise opeartions.
+ *
+ *  @ver    1.51.00.08
+ *  ============================================================================
+ *  Copyright (c) Texas Instruments Incorporated 2002-2008
+ *
+ *  Use of this software is controlled by the terms and conditions found in the
+ *  license agreement under which this software has been supplied or provided.
+ *  ============================================================================
+ */
+
+
+#if !defined (_BITOPS_H)
+#define _BITOPS_H
+
+
+#if defined (__cplusplus)
+extern "C" {
+#endif /* defined (__cplusplus) */
+
+
+/** ============================================================================
+ *  @macro  SET_BITS
+ *
+ *  @desc   Sets bits contained in given mask.
+ *          This macro is independent of operand width. User must ensure
+ *          correctness.
+ *  ============================================================================
+ */
+#define SET_BITS(num,mask)          ((num) |= (mask))
+
+/** ============================================================================
+ *  @macro  CLEAR_BITS
+ *
+ *  @desc   Clears bits contained in given mask.
+ *          This macro is independent of operand width. User must ensure
+ *          correctness.
+ *  ============================================================================
+ */
+#define CLEAR_BITS(num,mask)        ((num) &= ~(mask))
+
+/** ============================================================================
+ *  @macro  SET_BIT
+ *
+ *  @desc   Sets bit at given position.
+ *          This macro is independent of operand width. User must ensure
+ *          correctness.
+ *  ============================================================================
+ */
+#define SET_BIT(num,pos)            ((num) |= (1u << (pos)))
+
+/** ============================================================================
+ *  @macro  CLEAR_BIT
+ *
+ *  @desc   Clears bit at given position.
+ *          This macro is independent of operand width. User must ensure
+ *          correctness.
+ *  ============================================================================
+ */
+#define CLEAR_BIT(num,pos)          ((num) &= ~(1u << (pos)))
+
+
+/** ============================================================================
+ *  @macro  TEST_BIT
+ *
+ *  @desc   Tests if bit at given position is set.
+ *          This macro is independent of operand width. User must ensure
+ *          correctness.
+ *  ============================================================================
+ */
+#define TEST_BIT(num,pos)           ((((num) & (1u << (pos))) >> (pos)) & 0x01)
+
+
+/** ============================================================================
+ *  @macro  GET_NBITS8
+ *
+ *  @desc   Gets numeric value of specified bits from an 8 bit value.
+ *  ============================================================================
+ */
+#define GET_NBITS8(num,pos,width)   \
+            (((num) & ((0xFF >> (8u - (width))) << (pos))) >> (pos))
+
+/** ============================================================================
+ *  @macro  GET_NBITS16
+ *
+ *  @desc   Gets numeric value of specified bits from an 16 bit value.
+ *  ============================================================================
+ */
+#define GET_NBITS16(num,pos,width)  \
+            (((num) & ((0xFFFF >> (16u - (width))) << (pos))) >>  (pos))
+
+/** ============================================================================
+ *  @macro  GET_BITS32
+ *
+ *  @desc   Gets numeric value of specified bits from an 32 bit value.
+ *  ============================================================================
+ */
+#define GET_NBITS32(num,pos,width)  \
+            (((num) & ((0xFFFFFFFF >> (32u - (width))) << (pos))) >>  (pos))
+
+/** ============================================================================
+ *  @macro  SET_NBITS8
+ *
+ *  @desc   Sets specified bits in a 8 bit entity to given value.
+ *  ============================================================================
+ */
+#define SET_NBITS8(num,pos,width,value)     \
+            (num) &= ~((0xFF >> (8u - (width))) << (pos)) ;                  \
+            (num) |= (((value) & (0xFF >> (8u - (width)))) << (pos)) ;
+
+/** ============================================================================
+ *  @macro  SET_NBITS16
+ *
+ *  @desc   Sets specified bits in a 16 bit entity to given value.
+ *  ============================================================================
+ */
+#define SET_NBITS16(num,pos,width,value)    \
+            (num) &= ~((0xFFFF >> (16u - (width))) << (pos)) ;               \
+            (num) |= (((value) & (0xFFFF >> (16u - (width)))) << (pos)) ;
+
+/** ============================================================================
+ *  @macro  SET_NBITS32
+ *
+ *  @desc   Sets specified bits in a 32 bit entity to given value.
+ *  ============================================================================
+ */
+#define SET_NBITS32(num,pos,width,value)   \
+            (num) &= ~((0xFFFFFFFF >> (32u - (width))) << (pos)) ;           \
+            (num) |= (((value) & (0xFFFFFFFF >> (32u - (width)))) << (pos)) ;
+
+/** ============================================================================
+ *  @macro  BYTESWAP_WORD
+ *
+ *  @desc   Macro to swap bytes within a 16 bit word.
+ *  ============================================================================
+ */
+#define BYTESWAP_WORD(x)   (unsigned short int) (( (unsigned short int) ((((unsigned short int)(x)) << 8u) & 0xFF00u) \
+                                     | (unsigned short int)((((unsigned short int)(x)) >> 8u) & 0x00FFu)))
+
+/** ============================================================================
+ *  @macro  BYTESWAP_LONG
+ *
+ *  @desc   Macro to swap bytes within a 32 bit dword.
+ *  ============================================================================
+ */
+#define BYTESWAP_LONG(x) (   (((x) << 24u) & 0xFF000000u)    \
+                          |  (((x) <<  8u) & 0x00FF0000u)   \
+                          |  (((x) >>  8u) & 0x0000FF00u)   \
+                          |  (((x) >> 24u) & 0x000000FFu))
+
+/** ============================================================================
+ *  @macro  WORDSWAP_LONG
+ *
+ *  @desc   Macro to swap two 16-bit values within a 32 bit dword.
+ *  ============================================================================
+ */
+#define WORDSWAP_LONG(x) (   (((x) << 16u) & 0xFFFF0000u)    \
+                          |  (((x) >> 16u) & 0x0000FFFFu))
+
+/** ============================================================================
+ *  @macro  SWAP_LONG
+ *
+ *  @desc   Returns a word-swapped or non-swapped dword based on the parameter
+ *          passed.
+ *  ============================================================================
+ */
+#define SWAP_LONG(value, swap) (((swap) == FALSE) ?          \
+                                (value) : WORDSWAP_LONG (value))
+
+
+#if defined (__cplusplus)
+}
+#endif /* defined (__cplusplus) */
+
+
+#endif  /* !defined (_BITOPS_H) */

arch/arm/plat-omap/include/syslink/ducatienabler.h

+/*
+ * ducatienabler.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef _DDUCATIMMU_ENABLER_H_
+#define _DDUCATIMMU_ENABLER_H_
+
+#include <linux/types.h>
+#include <syslink/hw_defs.h>
+#include <syslink/hw_mmu.h>
+
+
+#define PAGE_SIZE_4KB				0x1000
+#define PAGE_SIZE_64KB				0x10000
+#define PAGE_SIZE_1MB				0x100000
+#define PAGE_SIZE_16MB				0x1000000
+
+/* Define the Peripheral PAs and their Ducati VAs. */
+#define L4_PERIPHERAL_MBOX			0x4A0F4000
+#define DSPVA_PERIPHERAL_MBOX			0xAA0F4000
+
+#define L4_PERIPHERAL_I2C1			0x48070000
+#define DSPVA_PERIPHERAL_I2C1			0xA8070000
+#define L4_PERIPHERAL_I2C2			0x48072000
+#define DSPVA_PERIPHERAL_I2C2			0xA8072000
+#define L4_PERIPHERAL_I2C3			0x48060000
+#define DSPVA_PERIPHERAL_I2C3			0xA8060000
+
+#define L4_PERIPHERAL_DMA			0x4A056000
+#define DSPVA_PERIPHERAL_DMA			0xAA056000
+
+#define L4_PERIPHERAL_GPIO1			0x4A310000
+#define DSPVA_PERIPHERAL_GPIO1		0xAA310000
+#define L4_PERIPHERAL_GPIO2			0x48055000
+#define DSPVA_PERIPHERAL_GPIO2		0xA8055000
+#define L4_PERIPHERAL_GPIO3			0x48057000
+#define DSPVA_PERIPHERAL_GPIO3		0xA8057000
+
+#define L4_PERIPHERAL_GPTIMER3			0x48034000
+#define DSPVA_PERIPHERAL_GPTIMER3		0xA8034000
+#define L4_PERIPHERAL_GPTIMER4			0x48036000
+#define DSPVA_PERIPHERAL_GPTIMER4		0xA8036000
+#define L4_PERIPHERAL_GPTIMER9			0x48040000
+#define DSPVA_PERIPHERAL_GPTIMER9		0xA8040000
+#define L4_PERIPHERAL_GPTIMER11		0x48088000
+#define DSPVA_PERIPHERAL_GPTIMER11		0xA8088000
+
+
+#define L3_TILER_VIEW0_ADDR			0x60000000
+#define DUCATIVA_TILER_VIEW0_ADDR		0x60000000
+#define DUCATIVA_TILER_VIEW0_LEN		0x20000000
+
+
+
+
+/* Define the various Ducati Memory Regions. */
+/* The first 4K page of BOOTVECS is programmed as a TLB entry. The remaining */
+/* three pages are not used and are mapped to minimize number of PTEs */
+#define DUCATI_BOOTVECS_ADDR			0x1000
+#define DUCATI_BOOTVECS_LEN			0x3000
+
+#define DUCATI_EXTMEM_SYSM3_ADDR		0x4000
+#define DUCATI_EXTMEM_SYSM3_LEN		0x1FC000
+
+#define DUCATI_EXTMEM_APPM3_ADDR		0x10000000
+#define DUCATI_EXTMEM_APPM3_LEN		0x200000
+
+#define DUCATI_PRIVATE_SYSM3_DATA_ADDR	0x84000000
+#define DUCATI_PRIVATE_SYSM3_DATA_LEN	0x200000
+
+#define DUCATI_PRIVATE_APPM3_DATA_ADDR	0x8A000000
+#define DUCATI_PRIVATE_APPM3_DATA_LEN	0x200000
+
+#define DUCATI_SHARED_M3_DATA_ADDR		0x90000000
+#define DUCATI_SHARED_M3_DATA_LEN		0x100000
+
+#define DUCATI_SHARED_IPC_ADDR		0x98000000
+#define DUCATI_SHARED_IPC_LEN			0x100000
+
+#define DUCATI_SW_DMM_ADDR			0x80000000
+#define DUCATI_SW_DMM_LEN			0x4000000
+
+
+/* Types of mapping attributes */
+
+/* MPU address is virtual and needs to be translated to physical addr */
+#define DSP_MAPVIRTUALADDR			0x00000000
+#define DSP_MAPPHYSICALADDR			0x00000001
+
+/* Mapped data is big endian */
+#define DSP_MAPBIGENDIAN			0x00000002
+#define DSP_MAPLITTLEENDIAN			0x00000000
+
+/* Element size is based on DSP r/w access size */
+#define DSP_MAPMIXEDELEMSIZE			0x00000004
+
+/*
+ * Element size for MMU mapping (8, 16, 32, or 64 bit)
+ * Ignored if DSP_MAPMIXEDELEMSIZE enabled
+ */
+#define DSP_MAPELEMSIZE8			0x00000008
+#define DSP_MAPELEMSIZE16			0x00000010
+#define DSP_MAPELEMSIZE32			0x00000020
+#define DSP_MAPELEMSIZE64			0x00000040
+
+#define DSP_MAPVMALLOCADDR			0x00000080
+
+struct mmu_entry {
+	u32 ul_phy_addr ;
+	u32 ul_virt_addr ;
+	u32 ul_size ;
+};
+
+struct memory_entry {
+	u32 ul_virt_addr;
+	u32 ul_size;
+};
+
+static const struct mmu_entry l4_map[] = {
+	/*  Mailbox 4KB*/
+	{L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB},
+};
+
+static const struct  memory_entry l3_memory_regions[] = {
+	/*  Remaining BootVecs regions */
+	{DUCATI_BOOTVECS_ADDR, DUCATI_BOOTVECS_LEN},
+	/*  EXTMEM_CORE0: 0x4000 to 0xFFFFF */
+	{DUCATI_EXTMEM_SYSM3_ADDR, DUCATI_EXTMEM_SYSM3_LEN},
+	/*  EXTMEM_CORE1: 0x10000000 to 0x100FFFFF */
+	{DUCATI_EXTMEM_APPM3_ADDR, DUCATI_EXTMEM_APPM3_LEN},
+	/*  PRIVATE_SYSM3_DATA*/
+	{DUCATI_PRIVATE_SYSM3_DATA_ADDR, DUCATI_PRIVATE_SYSM3_DATA_LEN},
+	/*  PRIVATE_APPM3_DATA*/
+	{DUCATI_PRIVATE_APPM3_DATA_ADDR, DUCATI_PRIVATE_APPM3_DATA_LEN},
+	/*  SHARED_M3_DATA*/
+	{DUCATI_SHARED_M3_DATA_ADDR, DUCATI_SHARED_M3_DATA_LEN},
+	/*  IPC*/
+	{DUCATI_SHARED_IPC_ADDR, DUCATI_SHARED_IPC_LEN},
+};
+
+void dbg_print_ptes(bool ashow_inv_entries, bool ashow_repeat_entries);
+int ducati_setup(void);
+void ducati_destroy(void);
+u32 get_ducati_virt_mem();
+
+#endif /* _DDUCATIMMU_ENABLER_H_*/

arch/arm/plat-omap/include/syslink/gate_remote.h

+/*
+ *  gate_remote.h
+ *
+ *  This includes the functions to handle remote gates
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _NAMESERVER_REMOTE_H_
+#define _GATE_REMOTE_H_
+
+#include <linux/types.h>
+
+/*
+ *  This function is used to enter in to a remote gate
+ */
+int gate_remote_enter(void *ghandle, u32 key);
+
+/*
+ *  This function is used to leave from a remote gate
+ */
+int gate_remote_leave(void *ghandle, u32 key);
+
+#endif /* _GATE_REMOTE_H_ */
+

arch/arm/plat-omap/include/syslink/gatepeterson.h

+/*
+ *  gatepeterson.h
+ *
+ *  The Gate Peterson Algorithm for mutual exclusion of shared memory.
+ *  Current implementation works for 2 processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _GATEPETERSON_H_
+#define _GATEPETERSON_H_
+
+#include <linux/types.h>
+
+/*
+ *  A set of context protection levels that each correspond to
+ *  single processor gates used for local protection
+ */
+enum gatepeterson_protect {
+	GATEPETERSON_PROTECT_DEFAULT,
+	GATEPETERSON_PROTECT_INTERRUPT,
+	GATEPETERSON_PROTECT_TASKLET,
+	GATEPETERSON_PROTECT_THREAD,
+	GATEPETERSON_PROTECT_PROCESS,
+	GATEPETERSON_PROTECT_NONE
+};
+
+/*
+ *  Structure defining config parameters for the Gate Peterson
+ *  module
+ */
+struct gatepeterson_config {
+	u32 max_name_len; /* GP name len */
+	enum gatepeterson_protect default_protection;
+	bool use_nameserver; /* Need a nameserver or not */
+	u32 max_runtime_entries; /* No of dynamic gps */
+	void *name_table_gate; /* for nameserver */
+};
+
+/*
+ *  Structure defining config parameters for the Gate Peterson
+ *  instances
+ */
+struct gatepeterson_params {
+	void *shared_addr;
+	u32 shared_addr_size;
+	char *name;
+	u16 opener_proc_id;
+	enum gatepeterson_protect local_protection;
+};
+
+/*
+ *  Function to initialize the parameter structure
+ */
+int gatepeterson_get_config(struct gatepeterson_config *config);
+
+/*
+ *  Function to initialize GP module
+ */
+int gatepeterson_setup(const struct gatepeterson_config *config);
+
+/*
+ *  Function to destroy the GP module
+ */
+int gatepeterson_destroy(void);
+
+/*
+ *  Function to initialize the parameter structure
+ */
+int gatepeterson_params_init(struct gatepeterson_params *params);
+
+/*
+ *  Function to create an instance of GatePeterson
+ */
+void *gatepeterson_create(const struct gatepeterson_params *params);
+
+/*
+ *  Function to delete an instance of GatePeterson
+ */
+int gatepeterson_delete(void **gphandle);
+
+/*
+ *  Function to open a previously created instance
+ */
+int gatepeterson_open(void **gphandle,
+			const struct gatepeterson_params *params);
+
+/*
+ *  Function to close a previously opened instance
+ */
+int gatepeterson_close(void **gphandle);
+
+/*
+ * Function to enter the gate peterson
+ */
+u32 gatepeterson_enter(void *gphandle);
+
+/*
+ *Function to leave the gate peterson
+ */
+void gatepeterson_leave(void *gphandle, u32 flag);
+
+
+/*
+ *  Returns the gatepeterson kernel object pointer
+ */
+void *gatepeterson_get_knl_handle(void **gpHandle);
+
+/*
+ * Function to return the shared memory requirement
+ */
+u32 gatepeterson_shared_memreq(const struct gatepeterson_params *params);
+
+#endif /* _GATEPETERSON_H_ */
+

arch/arm/plat-omap/include/syslink/gatepeterson_ioctl.h

+/*
+ *  gatepeterson_ioctl.h
+ *
+ *  The Gate Peterson Algorithm for mutual exclusion of shared memory.
+ *  Current implementation works for 2 processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _GATEPETERSON_IOCTL_
+#define _GATEPETERSON_IOCTL_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#include <ipc_ioctl.h>
+#include <gatepeterson.h>
+
+enum CMD_GATEPETERSON {
+	GATEPETERSON_GETCONFIG = GATEPETERSON_BASE_CMD,
+	GATEPETERSON_SETUP,
+	GATEPETERSON_DESTROY,
+	GATEPETERSON_PARAMS_INIT,
+	GATEPETERSON_CREATE,
+	GATEPETERSON_DELETE,
+	GATEPETERSON_OPEN,
+	GATEPETERSON_CLOSE,
+	GATEPETERSON_ENTER,
+	GATEPETERSON_LEAVE,
+	GATEPETERSON_SHAREDMEMREQ,
+};
+
+/*
+ *  IOCTL command IDs for gatepeterson
+ */
+
+/*
+ *  Command for gatepeterson_get_config
+ */
+#define CMD_GATEPETERSON_GETCONFIG	_IOWR(IPC_IOC_MAGIC,                   \
+					GATEPETERSON_GETCONFIG,                \
+					struct gatepeterson_cmd_args)
+
+/*
+ *  Command for gatepeterson_setup
+ */
+#define CMD_GATEPETERSON_SETUP		_IOW(IPC_IOC_MAGIC,                    \
+					GATEPETERSON_SETUP,                    \
+					struct gatepeterson_cmd_args)
+
+/*
+ *  Command for gatepeterson_setup
+ */
+#define CMD_GATEPETERSON_DESTROY	_IO(IPC_IOC_MAGIC,                     \
+					GATEPETERSON_DESTROY)
+
+/*
+ *  Command for gatepeterson_destroy
+ */
+#define CMD_GATEPETERSON_PARAMS_INIT	_IOWR(IPC_IOC_MAGIC,                   \
+					GATEPETERSON_PARAMS_INIT,              \
+					struct gatepeterson_cmd_args)
+
+/*
+ *  Command for gatepeterson_create
+ */
+#define CMD_GATEPETERSON_CREATE		_IOWR(IPC_IOC_MAGIC,                   \
+					GATEPETERSON_CREATE,                   \
+					struct gatepeterson_cmd_args)
+
+/*
+ *  Command for gatepeterson_delete
+ */
+#define CMD_GATEPETERSON_DELETE		_IOWR(IPC_IOC_MAGIC,                   \
+					GATEPETERSON_DELETE,                   \
+					struct gatepeterson_cmd_args)
+/*
+ *  Command for gatepeterson_open
+ */
+#define CMD_GATEPETERSON_OPEN		_IOWR(IPC_IOC_MAGIC,                   \
+					GATEPETERSON_OPEN,                     \
+					struct gatepeterson_cmd_args)
+
+/*
+ *  Command for gatepeterson_close
+ */
+#define CMD_GATEPETERSON_CLOSE		_IOWR(IPC_IOC_MAGIC,                   \
+					GATEPETERSON_CLOSE,                    \
+					struct gatepeterson_cmd_args)
+/*
+ *  Command for gatepeterson_enter
+ */
+#define CMD_GATEPETERSON_ENTER		_IOW(IPC_IOC_MAGIC,                    \
+					GATEPETERSON_ENTER,                    \
+					struct gatepeterson_cmd_args)
+
+/*
+ *  Command for gatepeterson_leave
+ */
+#define CMD_GATEPETERSON_LEAVE		_IOW(IPC_IOC_MAGIC,                    \
+					GATEPETERSON_LEAVE,                    \
+					struct gatepeterson_cmd_args)
+
+/*
+ *  Command for gatepeterson_shared_memreq
+ */
+#define CMD_GATEPETERSON_SHAREDMEMREQ	_IOWR(IPC_IOC_MAGIC,                   \
+					GATEPETERSON_SHAREDMEMREQ,             \
+					struct gatepeterson_cmd_args)
+
+/*
+ *  Command arguments for gatepeterson
+ */
+union gatepeterson_arg {
+	struct {
+		struct gatepeterson_params *params;
+	} params_init;
+
+	struct {
+		struct gatepeterson_config *config;
+	} get_config;
+
+	struct {
+		struct gatepeterson_config *config;
+	} setup;
+
+	struct {
+		void *handle;
+		struct gatepeterson_params *params;
+		u32 name_len;
+	} create;
+
+	struct {
+		void *handle;
+	} delete;
+
+	struct {
+		void *handle;
+		struct gatepeterson_params *params;
+		u32 name_len;
+	} open;
+
+	struct {
+		void *handle;
+	} close;
+
+	struct {
+		void *handle;
+		u32 flags;
+	} enter;
+
+	struct {
+		void *handle;
+		u32 flags;
+	} leave;
+
+	struct {
+		void *handle;
+		struct gatepeterson_params *params;
+		u32 bytes;
+	} shared_memreq;
+
+};
+
+/*
+ *  Command arguments for gatepeterson
+ */
+struct gatepeterson_cmd_args {
+	union gatepeterson_arg cmd_arg;
+	s32 api_status;
+};
+
+/*
+ *  This ioctl interface for gatepeterson module
+ */
+int gatepeterson_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args);
+
+#endif /* _GATEPETERSON_IOCTL_ */
+

arch/arm/plat-omap/include/syslink/gt.h

+
+/*
+ * gt.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ *  ======== gt.h ========
+ *  Purpose:
+ *	There are two definitions that affect which portions of trace
+ *	are acutally compiled into the client: GT_TRACE and GT_ASSERT. If
+ *	GT_TRACE is set to 0 then all trace statements (except for assertions)
+ *	will be compiled out of the client. If GT_ASSERT is set to 0 then
+ *	assertions will be compiled out of the client. GT_ASSERT can not be
+ *	set to 0 unless GT_TRACE is also set to 0 (i.e. GT_TRACE == 1 implies
+ *	GT_ASSERT == 1).
+ *
+ *! Revision History
+ *! ================
+ *! 02-Feb-2000 rr:	Renamed this file to gtce.h. GT CLASS and trace
+ *!			definitions are WinCE Specific.
+ *! 03-Jan-1997	ge	Replaced "GT_" prefix to GT_Config structure members
+ *!			to eliminate preprocessor confusion with other macros.
+ */
+#include <linux/types.h>
+#ifndef GT_
+#define GT_
+
+#ifndef GT_TRACE
+#define GT_TRACE 0	/* 0 = "trace compiled out"; 1 = "trace active" */
+#endif
+
+/* #include <syslink/host_os.h> */
+
+typedef s32(*Fxn)();	/* generic function type */
+
+
+#if !defined(GT_ASSERT) || GT_TRACE
+#define GT_ASSERT 1
+#endif
+
+struct GT_Config {
+	Fxn PRINTFXN;
+	Fxn PIDFXN;
+	Fxn TIDFXN;
+	Fxn ERRORFXN;
+};
+
+extern struct GT_Config *GT;
+
+struct gt_mask {
+	char *modName;
+	u8 *flags;
+} ;
+
+/*
+ *  New GT Class defenitions.
+ *
+ *  The following are the explanations and how it could be used in the code
+ *
+ *  -   GT_ENTER	On Entry to Functions
+ *
+ *  -   GT_1CLASS	Display level of debugging status- Object/Automatic
+ *			variables
+ *  -   GT_2CLASS	---- do ----
+ *
+ *  -   GT_3CLASS	 ---- do ---- + It can be used(recommended) for debug
+ *			status in the ISR, IST
+ *  -   GT_4CLASS	---- do ----
+ *
+ *  -   GT_5CLASS	Display entry for module init/exit functions
+ *
+ *  -   GT_6CLASS	Warn whenever SERVICES function fails
+ *
+ *  -   GT_7CLASS	Warn failure of Critical failures
+ *
+ */
+
+#define GT_ENTER	((u8)0x01)
+#define GT_1CLASS	((u8)0x02)
+#define GT_2CLASS	((u8)0x04)
+#define GT_3CLASS	((u8)0x08)
+#define GT_4CLASS	((u8)0x10)
+#define GT_5CLASS	((u8)0x20)
+#define GT_6CLASS	((u8)0x40)
+#define GT_7CLASS	((u8)0x80)
+#define GT_LEAVE	((u8)0x02)
+
+#ifdef _LINT_
+
+/* LINTLIBRARY */
+
+/*
+ *  ======== GT_assert ========
+ */
+/* ARGSUSED */
+void GT_assert(struct gt_mask mask, s32 expr)
+{
+}
+
+/*
+ *  ======== GT_config ========
+ */
+/* ARGSUSED */
+void GT_config(struct GT_Config config)
+{
+}
+
+/*
+ *  ======== GT_create ========
+ */
+/* ARGSUSED */
+void GT_create(struct gt_mask *mask, char *modName)
+{
+}
+
+/*
+ *  ======== GT_curline ========
+ *  Purpose:
+ *	Returns the current source code line number. Is useful for performing
+ *	branch testing using trace.  For example,
+ *
+ *	gt_1trace(curTrace, GT_1CLASS,
+ *	  "in module XX_mod, executing line %u\n", GT_curline());
+ */
+/* ARGSUSED */
+u16 GT_curline(void)
+{
+	return (u16)NULL;
+}
+
+/*
+ *  ======== GT_exit ========
+ */
+/* ARGSUSED */
+void GT_exit(void)
+{
+}
+
+/*
+ *  ======== GT_init ========
+ */
+/* ARGSUSED */
+void GT_init(void)
+{
+}
+
+/*
+ *  ======== GT_query ========
+ */
+/* ARGSUSED */
+bool GT_query(struct gt_mask mask, u8 class)
+{
+	return false;
+}
+
+/*
+ *  ======== GT_set ========
+ *  sets trace mask according to settings
+ */
+
+/* ARGSUSED */
+void GT_set(char *settings)
+{
+}
+
+/*
+ *  ======== GT_setprintf ========
+ *  sets printf function
+ */
+
+/* ARGSUSED */
+void GT_setprintf(Fxn fxn)
+{
+}
+
+/* ARGSUSED */
+void gt_0trace(struct gt_mask mask, u8 class, char *format)
+{
+}
+
+/* ARGSUSED */
+void gt_1trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void gt_2trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void gt_3trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void gt_4trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void gt_5trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void GT_6trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+#else
+
+#define	GT_BOUND	26	/* 26 letters in alphabet */
+
+extern void _GT_create(struct gt_mask *mask, char *modName);
+
+#define GT_exit()
+
+extern void GT_init(void);
+extern void _GT_set(char *str);
+extern s32 _GT_trace(struct gt_mask *mask, char *format, ...);
+
+#if GT_ASSERT == 0
+
+#define GT_assert(mask, expr)
+#define GT_config(config)
+#define GT_configInit(config)
+#define GT_seterror(fxn)
+
+#else
+
+extern struct GT_Config _GT_params;
+
+#define GT_assert(mask, expr) \
+	(!(expr) ? \
+		printk(KERN_ALERT "assertion violation: %s, line %d\n", \
+				__FILE__, __LINE__), NULL : NULL)
+
+#define GT_config(config)		(_GT_params = *(config))
+#define GT_configInit(config)		(*(config) = _GT_params)
+#define GT_seterror(fxn)		(_GT_params.ERRORFXN = (Fxn)(fxn))
+
+#endif
+
+#if GT_TRACE == 0
+
+#define GT_curline()			((u16)__LINE__)
+#define GT_create(mask, modName)
+#define GT_exit()
+#define GT_init()
+#define GT_set(settings)
+#define GT_setprintf(fxn)
+
+#define GT_query(mask, class)		false
+
+#define gt_0trace(mask, class, format)
+#define gt_1trace(mask, class, format, arg1)
+#define gt_2trace(mask, class, format, arg1, arg2)
+#define gt_3trace(mask, class, format, arg1, arg2, arg3)
+#define gt_4trace(mask, class, format, arg1, arg2, arg3, arg4)
+#define gt_5trace(mask, class, format, arg1, arg2, arg3, arg4, arg5)
+#define GT_6trace(mask, class, format, arg1, arg2, arg3, arg4, arg5, arg6)
+
+#else				/* GT_TRACE == 1 */
+
+#define GT_create(mask, modName)	_GT_create((mask), (modName))
+#define GT_curline()			((u16)__LINE__)
+#define GT_set(settings)		_GT_set(settings)
+#define GT_setprintf(fxn)		(_GT_params.PRINTFXN = (Fxn)(fxn))
+
+#define GT_query(mask, class) ((*(mask).flags & (class)))
+
+#define gt_0trace(mask, class, format) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format)) : 0)
+
+#define gt_1trace(mask, class, format, arg1) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1)) : 0)
+
+#define gt_2trace(mask, class, format, arg1, arg2) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2)) : 0)
+
+#define gt_3trace(mask, class, format, arg1, arg2, arg3) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2), (arg3)) : 0)
+
+#define gt_4trace(mask, class, format, arg1, arg2, arg3, arg4) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4)) : 0)
+
+#define gt_5trace(mask, class, format, arg1, arg2, arg3, arg4, arg5) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4), (arg5)) \
+	 : 0)
+
+#define GT_6trace(mask, class, format, arg1, arg2, arg3, arg4, arg5, arg6) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4), (arg5), \
+	(arg6)) : 0)
+
+#endif				/* GT_TRACE */
+
+#endif				/* _LINT_ */
+
+#endif				/* GTCE_ */

arch/arm/plat-omap/include/syslink/heap.h

+/*
+ *  heap.h
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _HEAP_H_
+#define _HEAP_H_
+
+#include <linux/types.h>
+
+/*
+ *  Structure defining memory related statistics
+ */
+struct memory_stats{
+	u32 *total_size; /* Total memory size */
+	u32 *total_free_size; /* Total free memory size */
+	u32 *largest_free_size; /* Largest free memory size */
+};
+
+/*!
+ *  ======== extendedstats ========
+ *  Stats structure for the get_extended_stats API.
+ *
+ *  max_allocated_blocks: The maximum number of blocks allocated
+ *  from this heap at any single point in time during the lifetime of this
+ *  heap instance.
+ *
+ *  num_allocated_blocks: The total number of blocks currently
+ *  allocated in this Heap instance.
+ */
+struct heap_extended_stats {
+	u32 max_allocated_blocks;
+	u32 num_allocated_blocks;
+};
+
+/*
+ *  Structure defining config parameters for the heapbuf module
+ */
+struct heap_config {
+	u32 max_name_len; /* Maximum length of name */
+	bool track_max_allocs; /* Track the max number of allocated blocks */
+};
+
+/*
+ *  Structure for the handle for the heap
+ */
+struct heap_object {
+	void* (*alloc) (void *handle, u32 size, u32 align);
+	int (*free) (void *handle, void *block, u32 size);
+	int (*get_stats) (void *handle, struct memory_stats *stats);
+	int (*get_extended_stats) (void *handle,
+				struct heap_extended_stats *stats);
+	void *obj;
+};
+
+/*
+ *  Allocate a block
+ */
+void *heap_alloc(void *handle, u32 size, u32 align);
+
+/*
+ *  Frees the block to this Heap
+ */
+int heap_free(void *handle, void *block, u32 size);
+
+/*
+ * Get heap statistics
+ */
+int heap_get_stats(void *handle, struct memory_stats *stats);
+
+/*
+ * Get heap extended statistics
+ */
+int heap_get_extended_stats(void *hphandle,
+				struct heap_extended_stats *stats);
+
+#endif /* _HEAP_H_ */
+

arch/arm/plat-omap/include/syslink/heapbuf.h

+/*
+ *  heapbuf.h
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _HEAPBUF_H_
+#define _HEAPBUF_H_
+
+#include <linux/types.h>
+#include <heap.h>
+#include <listmp.h>
+
+/*
+ *  Creation of Heap Buf succesful.
+*/
+#define HEAPBUF_CREATED            (0x05251995)
+
+/*
+ *  Version.
+ */
+#define HEAPBUF_VERSION            (1)
+
+/*
+ *  Structure defining parameters for the Heap Buf module
+ */
+struct heapbuf_params {
+	void *lock_handle;
+	bool exact; /* Only allocate on exact match of rquested size */
+	char *name; /* Name when using nameserver */
+	u32 align; /* Alignment (in MAUs, power of 2) of each block */
+	u32 num_blocks; /* Number of fixed-size blocks */
+	u32 block_size; /* Size (in MAUs) of each block*/
+	void *shared_addr; /* Physical address of the shared memory */
+	u32 shared_addr_size; /* Size of shareAddr  */
+};
+
+/*
+ *  Function to get default configuration for the heapbuf module
+ */
+int heapbuf_get_config(struct heap_config *cfgparams);
+
+/*
+ *  Function to setup the heapbuf module
+ */
+int heapbuf_setup(const struct heap_config *config);
+
+/*
+ *  Function to destroy the heapbuf module
+ */
+int heapbuf_destroy(void);
+
+/* Initialize this config-params structure with supplier-specified
+ *  defaults before instance creation
+ */
+void heapbuf_params_init(void *handle, struct heapbuf_params *params);
+
+/*
+ *  Creates a new instance of heapbuf module
+ */
+void *heapbuf_create(const struct heapbuf_params *params);
+
+/*
+ * Deletes a instance of heapbuf module
+ */
+int heapbuf_delete(void **handle);
+
+/*
+ *  Opens a created instance of heapbuf module
+ */
+int heapbuf_open(void **handle, const struct heapbuf_params *params);
+
+/*
+ *  Closes previously opened/created instance of heapbuf module
+ */
+int heapbuf_close(void *handle);
+
+/*
+ *  Returns the amount of shared memory required for creation
+ *  of each instance
+ */
+int heapbuf_shared_memreq(const struct heapbuf_params *params);
+
+/*
+ *  Allocate a block
+ */
+void *heapbuf_alloc(void *handle, u32 size, u32 align);
+
+/*
+ *  Frees the block to this heapbuf
+ */
+int heapbuf_free(void *handle, void *block, u32 size);
+
+/*
+ *  Get memory statistics
+ */
+int heapbuf_get_stats(void *handle, struct memory_stats *stats);
+
+/*
+ *  Get extended statistics
+ */
+int heapbuf_get_extended_stats(void *handle, struct heap_extended_stats *stats);
+#endif /* _HEAPBUF_H_ */
+

arch/arm/plat-omap/include/syslink/heapbuf_ioctl.h

+/*
+ *  heapbuf_ioctl.h
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _HEAPBUF_IOCTL_
+#define _HEAPBUF_IOCTL_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#include <ipc_ioctl.h>
+#include <heap.h>
+#include <heapbuf.h>
+
+
+enum CMD_HEAPBUF {
+	HEAPBUF_GETCONFIG = HEAPBUF_BASE_CMD,
+	HEAPBUF_SETUP,
+	HEAPBUF_DESTROY,
+	HEAPBUF_PARAMS_INIT,
+	HEAPBUF_CREATE,
+	HEAPBUF_DELETE,
+	HEAPBUF_OPEN,
+	HEAPBUF_CLOSE,
+	HEAPBUF_ALLOC,
+	HEAPBUF_FREE,
+	HEAPBUF_SHAREDMEMREQ,
+	HEAPBUF_GETSTATS,
+	HEAPBUF_GETEXTENDEDSTATS,
+};
+
+/*
+ *  Command for heapbuf_get_config
+ */
+#define CMD_HEAPBUF_GETCONFIG		_IOWR(IPC_IOC_MAGIC, HEAPBUF_GETCONFIG,\
+					 struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_setup
+ */
+#define CMD_HEAPBUF_SETUP		_IOW(IPC_IOC_MAGIC, HEAPBUF_SETUP,     \
+					 struct heapbuf_cmd_args)
+/*
+ *  Command for heapbuf_destroy
+ */
+#define CMD_HEAPBUF_DESTROY 		_IO(IPC_IOC_MAGIC, HEAPBUF_DESTROY)    \
+
+/*
+ *  Command for heapbuf_prams_init
+ */
+#define CMD_HEAPBUF_PARAMS_INIT 	_IOWR(IPC_IOC_MAGIC,                   \
+					HEAPBUF_PARAMS_INIT,                   \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_create
+ */
+#define CMD_HEAPBUF_CREATE 		_IOWR(IPC_IOC_MAGIC, HEAPBUF_CREATE,   \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_delete
+ */
+#define CMD_HEAPBUF_DELETE 		_IOW(IPC_IOC_MAGIC, HEAPBUF_DELETE,    \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_open
+ */
+#define CMD_HEAPBUF_OPEN 		_IOWR(IPC_IOC_MAGIC, HEAPBUF_OPEN,     \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_close
+ */
+#define CMD_HEAPBUF_CLOSE 		_IOW(IPC_IOC_MAGIC, HEAPBUF_CLOSE,     \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_alloc
+ */
+#define CMD_HEAPBUF_ALLOC 		_IOWR(IPC_IOC_MAGIC, HEAPBUF_ALLOC,    \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_free
+ */
+#define CMD_HEAPBUF_FREE	 	_IOW(IPC_IOC_MAGIC, HEAPBUF_FREE,      \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_shared_memreq
+ */
+#define CMD_HEAPBUF_SHAREDMEMREQ	_IOWR(IPC_IOC_MAGIC,                   \
+					HEAPBUF_SHAREDMEMREQ,                  \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_get_stats
+ */
+#define CMD_HEAPBUF_GETSTATS		_IOWR(IPC_IOC_MAGIC,                   \
+					HEAPBUF_GETSTATS,                      \
+					struct heapbuf_cmd_args)
+
+/*
+ *  Command for heapbuf_get_extended_stats
+ */
+#define CMD_HEAPBUF_GETEXTENDEDSTATS	_IOWR(IPC_IOC_MAGIC,                   \
+					HEAPBUF_GETEXTENDEDSTATS,              \
+					struct heapbuf_cmd_args)
+
+
+/*
+ *  Command arguments for heapbuf
+ */
+union heapbuf_arg {
+	struct {
+		void *handle;
+		struct heapbuf_params *params;
+	} params_init;
+
+	struct  {
+		struct heap_config *config;
+	} get_config;
+
+	struct {
+		struct heap_config *config;
+	} setup;
+
+	struct {
+		void *handle;
+		struct heapbuf_params *params;
+		u32 name_len;
+	} create;
+
+	struct {
+		void *handle;
+	} delete;
+
+	struct {
+		void *handle;
+		struct heapbuf_params *params;
+		u32 name_len;
+	} open;
+
+	struct {
+		void *handle;
+	} close;
+
+	struct {
+		void *handle;
+		u32 size;
+		u32 align;
+		u32 *block_srptr;
+	} alloc;
+
+	struct {
+		void *handle;
+		u32 *block_srptr;
+		u32 size;
+	} free;
+
+	struct {
+		void *handle;
+		struct memory_stats *stats;
+	} get_stats;
+
+	struct {
+		void *handle;
+		struct heap_extended_stats *stats;
+	} get_extended_stats;
+
+	struct {
+		void *handle;
+		struct heapbuf_params *params;
+		u32 bytes;
+	} shared_memreq;
+};
+
+/*
+ *  Command arguments for heapbuf
+ */
+struct heapbuf_cmd_args{
+	union heapbuf_arg cmd_arg;
+	s32 api_status;
+};
+
+/*
+ *  This ioctl interface for heapbuf module
+ */
+int heapbuf_ioctl(struct inode *pinode, struct file *filp,
+			unsigned int cmd, unsigned long  args);
+
+#endif /* _HEAPBUF_IOCTL_ */
+

arch/arm/plat-omap/include/syslink/host_os.h

+
+/*
+ * host_os.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ *  ======== windows.h ========
+ *
+ *! Revision History
+ *! ================
+ *! 08-Mar-2004 sb Added cacheflush.h to support Dynamic Memory Mapping feature
+ *! 16-Feb-2004 sb Added headers required for consistent_alloc
+ */
+
+#ifndef _HOST_OS_H_
+#define _HOST_OS_H_
+
+#include <linux/autoconf.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <linux/semaphore.h>
+#include <linux/uaccess.h>
+#include <asm/irq.h>
+#include <linux/io.h>
+#include <linux/syscalls.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/stddef.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/file.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/ctype.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/vmalloc.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/pagemap.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+
+/*  ----------------------------------- Macros */
+
+#define SEEK_SET        0	/* Seek from beginning of file.  */
+#define SEEK_CUR        1	/* Seek from current position.  */
+#define SEEK_END        2	/* Seek from end of file.  */
+
+/* TODO -- Remove, once BP defines them */
+#define INT_MAIL_MPU_IRQ        26
+#define INT_DSP_MMU_IRQ        28
+
+#endif

arch/arm/plat-omap/include/syslink/hw_defs.h

+
+/*
+ * hw_defs.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ *  ======== hw_defs.h ========
+ *  Description:
+ *      Global HW definitions
+ *
+ *! Revision History:
+ *! ================
+ *! 19 Apr 2004 sb: Added generic page size, endianness and element size defns
+ *! 16 Feb 2003 sb: Initial version
+ */
+#ifndef __HW_DEFS_H
+#define __HW_DEFS_H
+
+#include <syslink/GlobalTypes.h>
+
+/* Page size */
+#define HW_PAGE_SIZE_4KB   0x1000
+#define HW_PAGE_SIZE_64KB  0x10000
+#define HW_PAGE_SIZE_1MB   0x100000
+#define HW_PAGE_SIZE_16MB  0x1000000
+
+/* hw_status:  return type for HW API */
+typedef long hw_status;
+
+/* hw_set_clear_t:  Enumerated Type used to set and clear any bit */
+enum hw_set_clear_t {
+    HW_CLEAR,
+    HW_SET
+} ;
+
+/* hw_endianism_t:  Enumerated Type used to specify the endianism
+ *		Do NOT change these values. They are used as bit fields. */
+enum hw_endianism_t {
+    HW_LITTLE_ENDIAN,
+    HW_BIG_ENDIAN
+
+} ;
+
+/* hw_elemnt_siz_t:  Enumerated Type used to specify the element size
+ *		Do NOT change these values. They are used as bit fields. */
+enum hw_elemnt_siz_t {
+    HW_ELEM_SIZE_8BIT,
+    HW_ELEM_SIZE_16BIT,
+    HW_ELEM_SIZE_32BIT,
+    HW_ELEM_SIZE_64BIT
+
+} ;
+
+/* HW_IdleMode_t:  Enumerated Type used to specify Idle modes */
+	enum HW_IdleMode_t {
+		HW_FORCE_IDLE,
+		HW_NO_IDLE,
+		HW_SMART_IDLE
+	} ;
+
+#endif  /* __HW_DEFS_H */

arch/arm/plat-omap/include/syslink/hw_mmu.h

+
+
+/*
+ * hw_mmu.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ *  ======== hw_mmu.h ========
+ *  Description:
+ *      MMU types and API declarations
+ *
+ *! Revision History:
+ *! ================
+ *! 19-Apr-2004 sb  Moved & renamed endianness, page size, element size
+		    TLBAdd takes in MMUMap_attrs instead of separate arguments
+ *! 08-Mar-2004 sb  Added the Page Table management APIs
+ *! 16 Feb 2003 sb: Initial version
+ */
+#ifndef __HW_MMU_H
+#define __HW_MMU_H
+
+#include <linux/types.h>
+
+/* Bitmasks for interrupt sources */
+#define HW_MMU_TRANSLATION_FAULT   0x2
+#define HW_MMU_ALL_INTERRUPTS      0x1F
+
+#define HW_MMU_COARSE_PAGE_SIZE 0x400
+
+/* hw_mmu_mixed_size_t:  Enumerated Type used to specify whether to follow
+			CPU/TLB Element size */
+enum hw_mmu_mixed_size_t {
+	HW_MMU_TLBES,
+	HW_MMU_CPUES
+
+} ;
+
+/* hw_mmu_map_attrs_t:  Struct containing MMU mapping attributes */
+struct hw_mmu_map_attrs_t {
+	enum hw_endianism_t     endianism;
+	enum hw_elemnt_siz_t   element_size;
+	enum hw_mmu_mixed_size_t  mixedSize;
+} ;
+
+extern hw_status hw_mmu_enable(const u32 base_address);
+
+extern hw_status hw_mmu_disable(const u32 base_address);
+
+extern hw_status hw_mmu_numlocked_set(const u32 base_address,
+					u32 num_lcked_entries);
+
+extern hw_status hw_mmu_victim_numset(const u32 base_address,
+					u32 vctm_entry_num);
+
+/* For MMU faults */
+extern hw_status hw_mmu_eventack(const u32 base_address,
+				    u32 irq_mask);
+
+extern hw_status hw_mmu_event_disable(const u32 base_address,
+					u32 irq_mask);
+
+extern hw_status hw_mmu_event_enable(const u32 base_address,
+				       u32 irq_mask);
+
+extern hw_status hw_mmu_event_status(const u32 base_address,
+				       u32 *irq_mask);
+
+extern hw_status hw_mmu_flt_adr_rd(const u32 base_address,
+					 u32 *addr);
+
+/* Set the TT base address */
+extern hw_status hw_mmu_ttbset(const u32 base_address,
+				  u32 ttb_phys_addr);
+
+extern hw_status hw_mmu_twl_enable(const u32 base_address);
+
+extern hw_status hw_mmu_twl_disable(const u32 base_address);
+
+extern hw_status hw_mmu_tlb_flush(const u32 base_address,
+				    u32 virtual_addr,
+				    u32 page_size);
+
+extern hw_status hw_mmu_tlb_flushAll(const u32 base_address);
+
+extern hw_status hw_mmu_tlb_add(const u32     base_address,
+				  u32	   physical_addr,
+				  u32	   virtual_addr,
+				  u32	   page_size,
+				  u32	    entryNum,
+				  struct hw_mmu_map_attrs_t *map_attrs,
+				  enum hw_set_clear_t    preserve_bit,
+				  enum hw_set_clear_t    valid_bit);
+
+
+/* For PTEs */
+extern hw_status hw_mmu_pte_set(const u32     pg_tbl_va,
+				  u32	   physical_addr,
+				  u32	   virtual_addr,
+				  u32	   page_size,
+				  struct hw_mmu_map_attrs_t *map_attrs);
+
+extern hw_status hw_mmu_pt_clear(const u32   pg_tbl_va,
+				    u32	 pg_size,
+				    u32	 virtual_addr);
+
+static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va)
+{
+	u32 pte_addr;
+	u32 VA_31_to_20;
+
+	VA_31_to_20  = va >> (20 - 2); /* Left-shift by 2 here itself */
+	VA_31_to_20 &= 0xFFFFFFFCUL;
+	pte_addr = l1_base + VA_31_to_20;
+
+	return pte_addr;
+}
+
+static inline u32 hw_mmu_pte_addr_l2(u32 l2_base, u32 va)
+{
+	u32 pte_addr;
+
+	pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC);
+
+	return pte_addr;
+}
+
+static inline u32 hw_mmu_pte_coarsel1(u32 pte_val)
+{
+	u32 pteCoarse;
+
+	pteCoarse = pte_val & 0xFFFFFC00;
+
+	return pteCoarse;
+}
+
+static inline u32 hw_mmu_pte_sizel1(u32 pte_val)
+{
+	u32 pte_size = 0;
+
+	if ((pte_val & 0x3) == 0x1) {
+		/* Points to L2 PT */
+		pte_size = HW_MMU_COARSE_PAGE_SIZE;
+	}
+
+	if ((pte_val & 0x3) == 0x2) {
+		if (pte_val & (1 << 18))
+			pte_size = HW_PAGE_SIZE_16MB;
+		else
+			pte_size = HW_PAGE_SIZE_1MB;
+	}
+
+	return pte_size;
+}
+
+static inline u32 hw_mmu_pte_sizel2(u32 pte_val)
+{
+    u32 pte_size = 0;
+
+    if (pte_val & 0x2)
+	pte_size = HW_PAGE_SIZE_4KB;
+    else if (pte_val & 0x1)
+	pte_size = HW_PAGE_SIZE_64KB;
+
+    return pte_size;
+}
+extern hw_status hw_mmu_tlb_dump(u32 base_address, bool shw_inv_entries);
+
+extern u32 hw_mmu_pte_phyaddr(u32 pte_val, u32 pte_size);
+
+#endif  /* __HW_MMU_H */

arch/arm/plat-omap/include/syslink/hw_ocp.h

+
+/*  =================================================================
+  File hw_ocp.h
+
+  Path $ (PROJROOT)\driver\mailbox
+
+  Desc API declarations for generic OCP Socket system registers for Mailbox
+
+  Rev  0.1.0
+
+  This computer program is copyright to Texas Instruments Incorporated.
+  The program may not be used without the written permission of
+  Texas Instruments Incorporated or against the terms and conditions
+  stipulated in the agreement under which this program has been supplied.
+
+  (c) Texas Instruments Incorporated 2008
+
+  =====================================================================
+*/
+#ifndef __HW_OCP_H
+#define __HW_OCP_H
+
+/* ========================================================================
+* INCLUDE FILES (only if necessary)
+* =========================================================================
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+
+#endif
+
+#include <syslink/GlobalTypes.h>
+#include <syslink/hw_ocp.h>
+#include <syslink/hw_defs.h>
+#include <syslink/MBXRegAcM.h>
+#include <syslink/MBXAccInt.h>
+
+
+/* =======================================================================
+* EXPORTED DEFINITIONS
+* ========================================================================
+*/
+
+
+/* =======================================================================
+* EXPORTED TYPES
+* ========================================================================
+*/
+
+/* -----------------------------------------------------------------------
+* TYPE:         HW_IdleMode_t
+*
+* DESCRIPTION:  Enumerated Type for idle modes in OCP SYSCONFIG register
+*
+* -------------------------------------------------------------------------
+*/
+enum hal_ocp_idlemode_t {
+HW_OCP_FORCE_IDLE,
+HW_OCP_NO_IDLE,
+HW_OCP_SMART_IDLE
+};
+
+/* =======================================================================
+* EXPORTED VARIABLES
+* ========================================================================
+*/
+
+
+/* =======================================================================
+* EXPORTED FUNCTIONS
+* ========================================================================
+*/
+
+extern long hw_ocp_soft_reset(const unsigned long base_address);
+
+extern long hw_ocp_soft_reset_isdone(const unsigned long base_address,
+				unsigned long *reset_is_done);
+
+extern long hw_ocp_idle_modeset(const unsigned long base_address,
+				enum hal_ocp_idlemode_t idle_mode);
+
+extern long hw_ocp_idlemode_get(const unsigned long base_address,
+				enum hal_ocp_idlemode_t *idle_mode);
+
+extern long hw_ocp_autoidle_set(const unsigned long base_address,
+				enum hw_set_clear_t auto_idle);
+
+extern long hw_ocp_autoidle_get(const unsigned long base_address,
+				enum hw_set_clear_t *auto_idle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __HW_OCP_H */
+

arch/arm/plat-omap/include/syslink/ipc_ioctl.h

+/*
+ *  ipc_ioctl.h
+ *
+ *  Base file for all TI OMAP IPC ioctl's.
+ *  Linux-OMAP IPC has allocated base 0xEE with a range of 0x00-0xFF.
+ *  (need to get  the real one from open source maintainers)
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _IPC_IOCTL_H
+#define _IPC_IOCTL_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+
+#define IPC_IOC_MAGIC		0xE0
+#define IPC_IOC_BASE		0
+
+enum ipc_command_count {
+	MULTIPROC_CMD_NOS = 3,
+	NAMESERVER_CMD_NOS = 13,
+	HEAPBUF_CMD_NOS	= 13,
+	SHAREDREGION_CMD_NOS = 10,
+	GATEPETERSON_CMD_NOS = 11,
+	LISTMP_SHAREDMEMORY_CMD_NOS = 18,
+	MESSAGEQ_CMD_NOS = 17,
+	MESSAGEQ_TRANSPORTSHM_CMD_NOS = 9
+};
+
+enum ipc_command_ranges {
+	MULTIPROC_BASE_CMD = IPC_IOC_BASE,
+	MULTIPROC_END_CMD = (MULTIPROC_BASE_CMD + \
+				MULTIPROC_CMD_NOS - 1),
+
+	NAMESERVER_BASE_CMD = 10,
+	NAMESERVER_END_CMD = (NAMESERVER_BASE_CMD + \
+				NAMESERVER_CMD_NOS - 1),
+
+	HEAPBUF_BASE_CMD = 30,
+	HEAPBUF_END_CMD = (HEAPBUF_BASE_CMD + \
+				HEAPBUF_CMD_NOS - 1),
+
+	SHAREDREGION_BASE_CMD = 50,
+	SHAREDREGION_END_CMD = (SHAREDREGION_BASE_CMD + \
+				SHAREDREGION_CMD_NOS - 1),
+
+	GATEPETERSON_BASE_CMD = 70,
+	GATEPETERSON_END_CMD = (GATEPETERSON_BASE_CMD + \
+				GATEPETERSON_CMD_NOS - 1),
+
+	LISTMP_SHAREDMEMORY_BASE_CMD = 90,
+	LISTMP_SHAREDMEMORY_END_CMD = (LISTMP_SHAREDMEMORY_BASE_CMD + \
+				LISTMP_SHAREDMEMORY_CMD_NOS - 1),
+
+	MESSAGEQ_BASE_CMD = 110,
+	MESSAGEQ_END_CMD = (MESSAGEQ_BASE_CMD + \
+				MESSAGEQ_CMD_NOS - 1),
+
+	MESSAGEQ_TRANSPORTSHM_BASE_CMD = 130,
+	MESSAGEQ_TRANSPORTSHM_END_CMD = (MESSAGEQ_TRANSPORTSHM_BASE_CMD + \
+				MESSAGEQ_TRANSPORTSHM_CMD_NOS - 1)
+};
+
+int ipc_ioc_router(u32 cmd, ulong arg);
+
+#endif /* _IPC_IOCTL_H */
+

arch/arm/plat-omap/include/syslink/list.h

+
+/*
+ * list.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ *  ======== list.h ========
+ *  Purpose:
+ *      Declarations of list management control structures and definitions
+ *      of inline list management functions.
+ *
+ *  Public Functions:
+ *
+ *  Notes:
+ *
+ *! Revision History
+ *! ================
+ */
+
+#ifndef NOTIFY_LIST
+#define NOTIFY_LIST
+#include<linux/list.h>
+#include <syslink/host_os.h>
+
+
+struct lst_list {
+	struct list_head head;
+} ;
+
+
+/** ==========================================================================
+ *  @name   ListMatchFunc
+ *
+ *  @desc   Signature of the Matching function to be used by search algo.
+ *
+ *  @arg    elem
+ *              Element to be compared.
+ *  @arg    data
+ *              Comparing key data.
+ *
+ *  @ret    TRUE or FALSE.
+ *
+ *  @enter  None.
+ *
+ *  @leave  None.
+ *
+ *  @see    None.
+ *  ==========================================================================*/
+
+typedef bool (*ListMatchFunc)(struct list_head *elem, void  *data);
+
+
+
+extern signed long int omap_list_search(struct lst_list *list,
+					void  *data,
+					struct list_head **elem,
+					 ListMatchFunc  matchFunc);
+
+#endif				/* NOTIFY_LIST */
+

arch/arm/plat-omap/include/syslink/listmp.h

+/*
+ *  listmp.h
+ *
+ *  The listmp module defines the shared memory doubly linked list.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _LISTMP_H_
+#define _LISTMP_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/list.h>
+/*#include <heap.h>*/
+
+/* =============================================================================
+ *  All success and failure codes for the module
+ * =============================================================================
+ */
+/*!
+ *  @def	LISTMP_MODULEID
+ *  @brief  Unique module ID.
+ */
+#define LISTMP_MODULEID	(0xa413)
+
+/*!
+ *  @def	LISTMP_ERRORCODEBASE
+ *  @brief  Error code base for ListMP.
+ */
+#define LISTMP_ERRORCODEBASE	(LISTMP_MODULEID << 12)
+
+/*!
+ *  @def	LISTMP_MAKE_FAILURE
+ *  @brief  Macro to make error code.
+ */
+#define LISTMP_MAKE_FAILURE(x)	((int)(0x80000000 \
+				 + (LISTMP_ERRORCODEBASE + (x))))
+
+/*!
+ *  @def	LISTMP_MAKE_SUCCESS
+ *  @brief  Macro to make success code.
+ */
+#define LISTMP_MAKE_SUCCESS(x)	(LISTMP_ERRORCODEBASE + (x))
+
+/*!
+ *  @def	LISTMP_E_INVALIDARG
+ *  @brief  Argument passed to a function is invalid.
+ */
+#define LISTMP_E_INVALIDARG	LISTMP_MAKE_FAILURE(1)
+
+/*!
+ *  @def	LISTMP_E_MEMORY
+ *  @brief  Memory allocation failed.
+ */
+#define LISTMP_E_MEMORY	LISTMP_MAKE_FAILURE(2)
+
+/*!
+ *  @def	LISTMP_E_BUSY
+ *  @brief  The name is already registered or not.
+ */
+#define LISTMP_E_BUSY		LISTMP_MAKE_FAILURE(3)
+
+/*!
+ *  @def	LISTMP_E_FAIL
+ *  @brief  Generic failure.
+ */
+#define LISTMP_E_FAIL		LISTMP_MAKE_FAILURE(4)
+
+/*!
+ *  @def	LISTMP_E_NOTFOUND
+ *  @brief  Name not found in the nameserver.
+ */
+#define LISTMP_E_NOTFOUND	LISTMP_MAKE_FAILURE(5)
+
+/*!
+ *  @def	LISTMP_E_INVALIDSTATE
+ *  @brief  Module is not initialized.
+ */
+#define LISTMP_E_INVALIDSTATE	LISTMP_MAKE_FAILURE(6)
+
+/*!
+ *  @def	LISTMP_E_OSFAILURE
+ *  @brief  Failure in OS call.
+ */
+#define LISTMP_E_OSFAILURE	LISTMP_MAKE_FAILURE(7)
+
+/*!
+ *  @def	LISTMP_SUCCESS
+ *  @brief  Operation successful.
+ */
+#define LISTMP_SUCCESS		LISTMP_MAKE_SUCCESS(0)
+
+/*!
+ *  @def	LISTMP_S_ALREADYSETUP
+ *  @brief  The LISTMP module has already been setup in this process.
+ */
+#define LISTMP_S_ALREADYSETUP	LISTMP_MAKE_SUCCESS(1)
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+/*!
+ *  @brief  Enum defining types of list for the ListMP module.
+ */
+enum listmp_type {
+	listmp_type_SHARED = 0,
+	/*!< List in shared memory */
+	listmp_type_FAST = 1
+	/*!< Hardware Queue */
+};
+
+/*!
+ *  @brief  Structure defining config parameters for the ListMP module.
+ */
+struct listmp_config {
+	u32 max_name_len;
+	/*!< Maximum length of name */
+};
+
+/*!
+ *  @brief  Structure defining list element for the ListMP.
+ */
+struct listmp_elem {
+	volatile struct listmp_elem *next;
+	volatile struct listmp_elem *prev;
+};
+
+/*!
+ *  @brief  Structure defining config parameters for the ListMP instances.
+ */
+struct listmp_params {
+	void *shared_addr;
+	/*!< shared memory address */
+	u32 shared_addr_size;
+	/*!< shared memory size */
+	char *name;
+	/*!< Name of the object	*/
+	struct mutex *lock_handle;
+	/*!< Lock used for critical region management of the list */
+	void *heap_handle;
+	/*!< Handle of the heap to be used */
+	enum listmp_type list_type ;
+	/*!< Type of list */
+};
+
+
+/* =============================================================================
+ *  Forward declarations
+ * =============================================================================
+ */
+/*!
+ *  @brief  Structure defining config parameters for the ListMPSharedMemory.
+ */
+struct listmp_object {
+	bool (*empty)(void *listmp_handle);
+	/* Function to check if list is empty */
+	void *(*get_head)(void *listmp_handle);
+	/* Function to get head element from list */
+	void *(*get_tail)(void *listmp_handle);
+	/* Function to get tail element from list */
+	int (*put_head)(void *listmp_handle, struct listmp_elem *elem);
+	/* Function to put head element into list */
+	int (*put_tail)(void *listmp_handle, struct listmp_elem *elem);
+	/* Function to put tail element into list */
+	int (*insert)(void *listmp_handle, struct listmp_elem *elem,
+					struct listmp_elem *curElem);
+	/* Function to insert element into list */
+	int (*remove)(void *listmp_handle, struct listmp_elem *elem);
+	/* Function to remove element from list */
+	void *(*next)(void *listmp_handle, struct listmp_elem *elem);
+	/* Function to traverse to next element in list */
+	void *(*prev)(void *listmp_handle, struct listmp_elem *elem);
+	/* Function to traverse to prev element in list */
+	void *obj;
+	/*!< Handle to ListMP */
+	enum listmp_type list_type;
+	/* Type of list */
+};
+
+/* TBD: To be replaced by Function */
+#define listmp_shared_memreq	listmp_sharedmemory_shared_memreq
+#define listmp_params_init	listmp_sharedmemory_params_init
+
+/* =============================================================================
+ *  Functions to create instance of a list
+ * =============================================================================
+ */
+/* Function to create an instance of ListMP */
+void *listmp_create(struct listmp_params *params);
+
+/* Function to delete an instance of ListMP */
+int listmp_delete(void **listmp_handle_ptr);
+
+/* =============================================================================
+ *  Functions to open/close handle to list instance
+ * =============================================================================
+ */
+/* Function to open a previously created instance */
+int listmp_open(void **listmp_handle_ptr, struct listmp_params *params);
+
+/* Function to close a previously opened instance */
+int listmp_close(void *listmp_handle);
+
+/* =============================================================================
+ *  Function pointer types for list operations
+ * =============================================================================
+ */
+/* Function to check if list is empty */
+bool listmp_empty(void *listmp_handle);
+
+/* Function to get head element from list */
+void *listmp_get_head(void *listmp_handle);
+
+/* Function to get tail element from list */
+void *listmp_get_tail(void *listmp_handle);
+
+/* Function to put head element into list */
+int listmp_put_head(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to put tail element into list */
+int listmp_put_tail(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to insert element into list */
+int listmp_insert(void *listmp_handle, struct listmp_elem *elem,
+			struct listmp_elem *curElem);
+
+/* Function to traverse to remove element from list */
+int listmp_remove(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to traverse to next element in list */
+void *listmp_next(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to traverse to prev element in list */
+void *listmp_prev(void *listmp_handle, struct listmp_elem *elem);
+
+#endif /* _LISTMP_H_ */

arch/arm/plat-omap/include/syslink/messageq_transportshm_ioctl.h

+/*
+ *  messageq_transportshm_ioctl.h
+ *
+ *  Definitions of messageq_transportshm driver types and structures.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _MESSAGEQ_TRANSPORTSHM_IOCTL_H_
+#define _MESSAGEQ_TRANSPORTSHM_IOCTL_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Syslink headers */
+#include <ipc_ioctl.h>
+#include <messageq_transportshm.h>
+#include <sharedregion.h>
+
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+/* Base command ID for messageq_transportshm */
+#define MESSAGEQ_TRANSPORTSHM_IOC_MAGIC		IPC_IOC_MAGIC
+enum messageq_transportshm_drv_cmd {
+	MESSAGEQ_TRANSPORTSHM_GETCONFIG = MESSAGEQ_TRANSPORTSHM_BASE_CMD,
+	MESSAGEQ_TRANSPORTSHM_SETUP,
+	MESSAGEQ_TRANSPORTSHM_DESTROY,
+	MESSAGEQ_TRANSPORTSHM_PARAMS_INIT,
+	MESSAGEQ_TRANSPORTSHM_CREATE,
+	MESSAGEQ_TRANSPORTSHM_DELETE,
+	MESSAGEQ_TRANSPORTSHM_PUT,
+	MESSAGEQ_TRANSPORTSHM_SHAREDMEMREQ,
+	MESSAGEQ_TRANSPORTSHM_GETSTATUS
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL command IDs for messageq_transportshm
+ *  ----------------------------------------------------------------------------
+ */
+/* Base command ID for messageq_transportshm */
+#define MESSAGEQ_TRANSPORTSHM_BASE_CMD		0x0
+
+/* Command for messageq_transportshm_get_config */
+#define CMD_MESSAGEQ_TRANSPORTSHM_GETCONFIG \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, \
+	MESSAGEQ_TRANSPORTSHM_GETCONFIG, struct messageq_transportshm_cmd_args)
+
+/* Command for messageq_transportshm_setup */
+#define CMD_MESSAGEQ_TRANSPORTSHM_SETUP \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_SETUP, \
+	struct messageq_transportshm_cmd_args)
+
+/* Command for messageq_transportshm_setup */
+#define CMD_MESSAGEQ_TRANSPORTSHM_DESTROY \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_DESTROY, \
+	struct messageq_transportshm_cmd_args)
+
+/* Command for messageq_transportshm_destroy */
+#define CMD_MESSAGEQ_TRANSPORTSHM_PARAMS_INIT \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, \
+	MESSAGEQ_TRANSPORTSHM_PARAMS_INIT, \
+	struct messageq_transportshm_cmd_args)
+
+/* Command for messageq_transportshm_create */
+#define CMD_MESSAGEQ_TRANSPORTSHM_CREATE \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_CREATE, \
+	struct messageq_transportshm_cmd_args)
+
+/* Command for messageq_transportshm_delete */
+#define CMD_MESSAGEQ_TRANSPORTSHM_DELETE \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_DELETE, \
+	struct messageq_transportshm_cmd_args)
+
+/* Command for messageq_transportshm_put */
+#define CMD_MESSAGEQ_TRANSPORTSHM_PUT \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_PUT, \
+	struct messageq_transportshm_cmd_args)
+
+/* Command for messageq_transportshm_shared_memreq */
+#define CMD_MESSAGEQ_TRANSPORTSHM_SHAREDMEMREQ \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, \
+	MESSAGEQ_TRANSPORTSHM_SHAREDMEMREQ, \
+	struct messageq_transportshm_cmd_args)
+
+/* Command for messageq_transportshm_get_status */
+#define CMD_MESSAGEQ_TRANSPORTSHM_GETSTATUS \
+	_IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, \
+	MESSAGEQ_TRANSPORTSHM_GETSTATUS, struct messageq_transportshm_cmd_args)
+
+/* Command arguments for messageq_transportshm */
+struct messageq_transportshm_cmd_args {
+	union {
+		struct {
+			struct messageq_transportshm_config *config;
+		} get_config;
+
+		struct {
+			struct messageq_transportshm_config *config;
+		} setup;
+
+		struct {
+			void *messageq_transportshm_handle;
+			struct messageq_transportshm_params *params;
+		} params_init;
+
+		struct {
+			void *messageq_transportshm_handle;
+			u16 proc_id;
+			struct messageq_transportshm_params *params;
+		} create;
+
+		struct {
+			void *messageq_transportshm_handle;
+		} delete_transport;
+
+		struct {
+			void *messageq_transportshm_handle;
+			u32 *msg_srptr;
+		} put;
+
+		struct {
+			void *messageq_transportshm_handle;
+			enum messageq_transportshm_status status;
+		} get_status;
+
+		struct {
+			struct messageq_transportshm_params *params;
+			u32 bytes;
+		} shared_memreq;
+	} args;
+
+	int api_status;
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL functions for messageq_transportshm module
+ *  ----------------------------------------------------------------------------
+ */
+/*
+ *  ioctl interface function for messageq_transportshm
+ */
+int messageq_transportshm_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args);
+
+#endif /* _MESSAGEQ_TRANSPORTSHM_IOCTL_H_ */

arch/arm/plat-omap/include/syslink/notifydefs.h

+/*
+ * notifydefs.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#if !defined NOTIFYDEFS_H
+#define NOTIFYDEFS_H
+typedef void (*fn_notify_cbck) (unsigned long int procId,
+                                u32  eventNo,
+                                void *arg,
+                                u32  payload) ;
+
+#endif  /* !defined (NOTIFYDEFS_H) */

drivers/Makefile

@@ -109,4 +109,10 @@ obj-$(CONFIG_VIRTIO)		+= virtio/
 obj-$(CONFIG_VLYNQ)		+= vlynq/
 obj-$(CONFIG_STAGING)		+= staging/
 obj-y				+= platform/
-obj-y				+= ieee802154/
+obj-$(CONFIG_MPU_SYSLINK_IPC)   += dsp/syslink/multicore_ipc/
+obj-$(CONFIG_MPU_BRIDGE_NOTIFY) += dsp/syslink/omap_notify/
+obj-$(CONFIG_NOTIFY_DISPATCHER) += dsp/syslink/notify_dispatcher/
+obj-$(CONFIG_NOTIFY_TESLA)      += dsp/syslink/notify_tesladriver/
+obj-$(CONFIG_NOTIFY_DUCATI)     += dsp/syslink/notify_ducatidriver/
+obj-$(CONFIG_SYSLINK_PROC)      += dsp/syslink/procmgr/
+obj-$(CONFIG_SYSLINK_PROC4430)  += dsp/syslink/procmgr/proc4430/