add UART mapping to ducati

This patch adds mapping of UART peripherals to DUCATI
virtual address
Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>

arch/arm/plat-omap/include/syslink/ducatienabler.h

@@ -56,6 +56,15 @@
 #define L4_PERIPHERAL_GPTIMER11			0x48088000
 #define DUCATI_PERIPHERAL_GPTIMER11		0xA8088000
 
+#define L4_PERIPHERAL_UART1			0x4806A000
+#define DUCATI_PERIPHERAL_UART1			0xA806A000
+#define L4_PERIPHERAL_UART2			0x4806C000
+#define DUCATI_PERIPHERAL_UART2			0xA806C000
+#define L4_PERIPHERAL_UART3			0x48020000
+#define DUCATI_PERIPHERAL_UART3			0xA8020000
+#define L4_PERIPHERAL_UART4			0x4806E000
+#define DUCATI_PERIPHERAL_UART4			0xA806E000
+
 
 #define L3_TILER_VIEW0_ADDR			0x60000000
 #define DUCATIVA_TILER_VIEW0_ADDR		0x60000000
@@ -151,6 +160,12 @@ static const struct mmu_entry l4_map[] = {
 	{L4_PERIPHERAL_GPTIMER9, DUCATI_PERIPHERAL_GPTIMER9, HW_PAGE_SIZE_4KB},
 	{L4_PERIPHERAL_GPTIMER11, DUCATI_PERIPHERAL_GPTIMER11,
 							HW_PAGE_SIZE_4KB},
+	/* UARTs 4KB each */
+	{L4_PERIPHERAL_UART1, DUCATI_PERIPHERAL_UART1, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_UART2, DUCATI_PERIPHERAL_UART2, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_UART3, DUCATI_PERIPHERAL_UART3, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_UART4, DUCATI_PERIPHERAL_UART4,
+							HW_PAGE_SIZE_4KB},
 };
 
 static const struct  memory_entry l3_memory_regions[] = {