ARM: OMAP: Modifiy common clock.h for omap2, add omap1 specific clock.h

Modifiy common clock.h for omap2, add omap1 specific clock.h

arch/arm/plat-omap/clock.c

@@ -30,7 +30,7 @@ static struct clk_functions *arch_clock;
  * Standard clock functions defined in asm/hardware/clock.h
  *-------------------------------------------------------------------------*/
 
-struct clk *clk_get(struct device *dev, const char *id)
+struct clk * clk_get(struct device *dev, const char *id)
 {
 	struct clk *p, *clk = ERR_PTR(-ENOENT);
 
@@ -155,6 +155,8 @@ EXPORT_SYMBOL(clk_get_parent);
 /*-------------------------------------------------------------------------
  * OMAP specific clock functions shared between omap1 and omap2
  *-------------------------------------------------------------------------*/
+
+/* Used for clocks that always have same value as the parent clock */
 void followparent_recalc(struct clk *  clk)
 {
 	clk->rate = clk->parent->rate;

include/asm-arm/arch-omap/clock.h

@@ -21,11 +21,12 @@ struct clk {
 	const char		*name;
 	struct clk		*parent;
 	unsigned long		rate;
-	__s8			usecount;
-	__u16			flags;
+	__u32			flags;
 	__u32			enable_reg;
 	__u8			enable_bit;
 	__u8			rate_offset;
+	__u8			src_offset;
+	__s8			usecount;
 	void			(*recalc)(struct clk *);
 	int			(*set_rate)(struct clk *, unsigned long);
 	long			(*round_rate)(struct clk *, unsigned long);
@@ -53,85 +54,32 @@ extern void clk_unregister(struct clk *clk);
 extern void propagate_rate(struct clk *clk);
 extern void followparent_recalc(struct clk *  clk);
 
-/*-------------------------------------------------------------------------
- * Defines for omap1 clocks
- *-------------------------------------------------------------------------*/
-
 /* Clock flags */
-#define RATE_CKCTL		1
-#define RATE_FIXED		2
-#define RATE_PROPAGATES		4
-#define VIRTUAL_CLOCK		8
-#define ALWAYS_ENABLED		16
-#define ENABLE_REG_32BIT	32
-#define CLOCK_IN_OMAP16XX	64
-#define CLOCK_IN_OMAP1510	128
-#define CLOCK_IN_OMAP730	256
-#define VIRTUAL_IO_ADDRESS	512
-#define CLOCK_IDLE_CONTROL	1024
-#define CLOCK_NO_IDLE_PARENT	2048
-
-/* ARM_CKCTL bit shifts */
-#define CKCTL_PERDIV_OFFSET	0
-#define CKCTL_LCDDIV_OFFSET	2
-#define CKCTL_ARMDIV_OFFSET	4
-#define CKCTL_DSPDIV_OFFSET	6
-#define CKCTL_TCDIV_OFFSET	8
-#define CKCTL_DSPMMUDIV_OFFSET	10
-/*#define ARM_TIMXO		12*/
-#define EN_DSPCK		13
-/*#define ARM_INTHCK_SEL	14*/ /* Divide-by-2 for mpu inth_ck */
-/* DSP_CKCTL bit shifts */
-#define CKCTL_DSPPERDIV_OFFSET	0
-
-/* ARM_IDLECT1 bit shifts */
-/*#define IDLWDT_ARM	0*/
-/*#define IDLXORP_ARM	1*/
-/*#define IDLPER_ARM	2*/
-/*#define IDLLCD_ARM	3*/
-/*#define IDLLB_ARM	4*/
-/*#define IDLHSAB_ARM	5*/
-/*#define IDLIF_ARM	6*/
-/*#define IDLDPLL_ARM	7*/
-/*#define IDLAPI_ARM	8*/
-/*#define IDLTIM_ARM	9*/
-/*#define SETARM_IDLE	11*/
-
-/* ARM_IDLECT2 bit shifts */
-#define EN_WDTCK	0
-#define EN_XORPCK	1
-#define EN_PERCK	2
-#define EN_LCDCK	3
-#define EN_LBCK		4 /* Not on 1610/1710 */
-/*#define EN_HSABCK	5*/
-#define EN_APICK	6
-#define EN_TIMCK	7
-#define DMACK_REQ	8
-#define EN_GPIOCK	9 /* Not on 1610/1710 */
-/*#define EN_LBFREECK	10*/
-#define EN_CKOUT_ARM	11
-
-/* ARM_IDLECT3 bit shifts */
-#define EN_OCPI_CK	0
-#define EN_TC1_CK	2
-#define EN_TC2_CK	4
-
-/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
-#define EN_DSPTIMCK	5
-
-/* Various register defines for clock controls scattered around OMAP chip */
-#define USB_MCLK_EN_BIT		4	/* In ULPD_CLKC_CTRL */
-#define USB_HOST_HHC_UHOST_EN	9	/* In MOD_CONF_CTRL_0 */
-#define SWD_ULPD_PLL_CLK_REQ	1	/* In SWD_CLK_DIV_CTRL_SEL */
-#define COM_ULPD_PLL_CLK_REQ	1	/* In COM_CLK_DIV_CTRL_SEL */
-#define SWD_CLK_DIV_CTRL_SEL	0xfffe0874
-#define COM_CLK_DIV_CTRL_SEL	0xfffe0878
-#define SOFT_REQ_REG		0xfffe0834
-#define SOFT_REQ_REG2		0xfffe0880
-
-/*-------------------------------------------------------------------------
- * Defines for omap2 clocks
- *-------------------------------------------------------------------------*/
-
+#define RATE_CKCTL		(1 << 0)	/* Main fixed ratio clocks */
+#define RATE_FIXED		(1 << 1)	/* Fixed clock rate */
+#define RATE_PROPAGATES		(1 << 2)	/* Program children too */
+#define VIRTUAL_CLOCK		(1 << 3)	/* Composite clock from table */
+#define ALWAYS_ENABLED		(1 << 4)	/* Clock cannot be disabled */
+#define ENABLE_REG_32BIT	(1 << 5)	/* Use 32-bit access */
+#define VIRTUAL_IO_ADDRESS	(1 << 6)	/* Clock in virtual address */
+#define CLOCK_IDLE_CONTROL	(1 << 7)
+#define CLOCK_NO_IDLE_PARENT	(1 << 8)
+#define DELAYED_APP		(1 << 9)	/* Delay application of clock */
+#define CONFIG_PARTICIPANT	(1 << 10)	/* Fundamental clock */
+#define CM_MPU_SEL1		(1 << 11)	/* Domain divider/source */
+#define CM_DSP_SEL1		(1 << 12)
+#define CM_GFX_SEL1		(1 << 13)
+#define CM_MODEM_SEL1		(1 << 14)
+#define CM_CORE_SEL1		(1 << 15)	/* Sets divider for many */
+#define CM_CORE_SEL2		(1 << 16)	/* sets parent for GPT */
+#define CM_WKUP_SEL1		(1 << 17)
+#define CM_PLL_SEL1		(1 << 18)
+#define CM_PLL_SEL2		(1 << 19)
+#define CM_SYSCLKOUT_SEL1	(1 << 20)
+#define CLOCK_IN_OMAP730	(1 << 21)
+#define CLOCK_IN_OMAP1510	(1 << 22)
+#define CLOCK_IN_OMAP16XX	(1 << 23)
+#define CLOCK_IN_OMAP242X	(1 << 24)
+#define CLOCK_IN_OMAP243X	(1 << 25)
 
 #endif