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Commit 8d9c5f34 authored by Eilon Greenstein's avatar Eilon Greenstein Committed by David S. Miller
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bnx2x: New FW 

This is the FW blob and the relevant definitions without any logic. It
also contains the minimal mandatory code changes to work with this FW
but it does not contain enabling of the new features that this FW
provides.

This FW is needed for:
- More efficient multi-queue
- per queue statistics
- Big-endian issue with MSI
- Improved pause response
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 33af6bcc
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Showing with 14374 additions and 12635 deletions
drivers/net/bnx2x.h
View file @ 8d9c5f34
......@@ -1125,7 +1125,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE)
#define MULTI_MASK 0x7f
......
drivers/net/bnx2x_fw_defs.h
View file @ 8d9c5f34
......@@ -50,8 +50,10 @@
#define TSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
(IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \
: (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
(IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \
: (0x9c0 + (port * 0x130) + (client_id * 0x10)))
#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
(IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)
#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
......@@ -81,43 +83,43 @@
(function * 0x38)))
#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38)))
#define TSTORM_RX_PRODS_OFFSET(port, client_id) \
(IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \
: (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
#define TSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
(function * 0x8)))
#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20)
#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)
#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
#define USTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET ? 0x8000 : 0x1000)
(IS_E1H_OFFSET ? 0x8960 : 0x1000)
#define USTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
(IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
(0x5450 + (port * 0x1c8) + (clientId * 0x18)))
(IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \
(0x5330 + (port * 0x260) + (clientId * 0x20)))
#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \
0x28) + (index * 0x4)))
(IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \
((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
0x40) + (index * 0x4)))
#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1900 + (function * 0x28)))
(IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
(IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1908 + (function * 0x28)))
(IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
#define USTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
#define USTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
(IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
(IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
(0x5448 + (port * 0x1c8) + (clientId * 0x18)))
(IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \
(0x5328 + (port * 0x260) + (clientId * 0x20)))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \
(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
(function * 0x8)))
#define USTORM_RX_PRODS_OFFSET(port, client_id) \
(IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \
: (0x5318 + (port * 0x260) + (client_id * 0x20)))
#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
......@@ -137,7 +139,7 @@
#define XSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
(IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
(IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))
#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
......@@ -149,23 +151,23 @@
(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
#define XSTORM_E1HOV_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff)
(IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)
#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
(function * 0x8)))
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \
(function * 0x70)))
(IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \
(function * 0x90)))
#define XSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff)
(IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)
#define XSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
(IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \
(function * 0x70)))
(IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \
(function * 0x90)))
#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
(IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
(function * 0x10)))
......@@ -278,9 +280,6 @@
#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define ISCSI_STATE \
(ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
/* microcode fixed page page size 4K (chains and ring segments) */
#define MC_PAGE_SIZE (4096)
......@@ -289,7 +288,7 @@
/* Host coalescing constants */
/* index numbers */
#define HC_USTORM_DEF_SB_NUM_INDICES 4
#define HC_USTORM_DEF_SB_NUM_INDICES 8
#define HC_CSTORM_DEF_SB_NUM_INDICES 8
#define HC_XSTORM_DEF_SB_NUM_INDICES 4
#define HC_TSTORM_DEF_SB_NUM_INDICES 4
......@@ -386,9 +385,12 @@
#define FW_LOG_LIST_SIZE (50)
#define NUM_OF_PROTOCOLS 4
#define MAX_COS_NUMBER 16
#define NUM_OF_SAFC_BITS 16
#define MAX_COS_NUMBER 4
#define MAX_T_STAT_COUNTER_ID 18
#define MAX_X_STAT_COUNTER_ID 18
#define MAX_U_STAT_COUNTER_ID 18
#define UNKNOWN_ADDRESS 0
#define UNICAST_ADDRESS 1
......
drivers/net/bnx2x_hsi.h
View file @ 8d9c5f34
......@@ -1212,8 +1212,9 @@ struct host_func_stats {
#define BCM_5710_FW_MAJOR_VERSION 4
#define BCM_5710_FW_MINOR_VERSION 5
#define BCM_5710_FW_REVISION_VERSION 1
#define BCM_5710_FW_MINOR_VERSION 8
#define BCM_5710_FW_REVISION_VERSION 53
#define BCM_5710_FW_ENGINEERING_VERSION 0
#define BCM_5710_FW_COMPILE_FLAGS 1
......@@ -1465,9 +1466,11 @@ struct ustorm_eth_st_context_config {
#endif
#if defined(__BIG_ENDIAN)
u16 bd_buff_size;
u16 mc_alignment_size;
u8 statistics_counter_id;
u8 mc_alignment_log_size;
#elif defined(__LITTLE_ENDIAN)
u16 mc_alignment_size;
u8 mc_alignment_log_size;
u8 statistics_counter_id;
u16 bd_buff_size;
#endif
#if defined(__BIG_ENDIAN)
......@@ -1479,13 +1482,7 @@ struct ustorm_eth_st_context_config {
u8 __local_bd_prod;
u8 __local_sge_prod;
#endif
#if defined(__BIG_ENDIAN)
u16 __bd_cons;
u16 __sge_cons;
#elif defined(__LITTLE_ENDIAN)
u16 __sge_cons;
u16 __bd_cons;
#endif
u32 reserved;
u32 bd_page_base_lo;
u32 bd_page_base_hi;
u32 sge_page_base_lo;
......@@ -2162,9 +2159,9 @@ struct host_status_block {
* The data for RSS setup ramrod
*/
struct eth_client_setup_ramrod_data {
u32 client_id_5b;
u8 is_rdma_1b;
u8 reserved0;
u32 client_id;
u8 is_rdma;
u8 is_fcoe;
u16 reserved1;
};
......@@ -2225,7 +2222,7 @@ struct eth_fast_path_rx_cqe {
* The data for RSS setup ramrod
*/
struct eth_halt_ramrod_data {
u32 client_id_5b;
u32 client_id;
u32 reserved0;
};
......@@ -2236,11 +2233,11 @@ struct eth_halt_ramrod_data {
struct eth_query_ramrod_data {
#if defined(__BIG_ENDIAN)
u8 reserved0;
u8 collect_port_1b;
u8 collect_port;
u16 drv_counter;
#elif defined(__LITTLE_ENDIAN)
u16 drv_counter;
u8 collect_port_1b;
u8 collect_port;
u8 reserved0;
#endif
u32 ctr_id_vector;
......@@ -2282,7 +2279,7 @@ struct common_ramrod_eth_rx_cqe {
#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
u8 conn_type_3b;
u8 conn_type;
u16 reserved1;
u32 conn_and_cmd_data;
#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
......@@ -2377,14 +2374,16 @@ struct tstorm_eth_function_common_config {
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
#elif defined(__LITTLE_ENDIAN)
u16 config_flags;
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
......@@ -2395,14 +2394,16 @@ struct tstorm_eth_function_common_config {
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
u8 rss_result_mask;
u8 leading_client_id;
#endif
......@@ -2422,7 +2423,7 @@ struct eth_update_ramrod_data {
* MAC filtering configuration command header
*/
struct mac_configuration_hdr {
u8 length_6b;
u8 length;
u8 offset;
u16 client_id;
u32 reserved1;
......@@ -2544,24 +2545,28 @@ struct tstorm_eth_client_config {
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
u16 config_flags;
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
#elif defined(__LITTLE_ENDIAN)
u16 config_flags;
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
u16 drop_flags;
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
......@@ -2593,10 +2598,27 @@ struct tstorm_eth_mac_filter_config {
};
/*
* common flag to indicate existance of TPA.
*/
struct tstorm_eth_tpa_exist {
#if defined(__BIG_ENDIAN)
u16 reserved1;
u8 reserved0;
u8 tpa_exist;
#elif defined(__LITTLE_ENDIAN)
u8 tpa_exist;
u8 reserved0;
u16 reserved1;
#endif
u32 reserved2;
};
/*
* Three RX producers for ETH
*/
struct tstorm_eth_rx_producers {
struct ustorm_eth_rx_producers {
#if defined(__BIG_ENDIAN)
u16 bd_prod;
u16 cqe_prod;
......@@ -2614,23 +2636,6 @@ struct tstorm_eth_rx_producers {
};
/*
* common flag to indicate existence of TPA.
*/
struct tstorm_eth_tpa_exist {
#if defined(__BIG_ENDIAN)
u16 reserved1;
u8 reserved0;
u8 tpa_exist;
#elif defined(__LITTLE_ENDIAN)
u8 tpa_exist;
u8 reserved0;
u16 reserved1;
#endif
u32 reserved2;
};
/*
* per-port SAFC demo variables
*/
......@@ -2674,15 +2679,15 @@ struct fairness_vars_per_port {
*/
struct safc_struct_per_port {
#if defined(__BIG_ENDIAN)
u16 __reserved0;
u8 cur_cos_types;
u16 __reserved1;
u8 __reserved0;
u8 safc_timeout_usec;
#elif defined(__LITTLE_ENDIAN)
u8 safc_timeout_usec;
u8 cur_cos_types;
u16 __reserved0;
u8 __reserved0;
u16 __reserved1;
#endif
u8 cos_to_protocol[MAX_COS_NUMBER];
u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
};
......@@ -2788,13 +2793,15 @@ struct fairness_vars_per_vn {
*/
struct fw_version {
#if defined(__BIG_ENDIAN)
u16 patch;
u8 primary;
u8 client;
u8 engineering;
u8 revision;
u8 minor;
u8 major;
#elif defined(__LITTLE_ENDIAN)
u8 client;
u8 primary;
u16 patch;
u8 major;
u8 minor;
u8 revision;
u8 engineering;
#endif
u32 flags;
#define FW_VERSION_OPTIMIZED (0x1<<0)
......@@ -2812,9 +2819,10 @@ struct fw_version {
* FW version stored in first line of pram
*/
struct pram_fw_version {
u8 client;
u8 primary;
u16 patch;
u8 major;
u8 minor;
u8 revision;
u8 engineering;
u8 flags;
#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
......
drivers/net/bnx2x_init_values.h
View file @ 8d9c5f34
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/net/bnx2x_main.c
View file @ 8d9c5f34
......@@ -1377,7 +1377,7 @@ static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
u16 bd_prod, u16 rx_comp_prod,
u16 rx_sge_prod)
{
struct tstorm_eth_rx_producers rx_prods = {0};
struct ustorm_eth_rx_producers rx_prods = {0};
int i;
/* Update producers */
......@@ -1395,9 +1395,9 @@ static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
*/
wmb();
for (i = 0; i < sizeof(struct tstorm_eth_rx_producers)/4; i++)
REG_WR(bp, BAR_TSTRORM_INTMEM +
TSTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
REG_WR(bp, BAR_USTRORM_INTMEM +
USTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
((u32 *)&rx_prods)[i]);
mmiowb(); /* keep prod updates ordered */
......@@ -2915,7 +2915,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
return IRQ_HANDLED;
}
bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
#ifdef BNX2X_STOP_ON_ERROR
if (unlikely(bp->panic))
......@@ -3043,7 +3043,7 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp)
int rc;
ramrod_data.drv_counter = bp->stats_counter++;
ramrod_data.collect_port_1b = bp->port.pmf ? 1 : 0;
ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));
rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
......@@ -4240,10 +4240,6 @@ static void bnx2x_update_coalesce(struct bnx2x *bp)
USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
U_SB_ETH_RX_CQ_INDEX),
bp->rx_ticks ? 0 : 1);
REG_WR16(bp, BAR_USTRORM_INTMEM +
USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
U_SB_ETH_RX_BD_INDEX),
bp->rx_ticks ? 0 : 1);
/* HC_INDEX_C_ETH_TX_CQ_CONS */
REG_WR8(bp, BAR_CSTRORM_INTMEM +
......@@ -4489,25 +4485,14 @@ static void bnx2x_init_context(struct bnx2x *bp)
struct bnx2x_fastpath *fp = &bp->fp[i];
u8 sb_id = FP_SB_ID(fp);
context->xstorm_st_context.tx_bd_page_base_hi =
U64_HI(fp->tx_desc_mapping);
context->xstorm_st_context.tx_bd_page_base_lo =
U64_LO(fp->tx_desc_mapping);
context->xstorm_st_context.db_data_addr_hi =
U64_HI(fp->tx_prods_mapping);
context->xstorm_st_context.db_data_addr_lo =
U64_LO(fp->tx_prods_mapping);
context->xstorm_st_context.statistics_data = (BP_CL_ID(bp) |
XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
context->ustorm_st_context.common.sb_index_numbers =
BNX2X_RX_SB_INDEX_NUM;
context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
context->ustorm_st_context.common.status_block_id = sb_id;
context->ustorm_st_context.common.flags =
USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
context->ustorm_st_context.common.mc_alignment_size =
BCM_RX_ETH_PAYLOAD_ALIGN;
context->ustorm_st_context.common.mc_alignment_log_size =
6 /*BCM_RX_ETH_PAYLOAD_ALIGN*/;
context->ustorm_st_context.common.bd_buff_size =
bp->rx_buf_size;
context->ustorm_st_context.common.bd_page_base_hi =
......@@ -4519,13 +4504,29 @@ static void bnx2x_init_context(struct bnx2x *bp)
(USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
context->ustorm_st_context.common.sge_buff_size =
(u16)(BCM_PAGE_SIZE*PAGES_PER_SGE);
(u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
(u32)0xffff);
context->ustorm_st_context.common.sge_page_base_hi =
U64_HI(fp->rx_sge_mapping);
context->ustorm_st_context.common.sge_page_base_lo =
U64_LO(fp->rx_sge_mapping);
}
context->ustorm_ag_context.cdu_usage =
CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
CDU_REGION_NUMBER_UCM_AG,
ETH_CONNECTION_TYPE);
context->xstorm_st_context.tx_bd_page_base_hi =
U64_HI(fp->tx_desc_mapping);
context->xstorm_st_context.tx_bd_page_base_lo =
U64_LO(fp->tx_desc_mapping);
context->xstorm_st_context.db_data_addr_hi =
U64_HI(fp->tx_prods_mapping);
context->xstorm_st_context.db_data_addr_lo =
U64_LO(fp->tx_prods_mapping);
context->xstorm_st_context.statistics_data = (fp->cl_id |
XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
context->cstorm_st_context.sb_index_number =
C_SB_ETH_TX_CQ_INDEX;
context->cstorm_st_context.status_block_id = sb_id;
......@@ -4534,10 +4535,6 @@ static void bnx2x_init_context(struct bnx2x *bp)
CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
CDU_REGION_NUMBER_XCM_AG,
ETH_CONNECTION_TYPE);
context->ustorm_ag_context.cdu_usage =
CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
CDU_REGION_NUMBER_UCM_AG,
ETH_CONNECTION_TYPE);
}
}
......@@ -4569,7 +4566,7 @@ static void bnx2x_set_client_config(struct bnx2x *bp)
#ifdef BCM_VLAN
if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
tstorm_client.config_flags |=
TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
}
#endif
......@@ -4690,6 +4687,9 @@ static void bnx2x_init_internal_func(struct bnx2x *bp)
tstorm_config.config_flags = MULTI_FLAGS;
tstorm_config.rss_result_mask = MULTI_MASK;
}
if (IS_E1HMF(bp))
tstorm_config.config_flags |=
TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
tstorm_config.leading_client_id = BP_L_ID(bp);
......@@ -5338,7 +5338,6 @@ static int bnx2x_init_common(struct bnx2x *bp)
REG_WR(bp, i, 0xc0cac01a);
/* TODO: replace with something meaningful */
}
if (CHIP_IS_E1H(bp))
bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
REG_WR(bp, SRC_REG_SOFT_RST, 0);
......@@ -5358,6 +5357,11 @@ static int bnx2x_init_common(struct bnx2x *bp)
bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
/* enable context validation interrupt from CFC */
REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
/* set the thresholds to prevent CFC/CDU race */
REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
......@@ -5485,6 +5489,8 @@ static int bnx2x_init_port(struct bnx2x *bp)
REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
#endif
/* Port CMs come here */
bnx2x_init_block(bp, (port ? XCM_PORT1_START : XCM_PORT0_START),
(port ? XCM_PORT1_END : XCM_PORT0_END));
/* Port QM comes here */
#ifdef BCM_ISCSI
......@@ -5675,9 +5681,6 @@ static int bnx2x_init_func(struct bnx2x *bp)
}
bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);
if (CHIP_IS_E1H(bp))
REG_WR(bp, HC_REG_FUNC_NUM_P0 + port*4, func);
/* Reset PCIE errors for debug */
REG_WR(bp, 0x2114, 0xffffffff);
REG_WR(bp, 0x2120, 0xffffffff);
......@@ -6171,7 +6174,7 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
* unicasts 0-31:port0 32-63:port1
* multicast 64-127:port0 128-191:port1
*/
config->hdr.length_6b = 2;
config->hdr.length = 2;
config->hdr.offset = port ? 32 : 0;
config->hdr.client_id = BP_CL_ID(bp);
config->hdr.reserved1 = 0;
......@@ -6229,7 +6232,7 @@ static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
* unicasts: by func number
* multicast: 20+FUNC*20, 20 each
*/
config->hdr.length_6b = 1;
config->hdr.length = 1;
config->hdr.offset = BP_FUNC(bp);
config->hdr.client_id = BP_CL_ID(bp);
config->hdr.reserved1 = 0;
......@@ -6764,10 +6767,10 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
bnx2x_set_mac_addr_e1(bp, 0);
for (i = 0; i < config->hdr.length_6b; i++)
for (i = 0; i < config->hdr.length; i++)
CAM_INVALIDATE(config->config_table[i]);
config->hdr.length_6b = i;
config->hdr.length = i;
if (CHIP_REV_IS_SLOW(bp))
config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
else
......@@ -8959,7 +8962,7 @@ static int bnx2x_test_intr(struct bnx2x *bp)
if (!netif_running(bp->dev))
return -ENODEV;
config->hdr.length_6b = 0;
config->hdr.length = 0;
if (CHIP_IS_E1(bp))
config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
else
......@@ -9921,7 +9924,7 @@ static void bnx2x_set_rx_mode(struct net_device *dev)
config->config_table[i].
cam_entry.lsb_mac_addr);
}
old = config->hdr.length_6b;
old = config->hdr.length;
if (old > i) {
for (; i < old; i++) {
if (CAM_IS_INVALID(config->
......@@ -9940,9 +9943,9 @@ static void bnx2x_set_rx_mode(struct net_device *dev)
else
offset = BNX2X_MAX_MULTICAST*(1 + port);
config->hdr.length_6b = i;
config->hdr.length = i;
config->hdr.offset = offset;
config->hdr.client_id = BP_CL_ID(bp);
config->hdr.client_id = bp->fp->cl_id;
config->hdr.reserved1 = 0;
bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
......@@ -10487,7 +10490,7 @@ static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
struct mac_configuration_cmd *config =
bnx2x_sp(bp, mcast_config);
for (i = 0; i < config->hdr.length_6b; i++)
for (i = 0; i < config->hdr.length; i++)
CAM_INVALIDATE(config->config_table[i]);
}
......
drivers/net/bnx2x_reg.h
View file @ 8d9c5f34
......@@ -125,6 +125,10 @@
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_CQM_P_WEIGHT 0xd00b8
/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_CQM_S_WEIGHT 0xd00bc
/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
......@@ -132,6 +136,10 @@
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the SDM interface is detected. */
#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_CSDM_WEIGHT 0xd00b4
/* [RW 28] The CM header for QM formatting in case of an error in the QM
inputs. */
#define CCM_REG_ERR_CCM_HDR 0xd0094
......@@ -211,6 +219,11 @@
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the STORM interface is detected. */
#define CCM_REG_STORM_LENGTH_MIS 0xd016c
/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
tc. */
#define CCM_REG_STORM_WEIGHT 0xd009c
/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
......@@ -323,7 +336,11 @@
set one of these bits. the bit description can be found in CFC
specifications */
#define CFC_REG_ERROR_VECTOR 0x10403c
/* [WB 93] LCID info ram access */
#define CFC_REG_INFO_RAM 0x105000
#define CFC_REG_INFO_RAM_SIZE 1024
#define CFC_REG_INIT_REG 0x10404c
#define CFC_REG_INTERFACES 0x104058
/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
field allows changing the priorities of the weighted-round-robin arbiter
which selects which CFC load client should be served next */
......@@ -337,8 +354,6 @@
#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
/* [R 9] Number of Arriving LCIDs in Link List Block */
#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
/* [R 9] Number of Inside LCIDs in Link List Block */
#define CFC_REG_NUM_LCIDS_INSIDE 0x104008
/* [R 9] Number of Leaving LCIDs in Link List Block */
#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
/* [RW 8] The event id for aggregated interrupt 0 */
......@@ -1554,6 +1569,14 @@
command bit is written. This bit is set when the SPIO input does not
match the current value in #OLD_VALUE (reset value 0). */
#define MISC_REG_SPIO_INT 0xa500
/* [RW 32] reload value for counter 4 if reload; the value will be reload if
the counter reached zero and the reload bit
(~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
in this register. addres 0 - timer 1; address - timer 2�address 7 -
timer 8 */
#define MISC_REG_SW_TIMER_VAL 0xa5c0
/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
loaded; 0-prepare; -unprepare */
#define MISC_REG_UNPREPARED 0xa424
......@@ -1885,6 +1908,7 @@
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
load response is set and packet type is 0. Used in packet start message
to TCM. */
......@@ -1893,6 +1917,7 @@
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
/* [RW 32] The CM header for a match and packet type 1 for loopback port.
Used in packet start message to TCM. */
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
......@@ -2498,6 +2523,11 @@
considered zero so practically there are only 20 bits in this register;
queues 63-0 */
#define QM_REG_BASEADDR 0x168900
/* [RW 32] The base logical address (in bytes) of each physical queue. The
index I represents the physical queue number. The 12 lsbs are ignore and
considered zero so practically there are only 20 bits in this register;
queues 127-64 */
#define QM_REG_BASEADDR_EXT_A 0x16e100
/* [RW 16] The byte credit cost for each task. This value is for both ports */
#define QM_REG_BYTECRDCOST 0x168234
/* [RW 16] The initial byte credit value for both ports. */
......@@ -3438,6 +3468,16 @@
#define SRC_REG_KEYRSS0_0 0x40408
#define SRC_REG_KEYRSS0_7 0x40424
#define SRC_REG_KEYRSS1_9 0x40454
#define SRC_REG_KEYSEARCH_0 0x40458
#define SRC_REG_KEYSEARCH_1 0x4045c
#define SRC_REG_KEYSEARCH_2 0x40460
#define SRC_REG_KEYSEARCH_3 0x40464
#define SRC_REG_KEYSEARCH_4 0x40468
#define SRC_REG_KEYSEARCH_5 0x4046c
#define SRC_REG_KEYSEARCH_6 0x40470
#define SRC_REG_KEYSEARCH_7 0x40474
#define SRC_REG_KEYSEARCH_8 0x40478
#define SRC_REG_KEYSEARCH_9 0x4047c
#define SRC_REG_LASTFREE0 0x40530
#define SRC_REG_NUMBER_HASH_BITS0 0x40400
/* [RW 1] Reset internal state machines. */
......@@ -3481,6 +3521,10 @@
/* [RC 1] Message length mismatch (relative to last indication) at the In#9
interface. */
#define TCM_REG_CSEM_LENGTH_MIS 0x50174
/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define TCM_REG_CSEM_WEIGHT 0x500bc
/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
#define TCM_REG_ERR_EVNT_ID 0x500a0
/* [RW 28] The CM erroneous header for QM and Timers formatting. */
......@@ -3524,6 +3568,7 @@
#define TCM_REG_N_SM_CTX_LD_2 0x50058
#define TCM_REG_N_SM_CTX_LD_3 0x5005c
#define TCM_REG_N_SM_CTX_LD_4 0x50060
#define TCM_REG_N_SM_CTX_LD_5 0x50064
/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
......@@ -3563,6 +3608,10 @@
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define TCM_REG_STORM_TCM_IFEN 0x50010
/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define TCM_REG_STORM_WEIGHT 0x500ac
/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
......@@ -3598,10 +3647,22 @@
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define TCM_REG_TM_TCM_IFEN 0x5001c
/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define TCM_REG_TM_WEIGHT 0x500d0
/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
the initial credit value; read returns the current value of the credit
counter. Must be initialized to 32 at start-up. */
#define TCM_REG_TQM_INIT_CRD 0x5021c
/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define TCM_REG_TQM_P_WEIGHT 0x500c8
/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define TCM_REG_TQM_S_WEIGHT 0x500cc
/* [RW 28] The CM header value for QM request (primary). */
#define TCM_REG_TQM_TCM_HDR_P 0x50090
/* [RW 28] The CM header value for QM request (secondary). */
......@@ -3628,6 +3689,10 @@
/* [RC 1] Message length mismatch (relative to last indication) at the In#8
interface. */
#define TCM_REG_USEM_LENGTH_MIS 0x50170
/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define TCM_REG_USEM_WEIGHT 0x500b8
/* [RW 21] Indirect access to the descriptor table of the XX protection
mechanism. The fields are: [5:0] - length of the message; 15:6] - message
pointer; 20:16] - next pointer. */
......@@ -3677,6 +3742,7 @@
#define TM_REG_EN_CL1_INPUT 0x16400c
/* [RW 1] Enable client2 input. */
#define TM_REG_EN_CL2_INPUT 0x164010
#define TM_REG_EN_LINEAR0_TIMER 0x164014
/* [RW 1] Enable real time counter. */
#define TM_REG_EN_REAL_TIME_CNT 0x1640d8
/* [RW 1] Enable for Timers state machines. */
......@@ -3684,14 +3750,22 @@
/* [RW 4] Load value for expiration credit cnt. CFC max number of
outstanding load requests for timers (expiration) context loading. */
#define TM_REG_EXP_CRDCNT_VAL 0x164238
/* [RW 32] Linear0 logic address. */
#define TM_REG_LIN0_LOGIC_ADDR 0x164240
/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
/* [WB 64] Linear0 phy address. */
#define TM_REG_LIN0_PHY_ADDR 0x164270
/* [RW 1] Linear0 physical address valid. */
#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
/* [RW 24] Linear0 array scan timeout. */
#define TM_REG_LIN0_SCAN_TIME 0x16403c
/* [RW 32] Linear1 logic address. */
#define TM_REG_LIN1_LOGIC_ADDR 0x164250
/* [WB 64] Linear1 phy address. */
#define TM_REG_LIN1_PHY_ADDR 0x164280
/* [RW 1] Linear1 physical address valid. */
#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
/* [RW 6] Linear timer set_clear fifo threshold. */
#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
/* [RW 2] Load value for pci arbiter credit cnt. */
......@@ -3708,6 +3782,17 @@
#define TM_REG_TM_INT_STS 0x1640f0
/* [RW 8] The event id for aggregated interrupt 0 */
#define TSDM_REG_AGG_INT_EVENT_0 0x42038
#define TSDM_REG_AGG_INT_EVENT_1 0x4203c
#define TSDM_REG_AGG_INT_EVENT_10 0x42060
#define TSDM_REG_AGG_INT_EVENT_11 0x42064
#define TSDM_REG_AGG_INT_EVENT_12 0x42068
#define TSDM_REG_AGG_INT_EVENT_13 0x4206c
#define TSDM_REG_AGG_INT_EVENT_14 0x42070
#define TSDM_REG_AGG_INT_EVENT_15 0x42074
#define TSDM_REG_AGG_INT_EVENT_16 0x42078
#define TSDM_REG_AGG_INT_EVENT_17 0x4207c
#define TSDM_REG_AGG_INT_EVENT_18 0x42080
#define TSDM_REG_AGG_INT_EVENT_19 0x42084
#define TSDM_REG_AGG_INT_EVENT_2 0x42040
#define TSDM_REG_AGG_INT_EVENT_20 0x42088
#define TSDM_REG_AGG_INT_EVENT_21 0x4208c
......@@ -3723,6 +3808,19 @@
#define TSDM_REG_AGG_INT_EVENT_30 0x420b0
#define TSDM_REG_AGG_INT_EVENT_31 0x420b4
#define TSDM_REG_AGG_INT_EVENT_4 0x42048
/* [RW 1] The T bit for aggregated interrupt 0 */
#define TSDM_REG_AGG_INT_T_0 0x420b8
#define TSDM_REG_AGG_INT_T_1 0x420bc
#define TSDM_REG_AGG_INT_T_10 0x420e0
#define TSDM_REG_AGG_INT_T_11 0x420e4
#define TSDM_REG_AGG_INT_T_12 0x420e8
#define TSDM_REG_AGG_INT_T_13 0x420ec
#define TSDM_REG_AGG_INT_T_14 0x420f0
#define TSDM_REG_AGG_INT_T_15 0x420f4
#define TSDM_REG_AGG_INT_T_16 0x420f8
#define TSDM_REG_AGG_INT_T_17 0x420fc
#define TSDM_REG_AGG_INT_T_18 0x42100
#define TSDM_REG_AGG_INT_T_19 0x42104
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
/* [RW 16] The maximum value of the competion counter #0 */
......@@ -3967,6 +4065,10 @@
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the dorq interface is detected. */
#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define UCM_REG_DORQ_WEIGHT 0xe00c0
/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
#define UCM_REG_ERR_EVNT_ID 0xe00a4
/* [RW 28] The CM erroneous header for QM and Timers formatting. */
......@@ -4030,6 +4132,10 @@
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define UCM_REG_STORM_UCM_IFEN 0xe0010
/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define UCM_REG_STORM_WEIGHT 0xe00b0
/* [RW 4] Timers output initial credit. Max credit available - 15.Write
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 4 at start-up. */
......@@ -4040,6 +4146,10 @@
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define UCM_REG_TM_UCM_IFEN 0xe001c
/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define UCM_REG_TM_WEIGHT 0xe00d4
/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
......@@ -4092,6 +4202,10 @@
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define UCM_REG_UQM_P_WEIGHT 0xe00cc
/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define UCM_REG_UQM_S_WEIGHT 0xe00d0
/* [RW 28] The CM header value for QM request (primary). */
#define UCM_REG_UQM_UCM_HDR_P 0xe0094
/* [RW 28] The CM header value for QM request (secondary). */
......@@ -4107,6 +4221,10 @@
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the SDM interface is detected. */
#define UCM_REG_USDM_LENGTH_MIS 0xe0158
/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define UCM_REG_USDM_WEIGHT 0xe00c8
/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
......@@ -4114,6 +4232,10 @@
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the xsem interface isdetected. */
#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define UCM_REG_XSEM_WEIGHT 0xe00bc
/* [RW 20] Indirect access to the descriptor table of the XX protection
mechanism. The fields are:[5:0] - message length; 14:6] - message
pointer; 19:15] - next pointer. */
......@@ -4163,6 +4285,7 @@
#define USDM_REG_AGG_INT_EVENT_30 0xc40b0
#define USDM_REG_AGG_INT_EVENT_31 0xc40b4
#define USDM_REG_AGG_INT_EVENT_4 0xc4048
#define USDM_REG_AGG_INT_EVENT_5 0xc404c
/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
or auto-mask-mode (1) */
#define USDM_REG_AGG_INT_MODE_0 0xc41b8
......@@ -4177,6 +4300,8 @@
#define USDM_REG_AGG_INT_MODE_17 0xc41fc
#define USDM_REG_AGG_INT_MODE_18 0xc4200
#define USDM_REG_AGG_INT_MODE_19 0xc4204
#define USDM_REG_AGG_INT_MODE_4 0xc41c8
#define USDM_REG_AGG_INT_MODE_5 0xc41cc
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
/* [RW 16] The maximum value of the competion counter #0 */
......@@ -4427,6 +4552,10 @@
/* [RC 1] Set at message length mismatch (relative to last indication) at
the dorq interface. */
#define XCM_REG_DORQ_LENGTH_MIS 0x20230
/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define XCM_REG_DORQ_WEIGHT 0x200cc
/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
#define XCM_REG_ERR_EVNT_ID 0x200b0
/* [RW 28] The CM erroneous header for QM and Timers formatting. */
......@@ -4465,6 +4594,10 @@
/* [RC 1] Set at message length mismatch (relative to last indication) at
the nig0 interface. */
#define XCM_REG_NIG0_LENGTH_MIS 0x20238
/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define XCM_REG_NIG0_WEIGHT 0x200d4
/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
......@@ -4523,6 +4656,10 @@
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 4 at start-up. */
#define XCM_REG_TM_INIT_CRD 0x2041c
/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define XCM_REG_TM_WEIGHT 0x200ec
/* [RW 28] The CM header for Timers expiration command. */
#define XCM_REG_TM_XCM_HDR 0x200a8
/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
......@@ -4608,6 +4745,10 @@
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define XCM_REG_XQM_P_WEIGHT 0x200e4
/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define XCM_REG_XQM_S_WEIGHT 0x200e8
/* [RW 28] The CM header value for QM request (primary). */
#define XCM_REG_XQM_XCM_HDR_P 0x200a0
/* [RW 28] The CM header value for QM request (secondary). */
......@@ -4665,6 +4806,8 @@
#define XSDM_REG_AGG_INT_EVENT_10 0x166060
#define XSDM_REG_AGG_INT_EVENT_11 0x166064
#define XSDM_REG_AGG_INT_EVENT_12 0x166068
#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
#define XSDM_REG_AGG_INT_EVENT_14 0x166070
#define XSDM_REG_AGG_INT_EVENT_2 0x166040
#define XSDM_REG_AGG_INT_EVENT_20 0x166088
#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
......
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