Commit 7cafae52 authored by Linus Torvalds's avatar Linus Torvalds

Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] iwmmxt thread state alignment
  [ARM] 3350/1: Enable 1-wire on ARM
  [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem
  [ARM] 3355/1: NSLU2: remove propmt depends
  [ARM] 3354/1: NAS100d: fix power led handling
  [ARM] Fix muldi3.S
parents ba244fe9 cdaabbd7
...@@ -799,6 +799,8 @@ source "drivers/i2c/Kconfig" ...@@ -799,6 +799,8 @@ source "drivers/i2c/Kconfig"
source "drivers/spi/Kconfig" source "drivers/spi/Kconfig"
source "drivers/w1/Kconfig"
source "drivers/hwmon/Kconfig" source "drivers/hwmon/Kconfig"
#source "drivers/l3/Kconfig" #source "drivers/l3/Kconfig"
......
...@@ -57,7 +57,9 @@ int main(void) ...@@ -57,7 +57,9 @@ int main(void)
DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate));
DEFINE(TI_IWMMXT_STATE, (offsetof(struct thread_info, fpstate)+4)&~7); #ifdef CONFIG_IWMMXT
DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt));
#endif
BLANK(); BLANK();
DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0)); DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0));
DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1)); DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1));
......
...@@ -610,15 +610,12 @@ static int ptrace_setfpregs(struct task_struct *tsk, void __user *ufp) ...@@ -610,15 +610,12 @@ static int ptrace_setfpregs(struct task_struct *tsk, void __user *ufp)
static int ptrace_getwmmxregs(struct task_struct *tsk, void __user *ufp) static int ptrace_getwmmxregs(struct task_struct *tsk, void __user *ufp)
{ {
struct thread_info *thread = task_thread_info(tsk); struct thread_info *thread = task_thread_info(tsk);
void *ptr = &thread->fpstate;
if (!test_ti_thread_flag(thread, TIF_USING_IWMMXT)) if (!test_ti_thread_flag(thread, TIF_USING_IWMMXT))
return -ENODATA; return -ENODATA;
iwmmxt_task_disable(thread); /* force it to ram */ iwmmxt_task_disable(thread); /* force it to ram */
/* The iWMMXt state is stored doubleword-aligned. */ return copy_to_user(ufp, &thread->fpstate.iwmmxt, IWMMXT_SIZE)
if (((long) ptr) & 4) ? -EFAULT : 0;
ptr += 4;
return copy_to_user(ufp, ptr, 0x98) ? -EFAULT : 0;
} }
/* /*
...@@ -627,15 +624,12 @@ static int ptrace_getwmmxregs(struct task_struct *tsk, void __user *ufp) ...@@ -627,15 +624,12 @@ static int ptrace_getwmmxregs(struct task_struct *tsk, void __user *ufp)
static int ptrace_setwmmxregs(struct task_struct *tsk, void __user *ufp) static int ptrace_setwmmxregs(struct task_struct *tsk, void __user *ufp)
{ {
struct thread_info *thread = task_thread_info(tsk); struct thread_info *thread = task_thread_info(tsk);
void *ptr = &thread->fpstate;
if (!test_ti_thread_flag(thread, TIF_USING_IWMMXT)) if (!test_ti_thread_flag(thread, TIF_USING_IWMMXT))
return -EACCES; return -EACCES;
iwmmxt_task_release(thread); /* force a reload */ iwmmxt_task_release(thread); /* force a reload */
/* The iWMMXt state is stored doubleword-aligned. */ return copy_from_user(&thead->fpstate.iwmmxt, ufp, IWMMXT_SIZE)
if (((long) ptr) & 4) ? -EFAULT : 0;
ptr += 4;
return copy_from_user(ptr, ufp, 0x98) ? -EFAULT : 0;
} }
#endif #endif
......
...@@ -29,8 +29,8 @@ ENTRY(__aeabi_lmul) ...@@ -29,8 +29,8 @@ ENTRY(__aeabi_lmul)
mul xh, yl, xh mul xh, yl, xh
mla xh, xl, yh, xh mla xh, xl, yh, xh
mov ip, xl, asr #16 mov ip, xl, lsr #16
mov yh, yl, asr #16 mov yh, yl, lsr #16
bic xl, xl, ip, lsl #16 bic xl, xl, ip, lsl #16
bic yl, yl, yh, lsl #16 bic yl, yl, yh, lsl #16
mla xh, yh, ip, xh mla xh, yh, ip, xh
......
...@@ -8,11 +8,9 @@ menu "Intel IXP4xx Implementation Options" ...@@ -8,11 +8,9 @@ menu "Intel IXP4xx Implementation Options"
comment "IXP4xx Platforms" comment "IXP4xx Platforms"
# This entry is placed on top because otherwise it would have
# been shown as a submenu.
config MACH_NSLU2 config MACH_NSLU2
bool bool
prompt "NSLU2" if !(MACH_IXDP465 || MACH_IXDPG425 || ARCH_IXDP425 || ARCH_ADI_COYOTE || ARCH_AVILA || ARCH_IXCDP1100 || ARCH_PRPMC1100 || MACH_GTWX5715) prompt "Linksys NSLU2"
help help
Say 'Y' here if you want your kernel to support Linksys's Say 'Y' here if you want your kernel to support Linksys's
NSLU2 NAS device. For more information on this platform, NSLU2 NAS device. For more information on this platform,
......
...@@ -113,6 +113,9 @@ static void __init nas100d_init(void) ...@@ -113,6 +113,9 @@ static void __init nas100d_init(void)
{ {
ixp4xx_sys_init(); ixp4xx_sys_init();
/* gpio 14 and 15 are _not_ clocks */
*IXP4XX_GPIO_GPCLKR = 0;
nas100d_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); nas100d_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
nas100d_flash_resource.end = nas100d_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
......
...@@ -96,15 +96,16 @@ ENTRY(v6_coherent_user_range) ...@@ -96,15 +96,16 @@ ENTRY(v6_coherent_user_range)
#ifdef HARVARD_CACHE #ifdef HARVARD_CACHE
bic r0, r0, #CACHE_LINE_SIZE - 1 bic r0, r0, #CACHE_LINE_SIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D line 1: mcr p15, 0, r0, c7, c10, 1 @ clean D line
mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
add r0, r0, #CACHE_LINE_SIZE add r0, r0, #CACHE_LINE_SIZE
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
#endif #endif
mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
#ifdef HARVARD_CACHE
mov r0, #0 mov r0, #0
#ifdef HARVARD_CACHE
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
#else
mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
#endif #endif
mov pc, lr mov pc, lr
......
...@@ -24,14 +24,16 @@ ...@@ -24,14 +24,16 @@
static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
{ {
unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
const int zero = 0;
set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
flush_tlb_kernel_page(to); flush_tlb_kernel_page(to);
asm( "mcrr p15, 0, %1, %0, c14\n" asm( "mcrr p15, 0, %1, %0, c14\n"
" mcrr p15, 0, %1, %0, c5\n" " mcr p15, 0, %2, c7, c10, 4\n"
" mcr p15, 0, %2, c7, c5, 0\n"
: :
: "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES) : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
: "cc"); : "cc");
} }
......
...@@ -55,8 +55,10 @@ struct fp_soft_struct { ...@@ -55,8 +55,10 @@ struct fp_soft_struct {
unsigned int save[FP_SOFT_SIZE]; /* undefined information */ unsigned int save[FP_SOFT_SIZE]; /* undefined information */
}; };
#define IWMMXT_SIZE 0x98
struct iwmmxt_struct { struct iwmmxt_struct {
unsigned int save[0x98/sizeof(int) + 1]; unsigned int save[IWMMXT_SIZE / sizeof(unsigned int)];
}; };
union fp_state { union fp_state {
......
...@@ -59,7 +59,7 @@ struct thread_info { ...@@ -59,7 +59,7 @@ struct thread_info {
struct cpu_context_save cpu_context; /* cpu context */ struct cpu_context_save cpu_context; /* cpu context */
__u8 used_cp[16]; /* thread used copro */ __u8 used_cp[16]; /* thread used copro */
unsigned long tp_value; unsigned long tp_value;
union fp_state fpstate; union fp_state fpstate __attribute__((aligned(8)));
union vfp_state vfpstate; union vfp_state vfpstate;
struct restart_block restart_block; struct restart_block restart_block;
}; };
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment