Commit 753115be authored by Santosh Shilimkar's avatar Santosh Shilimkar

OMAP4: Enable L2 Cache support for OMAP4430 SDP

This patch enables L2 Cache support for OMAP4.
Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
parent 1e83f525
...@@ -229,7 +229,7 @@ CONFIG_HAS_TLS_REG=y ...@@ -229,7 +229,7 @@ CONFIG_HAS_TLS_REG=y
# CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set # CONFIG_ARM_ERRATA_460075 is not set
CONFIG_ARM_GIC=y CONFIG_ARM_GIC=y
# CONFIG_CACHE_L2X0 is not set
# #
# Bus support # Bus support
# #
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include <mach/control.h> #include <mach/control.h>
#include <mach/timer-gp.h> #include <mach/timer-gp.h>
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
static struct platform_device sdp4430_lcd_device = { static struct platform_device sdp4430_lcd_device = {
.name = "sdp4430_lcd", .name = "sdp4430_lcd",
...@@ -70,6 +71,16 @@ static void __init omap_4430sdp_init_irq(void) ...@@ -70,6 +71,16 @@ static void __init omap_4430sdp_init_irq(void)
static void __init omap_4430sdp_init(void) static void __init omap_4430sdp_init(void)
{ {
#ifdef CONFIG_CACHE_L2X0
void __iomem *l2cache_base = IO_ADDRESS(OMAP44XX_L2CACHE_BASE);
/* set RAM latencies to 1 cycle for eASIC */
writel(0, l2cache_base + L2X0_TAG_LATENCY_CTRL);
writel(0, l2cache_base + L2X0_DATA_LATENCY_CTRL);
/* 16KB way size, 8-way associativity, parity disabled
* Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
l2x0_init(l2cache_base, 0x02520000, 0xc0000fff);
#endif
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
omap_board_config = sdp4430_config; omap_board_config = sdp4430_config;
omap_board_config_size = ARRAY_SIZE(sdp4430_config); omap_board_config_size = ARRAY_SIZE(sdp4430_config);
......
...@@ -758,7 +758,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH ...@@ -758,7 +758,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
config CACHE_L2X0 config CACHE_L2X0
bool "Enable the L2x0 outer cache controller" bool "Enable the L2x0 outer cache controller"
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_OMAP4
default y default y
select OUTER_CACHE select OUTER_CACHE
help help
......
...@@ -43,6 +43,8 @@ ...@@ -43,6 +43,8 @@
#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100 #define OMAP44XX_LOCAL_TWD_SIZE 0x00000100
#define OMAP44XX_WKUPGEN_BASE 0x48281000 #define OMAP44XX_WKUPGEN_BASE 0x48281000
#define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) #define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
#define OMAP44XX_L2CACHE_BASE 0x48242000
#define OMAP44XX_VA_L2CACHE_BASE 0x48242000
#endif /* __ASM_ARCH_OMAP44XX_H */ #endif /* __ASM_ARCH_OMAP44XX_H */
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