Commit 748a7683 authored by Kumar Gala's avatar Kumar Gala

[POWERPC] Fix modpost warnings from head*.S on ppc32

We get warnings like the following from the various ppc32 head*.S files:

WARNING: vmlinux.o(.text+0x358): Section mismatch: reference to .init.text:early_init (between 'skpinv' and 'interrupt_base')
WARNING: vmlinux.o(.text+0x380): Section mismatch: reference to .init.text:machine_init (between 'skpinv' and 'interrupt_base')
WARNING: vmlinux.o(.text+0x384): Section mismatch: reference to .init.text:MMU_init (between 'skpinv' and 'interrupt_base')
WARNING: vmlinux.o(.text+0x3aa): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base')
WARNING: vmlinux.o(.text+0x3ae): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base')

Added a .text.head section simliar to what other architectures do since
modpost already excludes this from its warnings.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 5e14d21e
...@@ -48,20 +48,17 @@ ...@@ -48,20 +48,17 @@
mtspr SPRN_DBAT##n##L,RB; \ mtspr SPRN_DBAT##n##L,RB; \
1: 1:
.text .section .text.head, "ax"
.stabs "arch/powerpc/kernel/",N_SO,0,0,0f .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
.stabs "head_32.S",N_SO,0,0,0f .stabs "head_32.S",N_SO,0,0,0f
0: 0:
.globl _stext _ENTRY(_stext);
_stext:
/* /*
* _start is defined this way because the XCOFF loader in the OpenFirmware * _start is defined this way because the XCOFF loader in the OpenFirmware
* on the powermac expects the entry point to be a procedure descriptor. * on the powermac expects the entry point to be a procedure descriptor.
*/ */
.text _ENTRY(_start);
.globl _start
_start:
/* /*
* These are here for legacy reasons, the kernel used to * These are here for legacy reasons, the kernel used to
* need to look like a coff function entry for the pmac * need to look like a coff function entry for the pmac
...@@ -841,7 +838,7 @@ relocate_kernel: ...@@ -841,7 +838,7 @@ relocate_kernel:
* r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
* on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
*/ */
_GLOBAL(copy_and_flush) _ENTRY(copy_and_flush)
addi r5,r5,-4 addi r5,r5,-4
addi r6,r6,-4 addi r6,r6,-4
4: li r0,L1_CACHE_BYTES/4 4: li r0,L1_CACHE_BYTES/4
...@@ -954,9 +951,9 @@ __secondary_start: ...@@ -954,9 +951,9 @@ __secondary_start:
* included in CONFIG_6xx * included in CONFIG_6xx
*/ */
#if !defined(CONFIG_6xx) #if !defined(CONFIG_6xx)
_GLOBAL(__save_cpu_setup) _ENTRY(__save_cpu_setup)
blr blr
_GLOBAL(__restore_cpu_setup) _ENTRY(__restore_cpu_setup)
blr blr
#endif /* !defined(CONFIG_6xx) */ #endif /* !defined(CONFIG_6xx) */
...@@ -1080,7 +1077,7 @@ start_here: ...@@ -1080,7 +1077,7 @@ start_here:
/* /*
* Set up the segment registers for a new context. * Set up the segment registers for a new context.
*/ */
_GLOBAL(set_context) _ENTRY(set_context)
mulli r3,r3,897 /* multiply context by skew factor */ mulli r3,r3,897 /* multiply context by skew factor */
rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
addis r3,r3,0x6000 /* Set Ks, Ku bits */ addis r3,r3,0x6000 /* Set Ks, Ku bits */
......
...@@ -52,9 +52,9 @@ ...@@ -52,9 +52,9 @@
* *
* This is all going to change RSN when we add bi_recs....... -- Dan * This is all going to change RSN when we add bi_recs....... -- Dan
*/ */
.text .section .text.head, "ax"
_GLOBAL(_stext) _ENTRY(_stext);
_GLOBAL(_start) _ENTRY(_start);
/* Save parameters we are passed. /* Save parameters we are passed.
*/ */
...@@ -89,9 +89,9 @@ turn_on_mmu: ...@@ -89,9 +89,9 @@ turn_on_mmu:
*/ */
. = 0xc0 . = 0xc0
crit_save: crit_save:
_GLOBAL(crit_r10) _ENTRY(crit_r10)
.space 4 .space 4
_GLOBAL(crit_r11) _ENTRY(crit_r11)
.space 4 .space 4
/* /*
...@@ -814,7 +814,7 @@ finish_tlb_load: ...@@ -814,7 +814,7 @@ finish_tlb_load:
* The PowerPC 4xx family of processors do not have an FPU, so this just * The PowerPC 4xx family of processors do not have an FPU, so this just
* returns. * returns.
*/ */
_GLOBAL(giveup_fpu) _ENTRY(giveup_fpu)
blr blr
/* This is where the main kernel code starts. /* This is where the main kernel code starts.
......
...@@ -50,9 +50,9 @@ ...@@ -50,9 +50,9 @@
* r7 - End of kernel command line string * r7 - End of kernel command line string
* *
*/ */
.text .section .text.head, "ax"
_GLOBAL(_stext) _ENTRY(_stext);
_GLOBAL(_start) _ENTRY(_start);
/* /*
* Reserve a word at a fixed location to store the address * Reserve a word at a fixed location to store the address
* of abatron_pteptrs * of abatron_pteptrs
......
...@@ -38,12 +38,9 @@ ...@@ -38,12 +38,9 @@
#else #else
#define DO_8xx_CPU6(val, reg) #define DO_8xx_CPU6(val, reg)
#endif #endif
.text .section .text.head, "ax"
.globl _stext _ENTRY(_stext);
_stext: _ENTRY(_start);
.text
.globl _start
_start:
/* MPC8xx /* MPC8xx
* This port was done on an MBX board with an 860. Right now I only * This port was done on an MBX board with an 860. Right now I only
......
...@@ -52,9 +52,9 @@ ...@@ -52,9 +52,9 @@
* r7 - End of kernel command line string * r7 - End of kernel command line string
* *
*/ */
.text .section .text.head, "ax"
_GLOBAL(_stext) _ENTRY(_stext);
_GLOBAL(_start) _ENTRY(_start);
/* /*
* Reserve a word at a fixed location to store the address * Reserve a word at a fixed location to store the address
* of abatron_pteptrs * of abatron_pteptrs
......
...@@ -34,6 +34,8 @@ SECTIONS ...@@ -34,6 +34,8 @@ SECTIONS
/* Text and gots */ /* Text and gots */
.text : { .text : {
ALIGN_FUNCTION();
*(.text.head)
_text = .; _text = .;
TEXT_TEXT TEXT_TEXT
SCHED_TEXT SCHED_TEXT
......
...@@ -209,6 +209,10 @@ GLUE(.,name): ...@@ -209,6 +209,10 @@ GLUE(.,name):
#else /* 32-bit */ #else /* 32-bit */
#define _ENTRY(n) \
.globl n; \
n:
#define _GLOBAL(n) \ #define _GLOBAL(n) \
.text; \ .text; \
.stabs __stringify(n:F-1),N_FUN,0,0,n;\ .stabs __stringify(n:F-1),N_FUN,0,0,n;\
......
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