Intial Bridge changes for new tree These are the bridge changes for OMAP4 and...

Intial Bridge changes for new tree These are the bridge changes for OMAP4 and Notify Support. Require cleanup.
Signed-off-by: Ramesh Gupta G <grgupta@ti.com>

arch/arm/plat-omap/include/dspbridge/_chnl_sm.h

@@ -75,6 +75,7 @@
 #ifndef _CHNL_WORDSIZE
 #define _CHNL_WORDSIZE 4	/* default _CHNL_WORDSIZE is 2 bytes/word */
 #endif
+#ifdef OMAP_3430
 
 #define MAXOPPS 16
 
@@ -105,6 +106,7 @@ struct loadMonStruct {
     u32 predDspFreq;
 };
 
+#endif
 	enum SHM_DESCTYPE {
 		SHM_CURROPP = 0,
 		SHM_OPPINFO = 1,
@@ -127,6 +129,8 @@ struct loadMonStruct {
 		u32 arg;	/* Arg for Issue/Reclaim (23 bits for 55x). */
 		u32 resvd;	/* Keep structure size even for 32-bit DSPs */
 
+#ifdef OMAP_3430
+#ifndef DISABLE_BRIDGE_PM
 		/* Operating Point structure */
 		struct oppStruct  oppTableStruct;
 		/* Operating Point Request structure */
@@ -135,6 +139,8 @@ struct loadMonStruct {
 		struct loadMonStruct loadMonInfo;
 		char dummy[184];             /* padding to 256 byte boundary */
 		u32 shm_dbg_var[64];         /* shared memory debug variables */
+#endif
+#endif
 	} ;
 
 	/* Channel Manager: only one created per board: */

arch/arm/plat-omap/include/dspbridge/cfgdefs.h

@@ -89,6 +89,10 @@
 		u32 dwNumChnls;
 		void __iomem *dwPrmBase;
 		void __iomem *dwCmBase;
+#ifdef OMAP44XX
+        u32 dwCm1Base;
+        u32 dwCm2Base;
+#endif
 		void __iomem *dwPerBase;
 		u32 dwPerPmBase;
 		u32 dwCorePmBase;

arch/arm/plat-omap/include/dspbridge/drv.h

@@ -68,6 +68,7 @@
 #define DRV_ASSIGN     1
 #define DRV_RELEASE    0
 
+#ifdef OMAP_3430
 /* Provide the DSP Internal memory windows that can be accessed from L3 address
  * space */
 
@@ -118,6 +119,52 @@
 #define OMAP_PRCM_VDD1_DOMAIN 1
 #define OMAP_PRCM_VDD2_DOMAIN 2
 
+#else
+/* Provide the DSP Internal memory windows that can be accessed from L3 address
+ * space */
+ #define OMAP_GEM_BASE   0x107F8000
+#define OMAP_DSP_SIZE   0x00720000
+
+/* MEM1 is L2 RAM + L2 Cache space */
+#define OMAP_DSP_MEM1_BASE 0x5C7F8000
+#define OMAP_DSP_MEM1_SIZE 0x18000
+#define OMAP_DSP_GEM1_BASE 0x107F8000
+
+
+/* MEM2 is L1P RAM/CACHE space */
+#define OMAP_DSP_MEM2_BASE 0x5CE00000
+#define OMAP_DSP_MEM2_SIZE 0x8000
+#define OMAP_DSP_GEM2_BASE 0x10E00000
+
+/* MEM3 is L1D RAM/CACHE space */
+#define OMAP_DSP_MEM3_BASE 0x5CF04000
+#define OMAP_DSP_MEM3_SIZE 0x14000
+#define OMAP_DSP_GEM3_BASE 0x10F04000
+
+#define OMAP_IVA2_PRM_BASE 0x4A306000
+#define OMAP_IVA2_PRM_SIZE 0x2000
+
+#define OMAP_IVA2_CM1_BASE 0x4A004000
+#define OMAP_IVA2_CM1_SIZE 0x1000
+
+#define OMAP_IVA2_CM2_BASE 0x4A008000
+#define OMAP_IVA2_CM2_SIZE 0x2000
+
+
+#define OMAP_SYSC_BASE 0x4A002000
+#define OMAP_SYSC_SIZE 0x1000
+
+#define OMAP_MBOX_BASE 0x4A0F4000
+#define OMAP_MBOX_SIZE 0x1000
+
+#define OMAP_DMMU_BASE 0x4A066000
+#define OMAP_DMMU_SIZE 0x1000
+
+#define OMAP_PRCM_VDD1_DOMAIN 1
+#define OMAP_PRCM_VDD2_DOMAIN 2
+
+#endif
+
 #ifndef RES_CLEANUP_DISABLE
 
 /* GPP PROCESS CLEANUP Data structures */

arch/arm/plat-omap/include/dspbridge/host_os.h

@@ -60,9 +60,14 @@
 #include <asm/cacheflush.h>
 #include <linux/dma-mapping.h>
 
-/* TODO -- Remove, once BP defines them */
-#define INT_MAIL_MPU_IRQ        26
-#define INT_DSP_MMU_IRQ        28
+
+#ifdef OMAP_3430
+#define INT_MAIL_MPU_IRQ        INT_24XX_MAIL_U0_MPU
+#define INT_DSP_MMU_IRQ         INT_24XX_DSP_MMU
+#else
+#define INT_MAIL_MPU_IRQ        INT_44XX_MAIL_U0_MPU
+#define INT_DSP_MMU_IRQ         INT_44XX_DSP_MMU
+#endif
 
 struct dspbridge_platform_data {
 	void 	(*dsp_set_min_opp)(u8 opp_id);

arch/arm/plat-omap/include/dspbridge/io_sm.h

@@ -54,8 +54,8 @@
 
 #include <dspbridge/_chnl_sm.h>
 #include <dspbridge/host_os.h>
-
 #include <dspbridge/iodefs.h>
+#include <syslink/notifydefs.h>
 
 #define IO_INPUT            0
 #define IO_OUTPUT           1
@@ -129,7 +129,10 @@
  *      Interrupts are disabled and EOI for this interrupt has been sent.
  *  Ensures:
  */
-       irqreturn_t IO_ISR(int irq, IN void *pRefData);
+	void IO_ISR (IN unsigned long int  procId,
+                     IN void * pRefData,
+                     struct pt_regs *reg);
+
 /*
  *  ======== IO_RequestChnl ========
  *  Purpose:

drivers/dsp/bridge/Kbuild

@@ -15,7 +15,7 @@ librmgr = rmgr/dbdcd.o rmgr/disp.o rmgr/drv.o rmgr/mgr.o rmgr/node.o \
 		rmgr/proc.o rmgr/pwr.o rmgr/rmm.o rmgr/strm.o rmgr/dspdrv.o \
 		rmgr/nldr.o rmgr/drv_interface.o
 libdload = dynload/cload.o dynload/getsection.o dynload/reloc.o
-libhw = hw/hw_prcm.o hw/hw_dspssC64P.o hw/hw_mmu.o hw/hw_mbox.o
+libhw = hw/hw_prcm.o hw/hw_dspssC64P.o hw/hw_mmu.o
 
 bridgedriver-objs = $(libgen) $(libservices) $(libwmd) $(libpmgr) $(librmgr) \
 			$(libdload) $(libhw)
@@ -28,7 +28,7 @@ endif
 #Machine dependent
 ccflags-y += -D_TI_ -D_DB_TIOMAP -DTMS32060 \
 		-DTICFG_PROC_VER -DTICFG_EVM_TYPE -DCHNL_SMCLASS \
-		-DCHNL_MESSAGES -DUSE_LEVEL_1_MACROS
+		-DCHNL_MESSAGES -DUSE_LEVEL_1_MACROS -DOMAP44XX -DCONFIG_DISABLE_BRIDGE_PM
 
 #Header files
 ccflags-y += -Idrivers/dsp/bridge/services

drivers/dsp/bridge/hw/PRCMAccInt.h

@@ -18,6 +18,7 @@
 #define _PRCM_ACC_INT_H
 
 /* Mappings of level 1 EASI function numbers to function names */
+#ifdef OMAP_3430
 
 #define EASIL1_PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32  \
 						(PRCM_BASE_EASIL1 + 349)
@@ -297,4 +298,171 @@ enum PRCMPM_PWSTCTRL_IVA2PowerStateE {
     PRCMPM_PWSTCTRL_IVA2PowerStateOFF = 0x0000
 } ;
 
-#endif /* _PRCM_ACC_INT_H */
+#else
+
+#define PRM_PRM_IRQSTATUS_TESLA_OFFSET 			 (u32)(0x030)
+#define PRM_PRM_IRQENABLE_TESLA_OFFSET           (u32)(0x038)
+
+/*TESLA_PRM*/
+#define PRM_PM_TESLA_PWRSTCTRL_OFFSET            (u32)(0x400)
+#define PRM_PM_TESLA_PWRSTST_OFFSET              (u32)(0x404)
+#define PRM_RM_TESLA_RSTCTRL_OFFSET              (u32)(0x410)
+#define PRM_RM_TESLA_RSTST_OFFSET                (u32)(0x414)
+#define PRM_RM_TESLA_TESLA_CONTEXT_OFFSET        (u32)(0x424)
+
+/*CORE_PRM*/
+#define PRM_PM_CORE_PWRSTCTRL_OFFSET             (u32)(0x700)
+
+/*ALWAYS_ON_PRM*/
+#define PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET         (u32)(0x630)
+#define PRM_RM_ALWON_SR_IVA_CONTEXT_OFFSET       (u32)(0x634)
+
+
+/*CM1*/
+/*base address = 0x4A00_5000*/
+
+/*CKGEN_CM1*/
+#define CM1_CM_CLKMODE_DPLL_IVA_OFFSET           (u32)(0x1A0)
+#define CM1_CM_IDLEST_DPLL_IVA_OFFSET            (u32)(0x1A4)
+#define CM1_CM_AUTOIDLE_DPLL_IVA_OFFSET          (u32)(0x1A8)
+#define CM1_CM_CLKSEL_DPLL_IVA_OFFSET            (u32)(0x1AC)
+#define CM1_CM_DIV_M2_DPLL_IVA_OFFSET            (u32)(0x1B0)
+#define CM1_CM_DIV_M4_DPLL_IVA_OFFSET            (u32)(0x1B8)
+#define CM1_CM_DIV_M5_DPLL_IVA_OFFSET            (u32)(0x1BC)
+#define CM1_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET    (u32)(0x1C8)
+#define CM1_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET    (u32)(0x1CC)
+#define CM1_CM_BYPCLK_DPLL_IVA_OFFSET            (u32)(0x1DC)
+
+/*TESLA_CM1*/
+#define CM1_CM_TESLA_CLKSTCTRL_OFFSET            (u32)(0x400)
+#define CM1_CM_TESLA_STATICDEP_OFFSET            (u32)(0x404)
+#define CM1_CM_TESLA_DYNAMICDEP_OFFSET           (u32)(0x408)
+#define CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET        (u32)(0x420)
+
+/*ABE_CM1*/
+#define CM1_CM1_ABE_CLKSTCTRL_OFFSET             (u32)(0x500)
+#define CM1_CM1_ABE_MCBSP1_CLKCTRL_OFFSET        (u32)(0x548)
+#define CM1_CM1_ABE_MCBSP2_CLKCTRL_OFFSET        (u32)(0x550)
+#define CM1_CM1_ABE_MCBSP3_CLKCTRL_OFFSET        (u32)(0x558)
+#define CM1_CM1_ABE_TIMER5_CLKCTRL_OFFSET        (u32)(0x568)
+#define CM1_CM1_ABE_TIMER6_CLKCTRL_OFFSET        (u32)(0x570)
+#define CM1_CM1_ABE_TIMER7_CLKCTRL_OFFSET        (u32)(0x578)
+#define CM1_CM1_ABE_TIMER8_CLKCTRL_OFFSET        (u32)(0x580)
+
+/*CM2*/
+/*base address = 0x4A00_8000*/
+
+/*CKGEN_CM2*/
+#define CM2_CM_IVA_DVFS_PERF_TESLA_OFFSET        (u32)(0x128)
+#define CM2_CM_IVA_DVFS_PERF_IVAHD_OFFSET        (u32)(0x12C)
+#define CM2_CM_IVA_DVFS_PERF_ABE_OFFSET          (u32)(0x130)
+#define CM2_CM_IVA_DVFS_RESULT_OFFSET            (u32)(0x134)
+#define CM2_CM_IVA_DVFS_CURRENT_OFFSET           (u32)(0x138)
+
+/*L4PER_CM2*/
+#define CM2_CM_L4PER_CLKSTCTRL_OFFSET            (u32)(0x1400)
+#define CM2_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET    (u32)(0x1428)
+#define CM2_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET    (u32)(0x1430)
+#define CM2_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET     (u32)(0x1438)
+#define CM2_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET     (u32)(0x1440)
+#define CM2_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET     (u32)(0x1448)
+#define CM2_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET     (u32)(0x1450)
+#define CM2_CM_L4PER_MCBSP4_CLKCTRL_OFFSET       (u32)(0x14E0)
+#define CM2_CM_L4PER_MCBSP5_CLKCTRL_OFFSET       (u32)(0x14E8)
+
+
+/*BITS MASKS & OFFSETS*/
+
+/******************PM_TESLA_PWRSTCTRL***********/
+#define PM_TESLA_PWRSTCTRL_PowerState_OFFSET            (u32)(0x0)
+#define PM_TESLA_PWRSTCTRL_PowerState_MASK              (u32)(0x3)
+#define PM_TESLA_PWRSTCTRL_LogicRetState_OFFSET         (u32)(0x2)
+#define PM_TESLA_PWRSTCTRL_LogicRetState_MASK           (u32)(0x4)
+#define PM_TESLA_PWRSTCTRL_L1RetState_OFFSET            (u32)(0x8)
+#define PM_TESLA_PWRSTCTRL_L1RetState_MASK              (u32)(0x100)
+#define PM_TESLA_PWRSTCTRL_L2RetState_OFFSET            (u32)(0x9)
+#define PM_TESLA_PWRSTCTRL_L2RetState_MASK              (u32)(0x200)
+
+/******************PRM_PM_TESLA_PWRSTST*********/
+#define PM_TESLA_PWRSTST_PowerState_OFFSET              (u32)(0x0)
+#define PM_TESLA_PWRSTST_PowerState_MASK                (u32)(0x3)
+
+/******************RM_TESLA_RSTCTRL*************/
+#define RM_TESLA_RSTCTRL_RST1_MASK                      (u32)(0x1)
+#define RM_TESLA_RSTCTRL_RST1_OFFSET                    (u32)(0x0)
+#define RM_TESLA_RSTCTRL_RST2_MASK                      (u32)(0x2)
+#define RM_TESLA_RSTCTRL_RST2_OFFSET                    (u32)(0x1)
+
+/******************RM_TESLA_RSTST***************/
+
+#define RM_TESLA_RSTST_Clear_MASK                       (u32)(0x0F)
+
+/******************RM_TESLA_TESLA_CONTEXT*******/
+
+#define RM_TESLA_TESLA_CONTEXT_Clear_MASK               (u32)(0x701)
+
+/******************PM_CORE_PWRSTCTRL************/
+
+#define PRM_PM_CORE_PWRSTCTRL_PowerControl_OFFSET       (u32)(0x0)
+#define PRM_PM_CORE_PWRSTCTRL_PowerControl_MASK         (u32)(0x3)
+
+/******************PM_ALWON_SR_IVA_WKDEP********/
+
+#define PM_ALWON_SR_IVA_WKDEP_MPU_OFFSET                (u32)(0x0)
+#define PM_ALWON_SR_IVA_WKDEP_MPU_MASK                  (u32)(0x1)
+#define PM_ALWON_SR_IVA_WKDEP_DUCATI_OFFSET             (u32)(0x1)
+#define PM_ALWON_SR_IVA_WKDEP_DUCATI_MASK               (u32)(0x2)
+
+/******************CM_TESLA_CLKSTCTRL***********/
+
+#define CM_TESLA_CLKSTCTRL_Transition_OFFSET            (u32)(0x0)
+#define CM_TESLA_CLKSTCTRL_Transition_MASK              (u32)(0x3)
+
+/******************CM_TESLA_TESLA_CLKCTRL*******/
+#define CM_TESLA_TESLA_CLKCTRL_STBY_MASK                (u32)(0x40000)
+#define CM_TESLA_TESLA_CLKCTRL_STBY_OFFSET              (u32)(0x18)
+#define CM_TESLA_TESLA_CLKCTRL_IDLE_MASK                (u32)(0x30000)
+#define CM_TESLA_TESLA_CLKCTRL_IDLE_OFFSET              (u32)(0x16)
+#define CM_TESLA_TESLA_CLKCTRL_MODMODE_OFFSET           (u32)(0x0)
+#define CM_TESLA_TESLA_CLKCTRL_MODMODE_MASK             (u32)(0x03)
+
+/******************CM1_ABE_CLKSTCTRL************/
+
+#define CM1_ABE_CLKSTCTRL_Transition_OFFSET             (u32)(0x0)
+#define CM1_ABE_CLKSTCTRL_Transition_MASK               (u32)(0x3)
+
+/******************CM1_ABE_MCBSPX&TIMERX_CLKCTRL*/
+#define CM1_ABE_CLKCTRL_OFFSET                          (u32)(0x0)
+#define CM1_ABE_CLKCTRL_MASK                            (u32)(0x3)
+
+/******************CM1_L4PER_CLKSTCTRL************/
+
+#define CM1_L4PER_CLKSTCTRL_Transition_OFFSET             (u32)(0x0)
+#define CM1_L4PER_CLKSTCTRL_Transition_MASK               (u32)(0x3)
+
+/******************CM1_L4PER_MCBSPX&DMTIMERX_CLKCTRL*/
+#define CM1_L4PER_CLKCTRL_OFFSET                          (u32)(0x0)
+#define CM1_L4PER_CLKCTRL_MASK                            (u32)(0x3)
+
+/******************CM_IVA_DVFS_PERF*************/
+#define CM_IVA_DVFS_PERF_OFFSET                         (u32)(0x0)
+#define CM_IVA_DVFS_PERF_MASK                           (u32)(0xFF)
+
+/*****************************************************************************
+* EXPORTED TYPES
+******************************************************************************
+*/
+
+/* The following type definitions represent the 
+* enumerated values for each bitfield 
+*/
+
+enum PRM_PM_TESLA_PWRSTCTRLE {
+	PM_TESLA_PWRSTCTRLPowerStateOFF           = 0x0000,
+	PM_TESLA_PWRSTCTRLPowerStateRET           = 0x0001,
+	PM_TESLA_PWRSTCTRLPowerStateINACTIVE      = 0x0002,
+	PM_TESLA_PWRSTCTRLPowerStateON            = 0x0003
+};
+
+#endif
+#endif

drivers/dsp/bridge/hw/PRCMRegAcM.h

@@ -26,6 +26,8 @@
 
 #if defined(USE_LEVEL_1_MACROS)
 
+#ifdef OMAP_3430
+
 #define PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32(baseAddress)\
 {\
     const u32 offset = PRCM_PRCM_CLKCFG_CTRL_OFFSET;\
@@ -664,6 +666,599 @@
       (u32)((((u32)(var)) & PRCM_PM_PWSTST_IVA2_PowerStateSt_MASK) >>\
       PRCM_PM_PWSTST_IVA2_PowerStateSt_OFFSET))
 
+#else
+/********************************************************************/
+
+#define PRM_TESLA_PWRSTCTRLReadRegister32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_PM_TESLA_PWRSTCTRL_OFFSET))
+
+/********************************************************************/
+
+#define PRM_TESLA_PWRSTCTRLWriteON32(baseAddress)\
+{\
+	const u32 offset = PRM_PM_TESLA_PWRSTCTRL_OFFSET;\
+	const u32 newValue = (u32)PM_TESLA_PWRSTCTRLPowerStateON <<\
+	PM_TESLA_PWRSTCTRL_PowerState_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+	data &= ~(PM_TESLA_PWRSTCTRL_PowerState_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+}
+
+/********************************************************************/
+
+#define PRM_TESLA_PWRSTCTRLWriteINACTIVE32(baseAddress)\
+{\
+	const u32 offset = PRM_PM_TESLA_PWRSTCTRL_OFFSET;\
+	const u32 newValue = (u32)PM_TESLA_PWRSTCTRLPowerStateINACTIVE <<\
+	PM_TESLA_PWRSTCTRL_PowerState_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+	data &= ~(PM_TESLA_PWRSTCTRL_PowerState_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+}
+
+/********************************************************************/
+
+#define PRM_TESLA_PWRSTCTRLWriteRET32(baseAddress)\
+{\
+	const u32 offset = PRM_PM_TESLA_PWRSTCTRL_OFFSET;\
+	const u32 newValue = (u32)PM_TESLA_PWRSTCTRLPowerStateRET <<\
+	PM_TESLA_PWRSTCTRL_PowerState_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+	data &= ~(PM_TESLA_PWRSTCTRL_PowerState_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+}
+
+/********************************************************************/
+
+#define PRM_TESLA_PWRSTCTRLWriteOFF32(baseAddress)\
+{\
+	const u32 offset = PRM_PM_TESLA_PWRSTCTRL_OFFSET;\
+	const u32 newValue = (u32)PM_TESLA_PWRSTCTRLPowerStateOFF <<\
+	PM_TESLA_PWRSTCTRL_PowerState_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+	data &= ~(PM_TESLA_PWRSTCTRL_PowerState_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+}
+
+/********************************************************************/
+
+#define PRM_TESLA_PWRSTCTRLWriteLOGICRETSTATE32(baseAddress, value)\
+{\
+	const u32 offset = PRM_PM_TESLA_PWRSTCTRL_OFFSET;\
+	register u32 data = \
+	RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(PM_TESLA_PWRSTCTRL_LogicRetState_MASK);\
+	newValue <<= PM_TESLA_PWRSTCTRL_LogicRetState_OFFSET;\
+	newValue &= PM_TESLA_PWRSTCTRL_LogicRetState_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define PRM_TESLA_PWRSTCTRLWriteL1RETSTATE32(baseAddress, value)\
+{\
+	const u32 offset = PRM_PM_TESLA_PWRSTCTRL_OFFSET;\
+	register u32 data = \
+	RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(PM_TESLA_PWRSTCTRL_L1RetState_MASK);\
+	newValue <<= PM_TESLA_PWRSTCTRL_L1RetState_OFFSET;\
+	newValue &= PM_TESLA_PWRSTCTRL_L1RetState_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define PRM_TESLA_PWRSTCTRLWriteL2RETSTATE32(baseAddress, value)\
+{\
+	const u32 offset = PRM_PM_TESLA_PWRSTCTRL_OFFSET;\
+	register u32 data = \
+	RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(PM_TESLA_PWRSTCTRL_L2RetState_MASK);\
+	newValue <<= PM_TESLA_PWRSTCTRL_L2RetState_OFFSET;\
+	newValue  &= PM_TESLA_PWRSTCTRL_L2RetState_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+
+/********************************************************************/
+
+
+#define PRM_TESLA_PWRSTSTReadRegister32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_PM_TESLA_PWRSTST_OFFSET))
+
+/********************************************************************/
+
+
+#define PRM_TESLA_PWRSTSTGet32(baseAddress)\
+	(((RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_PM_TESLA_PWRSTST_OFFSET))&\
+	PM_TESLA_PWRSTST_PowerState_MASK) >>\
+	PM_TESLA_PWRSTST_PowerState_OFFSET)
+
+/********************************************************************/
+
+#define PRM_CORE_PWRSTCTRLWrite32(baseAddress, value)\
+{\
+	const u32 offset = PRM_PM_CORE_PWRSTCTRL_OFFSET;\
+	register u32 data = \
+	RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(PRM_PM_CORE_PWRSTCTRL_PowerControl_MASK);\
+	newValue <<= PRM_PM_CORE_PWRSTCTRL_PowerControl_OFFSET;\
+	newValue &= PRM_PM_CORE_PWRSTCTRL_PowerControl_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+
+#define PRM_TESLA_RSTCTRLReadRegister32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_RM_TESLA_RSTCTRL_OFFSET))
+
+#define PRM_TESLA_RSTCTRL_RST1_Write32(baseAddress, value)\
+{\
+	const u32 offset = PRM_RM_TESLA_RSTCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(RM_TESLA_RSTCTRL_RST1_MASK);\
+	newValue <<= RM_TESLA_RSTCTRL_RST1_OFFSET;\
+	newValue &= RM_TESLA_RSTCTRL_RST1_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define PRM_TESLA_RSTCTRL_RST2_Write32(baseAddress, value)\
+{\
+	const u32 offset = PRM_RM_TESLA_RSTCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(RM_TESLA_RSTCTRL_RST2_MASK);\
+	newValue <<= RM_TESLA_RSTCTRL_RST2_OFFSET;\
+	newValue &= RM_TESLA_RSTCTRL_RST2_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+
+/********************************************************************/
+
+#define PRM_TESLA_RSTSTReadRegister32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_RM_TESLA_RSTST_OFFSET))
+
+/********************************************************************/
+
+#define PRM_TESLA_RSTST_Clear32(baseAddress)\
+{\
+	const u32 offset = PRM_RM_TESLA_RSTST_OFFSET;\
+	register u32 newValue = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	newValue &= ~(RM_TESLA_RSTST_Clear_MASK);\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define PRM_TESLA_CONTEXTReadRegister32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_RM_TESLA_TESLA_CONTEXT_OFFSET))
+
+/********************************************************************/
+
+#define PRM_TESLA_CONTEXT_Clear32(baseAddress)\
+{\
+	const u32 offset = PRM_RM_TESLA_TESLA_CONTEXT_OFFSET;\
+	register u32 newValue = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	newValue &= ~(RM_TESLA_TESLA_CONTEXT_Clear_MASK);\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+
+#define PRM_WKUP_IVA_ReadRegister32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET))
+
+
+/********************************************************************/
+
+#define PRM_WKUP_IVA_MPU_Write32(baseAddress, value)\
+{\
+	const u32 offset = PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(PM_ALWON_SR_IVA_WKDEP_MPU_MASK);\
+	newValue <<= PM_ALWON_SR_IVA_WKDEP_MPU_OFFSET;\
+	newValue &= PM_ALWON_SR_IVA_WKDEP_MPU_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define PRM_WKUP_IVA_DUCATI_Write32(baseAddress, value)\
+{\
+	const u32 offset = PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(PM_ALWON_SR_IVA_WKDEP_DUCATI_MASK);\
+	newValue <<= PM_ALWON_SR_IVA_WKDEP_DUCATI_OFFSET;\
+	newValue &= PM_ALWON_SR_IVA_WKDEP_DUCATI_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define PRM_ALWON_CONTEXTReadRegister32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_RM_ALWON_SR_IVA_CONTEXT_OFFSET))
+
+
+/**********************************************************************/
+
+#define CM_CLKSTCTRL_TESLAWriteRegister32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM_TESLA_CLKSTCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM_TESLA_CLKSTCTRL_Transition_MASK);\
+	newValue <<= CM_TESLA_CLKSTCTRL_Transition_OFFSET;\
+	newValue &= CM_TESLA_CLKSTCTRL_Transition_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+
+/**********************************************************************/
+
+#define CM_TESLA_TESLA_CLKCTRLWriteRegister32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM_TESLA_TESLA_CLKCTRL_MODMODE_MASK);\
+	newValue <<= CM_TESLA_TESLA_CLKCTRL_MODMODE_OFFSET;\
+	newValue &= CM_TESLA_TESLA_CLKCTRL_MODMODE_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_TESLA_STBYST_Read32(baseAddress)\
+	(((RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET))&\
+	CM_TESLA_TESLA_CLKCTRL_STBY_MASK) >>\
+	CM_TESLA_TESLA_CLKCTRL_STBY_OFFSET)
+
+/********************************************************************/
+
+
+#define CM_TESLA_IDLEST_Read32(baseAddress)\
+	(((RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET))&\
+	CM_TESLA_TESLA_CLKCTRL_IDLE_MASK) >>\
+	CM_TESLA_TESLA_CLKCTRL_IDLE_OFFSET)
+
+
+/********************************************************************/
+
+#define CM_IVA_DVFS_PERFTESTLA_Read32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_PERF_TESLA_OFFSET))
+
+
+/********************************************************************/
+
+#define CM_IVA_DVFS_PERFTESTLA_Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_IVA_DVFS_PERF_TESLA_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM_IVA_DVFS_PERF_MASK);\
+	newValue <<= CM_IVA_DVFS_PERF_OFFSET;\
+	newValue &= CM_IVA_DVFS_PERF_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_IVA_DVFS_PERFIVAHD_Read32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_PERF_IVAHD_OFFSET))
+
+/********************************************************************/
+
+#define CM_IVA_DVFS_PERFIVAHD_Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_IVA_DVFS_PERF_IVAHD_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM_IVA_DVFS_PERF_MASK);\
+	newValue <<= CM_IVA_DVFS_PERF_OFFSET;\
+	newValue &= CM_IVA_DVFS_PERF_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_IVA_DVFS_PERFABE_Read32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_PERF_ABE_OFFSET))
+
+/********************************************************************/
+
+#define CM_IVA_DVFS_PERFABE_Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_IVA_DVFS_PERF_ABE_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM_IVA_DVFS_PERF_MASK);\
+	newValue <<= CM_IVA_DVFS_PERF_OFFSET;\
+	newValue &= CM_IVA_DVFS_PERF_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_IVA_DVFS_RESULT_Read32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_RESULT_OFFSET))
+
+/********************************************************************/
+
+#define CM_IVA_DVFS_CURRENT_Read32(baseAddress)\
+	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_CURRENT_OFFSET))
+
+
+/**********************************************************************/
+
+#define CM_CLKSTCTRL_ABEWriteRegister32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM1_ABE_CLKSTCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_ABE_CLKSTCTRL_Transition_MASK);\
+	newValue <<= CM1_ABE_CLKSTCTRL_Transition_OFFSET;\
+	newValue &= CM1_ABE_CLKSTCTRL_Transition_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_ABEEN_MCBSP1Write32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM1_ABE_MCBSP1_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_ABE_CLKCTRL_MASK);\
+	newValue <<= CM1_ABE_CLKCTRL_OFFSET;\
+	newValue &= CM1_ABE_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+
+#define CM_ABEEN_MCBSP2Write32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM1_ABE_MCBSP2_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_ABE_CLKCTRL_MASK);\
+	newValue <<= CM1_ABE_CLKCTRL_OFFSET;\
+	newValue &= CM1_ABE_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+
+#define CM_ABEEN_MCBSP3Write32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM1_ABE_MCBSP3_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_ABE_CLKCTRL_MASK);\
+	newValue <<= CM1_ABE_CLKCTRL_OFFSET;\
+	newValue &= CM1_ABE_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_ABEEN_TIMER5Write32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM1_ABE_TIMER5_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_ABE_CLKCTRL_MASK);\
+	newValue <<= CM1_ABE_CLKCTRL_OFFSET;\
+	newValue &= CM1_ABE_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_ABEEN_TIMER6Write32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM1_ABE_TIMER6_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_ABE_CLKCTRL_MASK);\
+	newValue <<= CM1_ABE_CLKCTRL_OFFSET;\
+	newValue &= CM1_ABE_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_ABEEN_TIMER7Write32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM1_ABE_TIMER7_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_ABE_CLKCTRL_MASK);\
+	newValue <<= CM1_ABE_CLKCTRL_OFFSET;\
+	newValue &= CM1_ABE_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_ABEEN_TIMER8Write32(baseAddress, value)\
+{\
+	const u32 offset = CM1_CM1_ABE_TIMER8_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_ABE_CLKCTRL_MASK);\
+	newValue <<= CM1_ABE_CLKCTRL_OFFSET;\
+	newValue &= CM1_ABE_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/**********************************************************************/
+
+#define CM_CLKSTCTRL_L4PERWriteRegister32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_CLKSTCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKSTCTRL_Transition_MASK);\
+	newValue <<= CM1_L4PER_CLKSTCTRL_Transition_OFFSET;\
+	newValue &= CM1_L4PER_CLKSTCTRL_Transition_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_L4PEREN_MCBSP4Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_MCBSP4_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKCTRL_MASK);\
+	newValue <<= CM1_L4PER_CLKCTRL_OFFSET;\
+	newValue &= CM1_L4PER_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_L4PEREN_MCBSP5Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_MCBSP5_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKCTRL_MASK);\
+	newValue <<= CM1_L4PER_CLKCTRL_OFFSET;\
+	newValue &= CM1_L4PER_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_L4PEREN_DMTIMER2Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKCTRL_MASK);\
+	newValue <<= CM1_L4PER_CLKCTRL_OFFSET;\
+	newValue &= CM1_L4PER_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_L4PEREN_DMTIMER3Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKCTRL_MASK);\
+	newValue <<= CM1_L4PER_CLKCTRL_OFFSET;\
+	newValue &= CM1_L4PER_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_L4PEREN_DMTIMER4Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKCTRL_MASK);\
+	newValue <<= CM1_L4PER_CLKCTRL_OFFSET;\
+	newValue &= CM1_L4PER_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_L4PEREN_DMTIMER9Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKCTRL_MASK);\
+	newValue <<= CM1_L4PER_CLKCTRL_OFFSET;\
+	newValue &= CM1_L4PER_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_L4PEREN_DMTIMER10Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKCTRL_MASK);\
+	newValue <<= CM1_L4PER_CLKCTRL_OFFSET;\
+	newValue &= CM1_L4PER_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+#define CM_L4PEREN_DMTIMER11Write32(baseAddress, value)\
+{\
+	const u32 offset = CM2_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+	register u32 newValue = ((u32)(value));\
+	data &= ~(CM1_L4PER_CLKCTRL_MASK);\
+	newValue <<= CM1_L4PER_CLKCTRL_OFFSET;\
+	newValue &= CM1_L4PER_CLKCTRL_MASK ;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+}
+
+/********************************************************************/
+
+
+#endif
 
 #endif  /* USE_LEVEL_1_MACROS */
 

drivers/dsp/bridge/hw/hw_prcm.c

@@ -29,6 +29,8 @@
 #include <hw_defs.h>
 #include <hw_prcm.h>
 
+#ifdef OMAP_3430
+
 static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
 				    enum HW_RstModule_t r,
 				    enum HW_SetClear_t val);
@@ -165,3 +167,455 @@ HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
 
 	return status;
 }
+
+#else
+static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val);
+static HW_STATUS HW_CLK_AutoIdleWriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val);
+static HW_STATUS HW_RST_WriteVal (const u32 baseAddress, enum HW_RstModule_t r, enum HW_SetClear_t val);
+
+/* ============================================================================
+* EXPORTED FUNCTIONS
+* =============================================================================
+*/
+
+HW_STATUS HW_CLK_Enable(const u32 baseAddress, enum HW_ClkModule_t c)
+{
+	return HW_CLK_WriteVal(baseAddress, c, HW_SET);
+}
+
+HW_STATUS HW_CLK_Disable(const u32 baseAddress, enum HW_ClkModule_t c)
+{
+	return HW_CLK_WriteVal(baseAddress, c, HW_CLEAR);
+}
+
+static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val)
+{
+	HW_STATUS status = RET_OK;
+	u32 val_clk = HW_CLEAR;
+
+	if (val == HW_SET)
+		val_clk = 0x2;
+
+
+	switch (c) {
+	case HW_CLK_TESLA:
+	CM_TESLA_TESLA_CLKCTRLWriteRegister32(baseAddress, val);
+	break;
+	case HW_CLK_MCBSP1:
+	CM_ABEEN_MCBSP1Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_MCBSP2:
+	CM_ABEEN_MCBSP2Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_MCBSP3:
+	CM_ABEEN_MCBSP3Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_MCBSP4:
+	CM_L4PEREN_MCBSP4Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_MCBSP5:
+	CM_L4PEREN_MCBSP5Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_TIMER5:
+	CM_ABEEN_TIMER5Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_TIMER6:
+	CM_ABEEN_TIMER6Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_TIMER7:
+	CM_ABEEN_TIMER7Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_TIMER8:
+	CM_ABEEN_TIMER8Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_DMTIMER2:
+	CM_L4PEREN_DMTIMER2Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_DMTIMER3:
+	CM_L4PEREN_DMTIMER3Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_DMTIMER4:
+	CM_L4PEREN_DMTIMER4Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_DMTIMER9:
+	CM_L4PEREN_DMTIMER9Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_DMTIMER10:
+	CM_L4PEREN_DMTIMER10Write32(baseAddress, val_clk);
+	break;
+	case HW_CLK_DMTIMER11:
+	CM_L4PEREN_DMTIMER11Write32(baseAddress, val_clk);
+	break;
+
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+
+
+HW_STATUS HW_CLK_AutoIdleEnable(const u32 baseAddress, enum HW_ClkModule_t c)
+{
+	return HW_CLK_AutoIdleWriteVal(baseAddress, c, HW_SET);
+}
+
+HW_STATUS HW_CLK_AutoIdleDisable(const u32 baseAddress, enum  HW_ClkModule_t c)
+{
+	return HW_CLK_AutoIdleWriteVal(baseAddress, c, HW_CLEAR);
+}
+
+static HW_STATUS HW_CLK_AutoIdleWriteVal(const u32 baseAddress, enum HW_ClkModule_t c,
+				enum HW_SetClear_t val)
+{
+	HW_STATUS status = RET_OK;
+
+	switch (c) {
+
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+HW_STATUS HW_CLK_StbyStatus(const u32 baseAddress, enum HW_SetClear_t *stbyState)
+{
+	HW_STATUS status = RET_OK;
+
+	*stbyState = (enum HW_SetClear_t)CM_TESLA_STBYST_Read32(baseAddress);
+
+	return status;
+}
+
+
+HW_STATUS HW_CLK_IdleStatus(const u32 baseAddress, enum HW_IdleStatus_t *idleState)
+{
+	HW_STATUS status = RET_OK;
+
+	*idleState = (enum HW_IdleStatus_t)CM_TESLA_IDLEST_Read32(baseAddress);
+
+	return status;
+}
+
+
+HW_STATUS HW_RST_Reset(const u32 baseAddress, enum HW_RstModule_t r)
+{
+	return HW_RST_WriteVal(baseAddress, r, HW_SET);
+}
+
+HW_STATUS HW_RST_UnReset(const u32 baseAddress, enum HW_RstModule_t r)
+{
+	return HW_RST_WriteVal(baseAddress, r, HW_CLEAR);
+}
+
+HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+
+	*value = PRM_TESLA_RSTCTRLReadRegister32(baseAddress);
+
+	return status;
+}
+
+static HW_STATUS HW_RST_WriteVal(const u32 baseAddress, enum HW_RstModule_t p,
+				enum HW_SetClear_t value)
+{
+	HW_STATUS status = RET_OK;
+
+	switch (p) {
+	case HW_RST1_TESLA:
+	PRM_TESLA_RSTCTRL_RST1_Write32(baseAddress, value);
+	break;
+	case HW_RST2_TESLA:
+	PRM_TESLA_RSTCTRL_RST2_Write32(baseAddress, value);
+	break;
+
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+HW_STATUS HW_RSTST_RegGet (const u32 baseAddress, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+
+	*value = PRM_TESLA_RSTSTReadRegister32(baseAddress);
+
+	return status;
+}
+
+
+HW_STATUS HW_RSTST_RegClear (const u32 baseAddress)
+{
+	HW_STATUS status = RET_OK;
+
+	PRM_TESLA_RSTST_Clear32(baseAddress);
+
+	return status;
+}
+
+
+HW_STATUS HW_PWRSTCTRL_RegGet(const u32 baseAddress, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+
+	*value = PRM_TESLA_PWRSTCTRLReadRegister32(baseAddress);
+
+	return status;
+}
+
+HW_STATUS HW_PWR_PowerStateGet(const u32 baseAddress,
+	enum HW_PwrModule_t p, enum  HW_PwrState_t *value)
+{
+	HW_STATUS status = RET_OK;
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+	*value = (enum HW_PwrState_t)PRM_TESLA_PWRSTSTGet32(baseAddress);
+	break;
+
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
+	enum HW_PwrModule_t p, enum HW_PwrState_t value)
+{
+	HW_STATUS status = RET_OK;
+
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+		switch (value) {
+		case HW_PWR_STATE_ON:
+		PRM_TESLA_PWRSTCTRLWriteON32(baseAddress);
+		break;
+		case HW_PWR_STATE_INACT:
+		PRM_TESLA_PWRSTCTRLWriteINACTIVE32(baseAddress);
+		break;
+		case HW_PWR_STATE_RET:
+		PRM_TESLA_PWRSTCTRLWriteRET32(baseAddress);
+		break;
+		case HW_PWR_STATE_OFF:
+		PRM_TESLA_PWRSTCTRLWriteOFF32(baseAddress);
+		break;
+		default:
+		status = RET_FAIL;
+		break;
+		}
+	break;
+	case HW_PWR_DOMAIN_CORE:
+		switch (value) {
+		case HW_PWR_STATE_ON:
+		case HW_PWR_STATE_INACT:
+		case HW_PWR_STATE_RET:
+		case HW_PWR_STATE_OFF:
+		PRM_CORE_PWRSTCTRLWrite32(baseAddress, value);
+		break;
+		default:
+		status = RET_FAIL;
+		break;
+		}
+	break;
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+
+HW_STATUS HW_PWR_RetentionStateSet(const u32 baseAddress,
+	enum HW_PwrModule_t p, enum  HW_RetState_t src, enum HW_SetClear_t  value)
+{
+	HW_STATUS status = RET_OK;
+
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+		switch (src) {
+		case HW_RETSTATE_LOGIC:
+		PRM_TESLA_PWRSTCTRLWriteLOGICRETSTATE32(baseAddress, value);
+		break;
+		case HW_RETSTATE_L1:
+		PRM_TESLA_PWRSTCTRLWriteL1RETSTATE32(baseAddress, value);
+		break;
+		case HW_RETSTATE_L2:
+		PRM_TESLA_PWRSTCTRLWriteL2RETSTATE32(baseAddress, value);
+		break;
+		default:
+		status = RET_FAIL;
+		break;
+		}
+	break;
+
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+
+HW_STATUS HW_PWRST_RegGet(const u32 baseAddress, enum HW_PwrModule_t p, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+	*value = PRM_TESLA_PWRSTSTReadRegister32(baseAddress);
+	break;
+
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+HW_STATUS HW_PWR_WkupDependency_RegGet(const u32 baseAddress, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+
+	*value = PRM_WKUP_IVA_ReadRegister32(baseAddress);
+
+	return status;
+}
+
+HW_STATUS HW_PWR_WkupDependencySet(const u32 baseAddress, enum HW_PwrModule_t p,
+	enum HW_WeakUpDep_t src, enum HW_SetClear_t value)
+{
+	HW_STATUS status = RET_OK;
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+		switch (src) {
+		case HW_WKUP_IVA_MPU:
+		PRM_WKUP_IVA_MPU_Write32(baseAddress, value);
+		break;
+		case HW_WKUP_IVA_DUCATI:
+		PRM_WKUP_IVA_DUCATI_Write32(baseAddress, value);
+		break;
+		default:
+		status = RET_FAIL;
+		break;
+		}
+	break;
+
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+HW_STATUS HW_PWR_ForceStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
+	enum HW_PWR_TransState_t value)
+{
+	HW_STATUS status = RET_OK;
+
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+	CM_CLKSTCTRL_TESLAWriteRegister32(baseAddress, value);
+	break;
+	case HW_PWR_DOMAIN_ABE:
+	CM_CLKSTCTRL_ABEWriteRegister32(baseAddress, value);
+	break;
+	case HW_PWR_DOMAIN_L4PER:
+	CM_CLKSTCTRL_L4PERWriteRegister32(baseAddress, value);
+	break;
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+
+HW_STATUS HW_TESLA_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+
+	*value = PRM_TESLA_CONTEXTReadRegister32(baseAddress);
+
+	return status;
+}
+
+HW_STATUS HW_TESLA_CONTEXT_ClrSet(const u32 baseAddress)
+{
+	HW_STATUS status = RET_OK;
+
+	PRM_TESLA_CONTEXT_Clear32(baseAddress);
+
+	return status;
+}
+
+
+HW_STATUS HW_ALWON_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+
+	*value = PRM_ALWON_CONTEXTReadRegister32(baseAddress);
+
+	return status;
+}
+
+
+HW_STATUS HW_IVA_DVFSSet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 value)
+{
+	HW_STATUS status = RET_OK;
+	switch (src) {
+	case HW_DVFS_PERF_TESLA:
+	CM_IVA_DVFS_PERFTESTLA_Write32(baseAddress, value);
+	break;
+	case HW_DVFS_PERF_IVAHD:
+	CM_IVA_DVFS_PERFIVAHD_Write32(baseAddress, value);
+	break;
+	case HW_DVFS_PERF_ABE:
+	CM_IVA_DVFS_PERFABE_Write32(baseAddress, value);
+	break;
+	default:
+	status = RET_FAIL;
+	break;
+	}
+	return status;
+}
+
+HW_STATUS HW_IVA_DVFS_RegGet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+	switch (src) {
+	case HW_DVFS_PERF_TESLA:
+	*value = CM_IVA_DVFS_PERFTESTLA_Read32(baseAddress);
+	break;
+	case HW_DVFS_PERF_IVAHD:
+	*value = CM_IVA_DVFS_PERFIVAHD_Read32(baseAddress);
+	break;
+	case HW_DVFS_PERF_ABE:
+	*value = CM_IVA_DVFS_PERFABE_Read32(baseAddress);
+	break;
+	case HW_DVFS_RESULT:
+	*value = CM_IVA_DVFS_RESULT_Read32(baseAddress);
+	break;
+	case HW_DVFS_CURRENT:
+	*value = CM_IVA_DVFS_CURRENT_Read32(baseAddress);
+	break;
+	default:
+	status = RET_FAIL;
+	break;
+	}
+	return status;
+
+}
+#endif

drivers/dsp/bridge/hw/hw_prcm.h

@@ -29,6 +29,7 @@
 
 /* HW_ClkModule:  Enumerated Type used to specify the clock domain */
 
+#ifdef OMAP_3430
 enum HW_ClkModule_t {
 /* DSP Domain */
     HW_CLK_DSP_CPU,
@@ -165,5 +166,181 @@ extern HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
 
 extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
 					     enum HW_TransitionState_t val);
+#else
+enum HW_ClkModule_t {
+
+/*CM1 ABE*/
+	HW_CLK_TESLA,
+	HW_CLK_AESS,
+	HW_CLK_PDM,
+	HW_CLK_DMIC,
+	HW_CLK_MCASP,
+	HW_CLK_MCBSP1,
+	HW_CLK_MCBSP2,
+	HW_CLK_MCBSP3,
+	HW_CLK_SLIMBUS,
+	HW_CLK_TIMER5,
+	HW_CLK_TIMER6,
+	HW_CLK_TIMER7,
+	HW_CLK_TIMER8,
+	HW_CLK_WDT3,
+
+/*CM2 L4PER*/
+
+	HW_CLK_DMTIMER2,
+	HW_CLK_DMTIMER3,
+	HW_CLK_DMTIMER4,
+	HW_CLK_DMTIMER9,
+	HW_CLK_DMTIMER10,
+	HW_CLK_DMTIMER11,
+	HW_CLK_MCBSP4,
+	HW_CLK_MCBSP5,
+
+
+};
+
+
+
+/* ----------------------------------------------------------------------------
+* TYPE:         HW_RstModule
+*
+* DESCRIPTION:  Enumerated Type used to specify the module to be reset
+*
+* -----------------------------------------------------------------------------
+*/
+enum HW_RstModule_t {
+	HW_RST1_TESLA,  /*Reset the DSP*/
+	HW_RST2_TESLA,  /* Reset MMU */
+};
+
+
+
+/* ----------------------------------------------------------------------------
+* TYPE:         HW_PwrModule
+*
+* DESCRIPTION:  Enumerated Type used to specify the power domain
+*
+* -----------------------------------------------------------------------------
+*/
+
+enum HW_PwrModule_t {
+/* Domains*/
+	HW_PWR_DOMAIN_CORE,
+	HW_PWR_DOMAIN_MPU,
+	HW_PWR_DOMAIN_WAKEUP,
+	HW_PWR_DOMAIN_TESLA,
+	HW_PWR_DOMAIN_ABE,
+	HW_PWR_DOMAIN_L4PER,
+/* Sub-domains */
+	HW_PWR_DSP_IPI,        /* IPI = Intrusive Port Interface */
+	HW_PWR_IVA_ISP         /* ISP = Intrusive Slave Port*/
+} ;
+
+
+enum HW_PwrState_t {
+	HW_PWR_STATE_OFF,
+	HW_PWR_STATE_RET,
+	HW_PWR_STATE_INACT,
+	HW_PWR_STATE_ON = 3
+};
+
+enum HW_RetState_t {
+	HW_RETSTATE_LOGIC,
+	HW_RETSTATE_L1,
+	HW_RETSTATE_L2
+};
+
+enum HW_WeakUpDep_t {
+	HW_WKUP_IVA_MPU,
+	HW_WKUP_IVA_DUCATI
+};
+
+enum HW_IvaDVFS_t {
+	HW_DVFS_PERF_TESLA,
+	HW_DVFS_PERF_IVAHD,
+	HW_DVFS_PERF_ABE,
+	HW_DVFS_RESULT,
+	HW_DVFS_CURRENT
+};
+
+enum HW_PWR_TransState_t {
+	HW_AUTOTRANS_DIS = 0x0,
+	HW_SW_SUP_SLEEP,
+	HW_SW_SUP_WAKEUP,
+	HW_AUTOTRANS_EN
+};
+
+enum HW_IdleStatus_t {
+	HW_TESLA_FULLFUNC = 0x0, /* Module is fully functional, including OCP*/
+	HW_TESLA_TRANSITIONING, /* Transitioning (weakup, sleep or sleep abortion)*/
+	HW_TESLA_IDLE,/* Idle mode(only OCP)*/
+	HW_TESLA_DISABLED/*Module is disabled and cannot be accessed*/
+};
+
+
+extern HW_STATUS HW_CLK_Enable(const u32 baseAddress,
+				enum HW_ClkModule_t c);
+
+extern HW_STATUS HW_CLK_Disable(const u32 baseAddress,
+				enum HW_ClkModule_t c);
+
+extern HW_STATUS HW_CLK_AutoIdleEnable(const u32 baseAddress,
+				enum HW_ClkModule_t c);
+
+extern HW_STATUS HW_CLK_AutoIdleDisable(const u32 baseAddress,
+				enum HW_ClkModule_t c);
+
+extern HW_STATUS HW_CLK_StbyStatus(const u32 baseAddress,  enum HW_SetClear_t *stbyState);
+
+extern HW_STATUS HW_CLK_IdleStatus(const u32 baseAddress,  enum HW_IdleStatus_t *idleState);
+
+extern HW_STATUS HW_RST_Reset(const u32 baseAddress,
+				enum HW_RstModule_t r);
+
+extern HW_STATUS HW_RST_UnReset (const u32 baseAddress,
+				enum HW_RstModule_t r);
+
+extern HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, u32 *value);
+
+extern HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, u32 *value);
+
+extern HW_STATUS HW_RSTST_RegClear(const u32 baseAddress);
+
+extern HW_STATUS HW_PWRSTCTRL_RegGet(const u32 baseAddress, u32 *value);
+
+extern HW_STATUS HW_PWR_PowerStateGet(const u32 baseAddress,
+				enum HW_PwrModule_t p, enum HW_PwrState_t *value);
+
+extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
+				enum HW_PwrState_t value);
+
+extern HW_STATUS HW_PWR_RetentionStateSet(const u32 baseAddress,
+				enum HW_PwrModule_t p, enum HW_RetState_t src, enum HW_SetClear_t  value);
+
+extern HW_STATUS HW_PWRST_RegGet(const u32 baseAddress, enum HW_PwrModule_t p, u32 *value);
+
+extern HW_STATUS HW_PWR_WkupDependency_RegGet(const u32 baseAddress, u32 *value);
+
+extern HW_STATUS HW_PWR_WkupDependencySet(const u32 baseAddress, enum HW_PwrModule_t p,
+				enum HW_WeakUpDep_t src, enum HW_SetClear_t value);
+
+extern HW_STATUS HW_PWR_ForceStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
+				enum HW_PWR_TransState_t value);
+
+extern HW_STATUS HW_TESLA_RST_WriteVal(const u32 baseAddress, enum HW_RstModule_t p,
+				enum HW_SetClear_t value);
+
+extern HW_STATUS HW_TESLA_CONTEXT_RegGet(const u32 baseAddress, u32 *value);
+
+extern HW_STATUS HW_TESLA_CONTEXT_ClrSet(const u32 baseAddress);
+
+extern HW_STATUS HW_ALWON_CONTEXT_RegGet(const u32 baseAddress, u32 *value);
+
+extern HW_STATUS HW_IVA_DVFSSet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 value);
+
+extern HW_STATUS HW_IVA_DVFS_RegGet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 *value);
+
+
+#endif
 
 #endif  /* __HW_PRCM_H */

drivers/dsp/bridge/pmgr/dbll.c

@@ -1190,11 +1190,34 @@ static struct dynload_symbol *addToSymbolTable(struct Dynamic_Loader_Sym *this,
 		pSym = findSymbol(this, name);
 		bGblSearch = true;
 		if (pSym) {
+
+	#ifdef OMAP44XX
+	#define SQ_IGNORE_SYMBOLS 1
+	#endif
+	#if !SQ_IGNORE_SYMBOLS
+
 			bRedefinedSymbol = true;
 			GT_1trace(DBLL_debugMask, GT_6CLASS,
 				 "Symbol already defined in "
 				 "symbol table: %s\n", name);
 			return NULL;
+	#else
+		                        if ((strcmp(name, "___ASM__") == 0)
+                                || (strcmp(name, "___TARG__") == 0)
+                                || (strcmp(name, "___PLAT__") == 0)
+                                || (strcmp(name, "___ISA__") == 0)
+								|| (strcmp(name, "___TRDR__") == 0))
+                                retVal = findSymbol(this, name);
+                        else {
+                                bRedefinedSymbol = true;
+                                GT_1trace(DBLL_debugMask, GT_6CLASS,
+                                         "Symbol already defined in "
+                                         "symbol table: %s\n", name);
+                                return NULL;
+                        }
+	#endif
+
+
 		}
 	}
 	/* Allocate string to copy symbol name */

drivers/dsp/bridge/rmgr/drv.c

@@ -1654,8 +1654,16 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
 
 			if (pResources->dwPrmBase)
 				iounmap(pResources->dwPrmBase);
+#ifdef OMAP_3430
 			if (pResources->dwCmBase)
-				iounmap(pResources->dwCmBase);
+				iounmap((void *)pResources->dwCmBase);
+#endif
+#ifdef OMAP_44XX
+			if (pResources->dwCm1Base)
+				iounmap((void *)pResources->dwCm1Base);
+			if (pResources->dwCm2Base)
+				iounmap((void *)pResources->dwCm2Base);
+#endif
 			if (pResources->dwMboxBase)
 				iounmap(pResources->dwMboxBase);
 			if (pResources->dwMemBase[0])
@@ -1682,7 +1690,13 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
 				 * as it is used in BOARD_Stop */
 			}
 			pResources->dwPrmBase = NULL;
+#ifdef OMAP_3430
 			pResources->dwCmBase = NULL;
+#endif
+#ifdef OMAP_44XX
+			pResources->dwCm1Base = (u32) NULL;
+			pResources->dwCm2Base = (u32) NULL;
+#endif
 			pResources->dwMboxBase = NULL;
 			pResources->dwMemBase[0] = (u32) NULL;
 			pResources->dwMemBase[2] = (u32) NULL;
@@ -1710,8 +1724,17 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
 
 		pResources->dwPrmBase = ioremap(OMAP_IVA2_PRM_BASE,
 							OMAP_IVA2_PRM_SIZE);
-		pResources->dwCmBase = ioremap(OMAP_IVA2_CM_BASE,
-							OMAP_IVA2_CM_SIZE);
+
+#ifdef OMAP44XX
+                pResources->dwCm1Base = (u32)ioremap(OMAP_IVA2_CM1_BASE,
+                                                        OMAP_IVA2_CM1_SIZE);
+                pResources->dwCm2Base = (u32)ioremap(OMAP_IVA2_CM2_BASE,
+                                                        OMAP_IVA2_CM2_SIZE);
+#else
+				pResources->dwCmBase = ioremap(OMAP_IVA2_CM_BASE,
+													OMAP_IVA2_CM_SIZE);
+#endif
+
 		pResources->dwMboxBase = ioremap(OMAP_MBOX_BASE,
 							OMAP_MBOX_SIZE);
 		pResources->dwSysCtrlBase = ioremap(OMAP_SYSC_BASE,
@@ -1722,8 +1745,15 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
 			 pResources->dwMemBase[3]);
 		GT_1trace(curTrace, GT_2CLASS, "dwPrmBase 0x%x\n",
 							pResources->dwPrmBase);
+#ifdef OMAP44XX
+		GT_1trace(curTrace, GT_2CLASS, "dwCm1Base 0x%x\n",
+							pResources->dwCm1Base);
+		GT_1trace(curTrace, GT_2CLASS, "dwCm2Base 0x%x\n",
+							pResources->dwCm2Base);
+#else
 		GT_1trace(curTrace, GT_2CLASS, "dwCmBase 0x%x\n",
 							pResources->dwCmBase);
+#endif
 		GT_1trace(curTrace, GT_2CLASS, "dwWdTimerDspBase 0x%x\n",
 						pResources->dwWdTimerDspBase);
 		GT_1trace(curTrace, GT_2CLASS, "dwMboxBase 0x%x\n",
@@ -1806,12 +1836,20 @@ static DSP_STATUS RequestBridgeResourcesDSP(u32 dwContext, s32 bRequest)
 							OMAP_DSP_MEM2_SIZE);
 		pResources->dwMemBase[4] = (u32)ioremap(OMAP_DSP_MEM3_BASE,
 							OMAP_DSP_MEM3_SIZE);
+#ifdef OMAP_3430
 		pResources->dwPerBase = ioremap(OMAP_PER_CM_BASE,
 							OMAP_PER_CM_SIZE);
-               pResources->dwPerPmBase = (u32)ioremap(OMAP_PER_PRM_BASE,
-                                                       OMAP_PER_PRM_SIZE);
-               pResources->dwCorePmBase = (u32)ioremap(OMAP_CORE_PRM_BASE,
+        pResources->dwPerPmBase = (u32)ioremap(OMAP_PER_PRM_BASE,
+                                                     OMAP_PER_PRM_SIZE);
+        pResources->dwCorePmBase = (u32)ioremap(OMAP_CORE_PRM_BASE,
                                                        OMAP_CORE_PRM_SIZE);
+#else
+
+        pResources->dwCm1Base = (u32)ioremap(OMAP_IVA2_CM1_BASE,
+                            OMAP_IVA2_CM1_SIZE);
+        pResources->dwCm2Base = (u32)ioremap(OMAP_IVA2_CM2_BASE,
+                            OMAP_IVA2_CM2_SIZE);
+#endif
 		pResources->dwDmmuBase = ioremap(OMAP_DMMU_BASE,
 							OMAP_DMMU_SIZE);
 		pResources->dwWdTimerDspBase = NULL;
@@ -1828,8 +1866,15 @@ static DSP_STATUS RequestBridgeResourcesDSP(u32 dwContext, s32 bRequest)
 						pResources->dwMemBase[4]);
 		GT_1trace(curTrace, GT_2CLASS, "dwPrmBase 0x%x\n",
 						pResources->dwPrmBase);
+#ifdef OMAP44XX
+		GT_1trace(curTrace, GT_2CLASS, "dwCm1Base 0x%x\n",
+							pResources->dwCm1Base);
+		GT_1trace(curTrace, GT_2CLASS, "dwCm2Base 0x%x\n",
+							pResources->dwCm2Base);
+#else
 		GT_1trace(curTrace, GT_2CLASS, "dwCmBase 0x%x\n",
 						pResources->dwCmBase);
+#endif
 		GT_1trace(curTrace, GT_2CLASS, "dwWdTimerDspBase 0x%x\n",
 						pResources->dwWdTimerDspBase);
 		GT_1trace(curTrace, GT_2CLASS, "dwMboxBase 0x%x\n",

drivers/dsp/bridge/rmgr/drv_interface.c

@@ -110,7 +110,12 @@
 #define DRIVER_NAME  "DspBridge"
 #define DRIVER_MAJOR 0		/* Linux assigns our Major device number */
 #define DRIVER_MINOR 0		/* Linux assigns our Major device number */
+
+#ifdef OMAP44XX
+s32 dsp_debug = 1;
+#else
 s32 dsp_debug;
+#endif
 
 struct platform_device *omap_dspbridge_dev;
 

drivers/dsp/bridge/rmgr/proc.c

@@ -161,7 +161,17 @@
 #define PWR_TIMEOUT	 500	/* Sleep/wake timout in msec */
 #define EXTEND	      "_EXT_END"	/* Extmem end addr in DSP binary */
 
+#ifdef OMAP44XX
+/* Start address of memory for dynamic mapping */
+const u32 DEXTMEMMAP_BEG   = 0x30000000 ;
+
+/* End address of memory for dynamic mapping */
+
+const u32 DEXTMEMMAP_END   = 0x40000000 ;
+#endif
+
 extern char *iva_img;
+
 /* The PROC_OBJECT structure.   */
 struct PROC_OBJECT {
 	struct LST_ELEM link;		/* Link to next PROC_OBJECT */
@@ -193,6 +203,15 @@ static u32 cRefs;
 
 struct SYNC_CSOBJECT *hProcLock;	/* For critical sections */
 
+#ifndef CONFIG_DISABLE_BRIDGE_PM
+#ifndef CONFIG_DISABLE_BRIDGE_DVFS
+#ifdef                  status = DSP_EFAILo CONFIG_OMAP3_PM
+extern struct constraint_handle *mpu_constraint_handle;
+#endif
+#endif
+#endif
+
+
 /*  ----------------------------------- Function Prototypes */
 static DSP_STATUS PROC_Monitor(struct PROC_OBJECT *hProcessor);
 static s32 GetEnvpCount(char **envp);
@@ -1075,8 +1094,16 @@ DSP_STATUS PROC_Load(DSP_HPROCESSOR hProcessor, IN CONST s32 iArgc,
 	s32 nProcID = 0;	/* Anticipate MP version. */
 	struct DCD_MANAGER *hDCDHandle;
 	struct DMM_OBJECT *hDmmMgr;
+
+#ifdef OMAP_3430
 	u32 dwExtEnd;
+#endif
 	u32 uProcId;
+
+#ifdef OMAP44XX
+        u32     dwDmmStart;
+#endif
+
 #ifdef DEBUG
 	BRD_STATUS uBrdState;
 #endif
@@ -1090,6 +1117,7 @@ DSP_STATUS PROC_Load(DSP_HPROCESSOR hProcessor, IN CONST s32 iArgc,
 #ifdef OPT_LOAD_TIME_INSTRUMENTATION
 	do_gettimeofday(&tv1);
 #endif
+
 #if defined(CONFIG_BRIDGE_DVFS) && !defined(CONFIG_CPU_FREQ)
 	struct dspbridge_platform_data *pdata =
 				omap_dspbridge_dev->dev.platform_data;
@@ -1313,6 +1341,7 @@ DSP_STATUS PROC_Load(DSP_HPROCESSOR hProcessor, IN CONST s32 iArgc,
 			/* Use all available DSP address space after EXTMEM
 			 * for DMM */
 			if (DSP_SUCCEEDED(status)) {
+#ifdef OMAP_3430
 				status = COD_GetSymValue(hCodMgr, EXTEND,
 								&dwExtEnd);
 				if (DSP_FAILED(status)) {
@@ -1321,18 +1350,30 @@ DSP_STATUS PROC_Load(DSP_HPROCESSOR hProcessor, IN CONST s32 iArgc,
 						 "COD_GetSymValue %s.\n",
 						 EXTEND);
 				}
+#endif
 			}
 			/* Reset DMM structs and add an initial free chunk*/
 			if (DSP_SUCCEEDED(status)) {
 				status = DEV_GetDmmMgr(pProcObject->hDevObject,
 						      &hDmmMgr);
 				if (DSP_SUCCEEDED(status)) {
+#ifdef OMAP_3430
 					/* Set dwExtEnd to DMM START u8
 					  * address */
 					dwExtEnd = (dwExtEnd + 1) * DSPWORDSIZE;
 					 /* DMM memory is from EXT_END */
 					status = DMM_CreateTables(hDmmMgr,
-						dwExtEnd, DMMPOOLSIZE);
+					dwExtEnd, DMMPOOLSIZE);
+#else
+					dwDmmStart = (DEXTMEMMAP_BEG) * (DSPWORDSIZE);
+
+                    status = DMM_CreateTables(hDmmMgr,dwDmmStart,
+											 DMMPOOLSIZE);
+#endif
+		
+
+
+
 				}
 			}
 		}

drivers/dsp/bridge/services/services.c

@@ -85,7 +85,9 @@ void SERVICES_Exit(void)
 		NTFY_Exit();
 		UTIL_Exit();
 		SYNC_Exit();
+#ifdef OMAP_3430
 		CLK_Exit();
+#endif
 		REG_Exit();
 		LST_Exit();
 		KFILE_Exit();
@@ -133,12 +135,18 @@ bool SERVICES_Init(void)
 		fLST = LST_Init();
 		/* fREG = REG_Init(); */
 		fSYNC = SYNC_Init();
+#ifdef OMAP_3430
 		fCLK  = CLK_Init();
+#endif
 		fUTIL = UTIL_Init();
 		fNTFY = NTFY_Init();
 
                fInit = fCFG && fCSL && fDBG && fDPC && fKFILE &&
+#ifdef OMAP_3430
                        fLST && fMEM && fREG && fSYNC && fCLK && fUTIL;
+#else
+                       fLST && fMEM && fREG && fSYNC && fUTIL;
+#endif
 
 		if (!fInit) {
 			if (fNTFY)
@@ -150,8 +158,10 @@ bool SERVICES_Init(void)
 			if (fSYNC)
 				SYNC_Exit();
 
+#ifdef OMAP_3430
 			if (fCLK)
 				CLK_Exit();
+#endif
 
 			if (fREG)
 				REG_Exit();

drivers/dsp/bridge/wmd/_tiomap.h

@@ -19,6 +19,28 @@
  *  Description:
  *      Definitions and types private to this WMD.
  *
+ *! Revision History
+ *! ================
+ *! 12-Apr-2004 hp:  Removed the L4 entry of Dsp DMA , not needed
+ *! 08-Mar-2004 sb:  Added the Dynamic Memory Mapping feature - PgTableAttrs
+ *! 21-Mar-2003 sb:  Added numTLBEntries to struct WMD_DEV_CONTEXT
+ *! 20-Feb-2003 vp:  Ported to Linux platform.
+ *! 30-Jul-2002 rr:  Modified TBC_ID_VALUE to 0xb47002f.
+ *! 10-May-2002 sg:  Added ARM_SYSST_OFFSET and IDLE_DSP_MASK.
+ *! 14-Mar-2002 rr:  Added Boot vector field to pDevContext.
+ *!                  Added TBC Register defines and value for OMAP1510.
+ *! 12-Jan-2002 ag:  wIntrVal2Dsp Added.
+ *! 05-Nov-2001 kc:  Added MMU fault related definitions.
+ *! 03-Aug-2001 ag   Added TLB table for OEM cofig of DSP-MMU.
+ *! 23-Aug-2001 rr:  Added API_SIZE define.
+ *! 16-Aug-2001 rr:  Added dwDspExtBaseAddr to access the Ext memory.
+ *! 24-Jul-2001 ag:  Added Internal SRAM MMU table entry.
+ *! 27-Jun-2001 rr:  Name changed to _tihelen.h.
+ *! 27-Jun-2001 ag:  Added dwIntAddr in WMD_DEV_CONTEXT used for MB INTRs msk.
+ *! 07-May-2001 ag:  Added DSP Clock Module CLKM2.
+ *!                  Added TIHEL_SDRAMPHYSBASE used for DSP MMU init.
+ *!                  Added ClearBit() MACRO.
+ *! 18-Jan-2001 rr:  Created
  */
 
 #ifndef _TIOMAP_
@@ -34,6 +56,7 @@
 struct MAP_L4PERIPHERAL {
 	u32 physAddr;
 	u32 dspVirtAddr;
+	u32 ulSize;
 } ;
 
 #define ARM_MAILBOX_START               0xfffcf000
@@ -58,132 +81,142 @@ struct MAP_L4PERIPHERAL {
 
 #define MAX_LOCK_TLB_ENTRIES 15
 
-#define L4_PERIPHERAL_PRM        0x48306000  /*PRM L4 Peripheral */
-#define DSPVA_PERIPHERAL_PRM     0x1181e000
-#define L4_PERIPHERAL_SCM        0x48002000  /*SCM L4 Peripheral */
-#define DSPVA_PERIPHERAL_SCM     0x1181f000
-#define L4_PERIPHERAL_MMU        0x5D000000  /*MMU L4 Peripheral */
-#define DSPVA_PERIPHERAL_MMU     0x11820000
-#define L4_PERIPHERAL_CM        0x48004000       /* Core L4, Clock Management */
-#define DSPVA_PERIPHERAL_CM     0x1181c000
-#define L4_PERIPHERAL_PER        0x48005000       /*  PER */
-#define DSPVA_PERIPHERAL_PER     0x1181d000
-
-#define L4_PERIPHERAL_GPIO1       0x48310000
-#define DSPVA_PERIPHERAL_GPIO1    0x11809000
-#define L4_PERIPHERAL_GPIO2       0x49050000
-#define DSPVA_PERIPHERAL_GPIO2    0x1180a000
-#define L4_PERIPHERAL_GPIO3       0x49052000
-#define DSPVA_PERIPHERAL_GPIO3    0x1180b000
-#define L4_PERIPHERAL_GPIO4       0x49054000
-#define DSPVA_PERIPHERAL_GPIO4    0x1180c000
-#define L4_PERIPHERAL_GPIO5       0x49056000
-#define DSPVA_PERIPHERAL_GPIO5    0x1180d000
-
-#define L4_PERIPHERAL_IVA2WDT      0x49030000
-#define DSPVA_PERIPHERAL_IVA2WDT   0x1180e000
-
-#define L4_PERIPHERAL_DISPLAY     0x48050000
-#define DSPVA_PERIPHERAL_DISPLAY  0x1180f000
-
-#define L4_PERIPHERAL_SSI         0x48058000
-#define DSPVA_PERIPHERAL_SSI      0x11804000
-#define L4_PERIPHERAL_GDD         0x48059000
-#define DSPVA_PERIPHERAL_GDD      0x11805000
-#define L4_PERIPHERAL_SS1         0x4805a000
-#define DSPVA_PERIPHERAL_SS1      0x11806000
-#define L4_PERIPHERAL_SS2         0x4805b000
-#define DSPVA_PERIPHERAL_SS2      0x11807000
-
-#define L4_PERIPHERAL_CAMERA      0x480BC000
-#define DSPVA_PERIPHERAL_CAMERA   0x11819000
-
-#define L4_PERIPHERAL_SDMA        0x48056000
-#define DSPVA_PERIPHERAL_SDMA     0x11810000 /*0x1181d000 conflicts with PER */
-
-#define L4_PERIPHERAL_UART1             0x4806a000
-#define DSPVA_PERIPHERAL_UART1          0x11811000
-#define L4_PERIPHERAL_UART2             0x4806c000
-#define DSPVA_PERIPHERAL_UART2          0x11812000
-#define L4_PERIPHERAL_UART3             0x49020000
-#define DSPVA_PERIPHERAL_UART3    0x11813000
-
-#define L4_PERIPHERAL_MCBSP1      0x48074000
-#define DSPVA_PERIPHERAL_MCBSP1   0x11814000
-#define L4_PERIPHERAL_MCBSP2      0x49022000
-#define DSPVA_PERIPHERAL_MCBSP2   0x11815000
-#define L4_PERIPHERAL_MCBSP3      0x49024000
-#define DSPVA_PERIPHERAL_MCBSP3   0x11816000
-#define L4_PERIPHERAL_MCBSP4      0x49026000
-#define DSPVA_PERIPHERAL_MCBSP4   0x11817000
-#define L4_PERIPHERAL_MCBSP5      0x48096000
-#define DSPVA_PERIPHERAL_MCBSP5   0x11818000
-
-#define L4_PERIPHERAL_GPTIMER5    0x49038000
-#define DSPVA_PERIPHERAL_GPTIMER5 0x11800000
-#define L4_PERIPHERAL_GPTIMER6    0x4903a000
-#define DSPVA_PERIPHERAL_GPTIMER6 0x11801000
-#define L4_PERIPHERAL_GPTIMER7    0x4903c000
-#define DSPVA_PERIPHERAL_GPTIMER7 0x11802000
-#define L4_PERIPHERAL_GPTIMER8    0x4903e000
-#define DSPVA_PERIPHERAL_GPTIMER8 0x11803000
-
-#define L4_PERIPHERAL_SPI1      0x48098000
-#define DSPVA_PERIPHERAL_SPI1   0x1181a000
-#define L4_PERIPHERAL_SPI2      0x4809a000
-#define DSPVA_PERIPHERAL_SPI2   0x1181b000
-
-#define L4_PERIPHERAL_MBOX        0x48094000
-#define DSPVA_PERIPHERAL_MBOX     0x11808000
-
-#define PM_GRPSEL_BASE 			0x48307000
-#define DSPVA_GRPSEL_BASE 		0x11821000
-
-#define L4_PERIPHERAL_SIDETONE_MCBSP2        0x49028000
-#define DSPVA_PERIPHERAL_SIDETONE_MCBSP2 0x11824000
-#define L4_PERIPHERAL_SIDETONE_MCBSP3        0x4902a000
-#define DSPVA_PERIPHERAL_SIDETONE_MCBSP3 0x11825000
-
-/* define a static array with L4 mappings */
+#define L4_PERIPHERAL_UART3                      0x48020000
+#define DSPVA_PERIPHERAL_UART3                  L4_PERIPHERAL_UART3
+
+#define L4_PERIPHERAL_GPIO2                      0x48055000
+#define DSPVA_PERIPHERAL_GPIO2                   L4_PERIPHERAL_GPIO2
+#define L4_PERIPHERAL_GPIO3                      0x48057000
+#define DSPVA_PERIPHERAL_GPIO3                   L4_PERIPHERAL_GPIO3
+#define L4_PERIPHERAL_GPIO4                      0x48059000
+#define DSPVA_PERIPHERAL_GPIO4                   L4_PERIPHERAL_GPIO4
+#define L4_PERIPHERAL_GPIO5                      0x4805B000
+#define DSPVA_PERIPHERAL_GPIO5                   L4_PERIPHERAL_GPIO5
+
+#define L4_PERIPHERAL_GPTIMER5                   0x49038000
+#define DSPVA_PERIPHERAL_GPTIMER5                L4_PERIPHERAL_GPTIMER5
+#define L4_PERIPHERAL_GPTIMER6                   0x4903A000
+#define DSPVA_PERIPHERAL_GPTIMER6                L4_PERIPHERAL_GPTIMER6
+#define L4_PERIPHERAL_GPTIMER7                   0x4903C000
+#define DSPVA_PERIPHERAL_GPTIMER7                L4_PERIPHERAL_GPTIMER7
+#define L4_PERIPHERAL_GPTIMER8                   0x4903E000
+#define DSPVA_PERIPHERAL_GPTIMER8                L4_PERIPHERAL_GPTIMER8
+
+#define L4_PERIPHERAL_UART1                      0x4806A000
+#define DSPVA_PERIPHERAL_UART1                   L4_PERIPHERAL_UART1
+#define L4_PERIPHERAL_UART2                      0x4806C000
+#define DSPVA_PERIPHERAL_UART2                   L4_PERIPHERAL_UART2
+#define L4_PERIPHERAL_UART4                      0x4806E000
+#define DSPVA_PERIPHERAL_UART4                   L4_PERIPHERAL_UART4
+
+#define L4_PERIPHERAL_MCBSP4                     0x48074000
+#define DSPVA_PERIPHERAL_MCBSP4                  L4_PERIPHERAL_MCBSP4
+#define L4_PERIPHERAL_MCBSP5                     0x48096000
+#define DSPVA_PERIPHERAL_MCBSP5                  L4_PERIPHERAL_MCBSP5
+
+#define L4_PERIPHERAL_MCSPI1                     0x48098000
+#define DSPVA_PERIPHERAL_MCSPI1                  L4_PERIPHERAL_MCSPI1
+#define L4_PERIPHERAL_MCSPI2                     0x4809A000
+#define DSPVA_PERIPHERAL_MCSPI2                  L4_PERIPHERAL_MCSPI2
+
+#define L4_PERIPHERAL_MCBSP1                     0x49022000
+#define DSPVA_PERIPHERAL_MCBSP1                  L4_PERIPHERAL_MCBSP1
+#define L4_PERIPHERAL_MCBSP2                     0x49024000
+#define DSPVA_PERIPHERAL_MCBSP2                  L4_PERIPHERAL_MCBSP2
+#define L4_PERIPHERAL_MCBSP3                     0x49028000
+#define DSPVA_PERIPHERAL_MCBSP3                  L4_PERIPHERAL_MCBSP3
+
+#define L4_PERIPHERAL_WDT3                       0x49030000
+#define DSPVA_PERIPHERAL_WDT3                    L4_PERIPHERAL_WDT3
+
+#define L4_PERIPHERAL_MBOX                       0x4A0F4000
+#define DSPVA_PERIPHERAL_MBOX                    L4_PERIPHERAL_MBOX
+
+
+#define L4_PERIPHERAL_CM1                        0x4A004000
+#define DSPVA_PERIPHERAL_CM1                     L4_PERIPHERAL_CM1
+#define L4_PERIPHERAL_CM2_P1                     0x4A008000 /*(4Kb)*/
+#define DSPVA_PERIPHERAL_CM2_P1                  L4_PERIPHERAL_CM2_P1
+#define L4_PERIPHERAL_CM2_P2                     0x4A009000 /*(4Kb)*/
+#define DSPVA_PERIPHERAL_CM2_P2                  L4_PERIPHERAL_CM2_P2
+
+
+#define L4_PERIPHERAL_PRM_P1                     0x4A306000 /*(4Kb)*/
+#define DSPVA_PERIPHERAL_PRM_P1			 L4_PERIPHERAL_PRM_P1
+#define L4_PERIPHERAL_PRM_P2                     0x4A307000 /*(4Kb)*/
+#define DSPVA_PERIPHERAL_PRM_P2			 L4_PERIPHERAL_PRM_P2
+
+
+
+#define L4_PERIPHERAL_SCRM                       0x4A30A000
+#define DSPVA_PERIPHERAL_SCRM                    L4_PERIPHERAL_SCRM
+
+#define L4_PERIPHERAL_GPIO1                      0x4A310000
+#define DSPVA_PERIPHERAL_GPIO1                   L4_PERIPHERAL_GPIO1
+
+#define NOTIFY_TESLA_EVENTNUMBER 0x00000000
+
 static const struct MAP_L4PERIPHERAL L4PeripheralTable[] = {
-	{L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX},
-	{L4_PERIPHERAL_SCM, DSPVA_PERIPHERAL_SCM},
-	{L4_PERIPHERAL_MMU, DSPVA_PERIPHERAL_MMU},
-	{L4_PERIPHERAL_GPTIMER5, DSPVA_PERIPHERAL_GPTIMER5},
-	{L4_PERIPHERAL_GPTIMER6, DSPVA_PERIPHERAL_GPTIMER6},
-	{L4_PERIPHERAL_GPTIMER7, DSPVA_PERIPHERAL_GPTIMER7},
-	{L4_PERIPHERAL_GPTIMER8, DSPVA_PERIPHERAL_GPTIMER8},
-	{L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1},
-	{L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2},
-	{L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3},
-	{L4_PERIPHERAL_GPIO4, DSPVA_PERIPHERAL_GPIO4},
-	{L4_PERIPHERAL_GPIO5, DSPVA_PERIPHERAL_GPIO5},
-	{L4_PERIPHERAL_IVA2WDT, DSPVA_PERIPHERAL_IVA2WDT},
-	{L4_PERIPHERAL_DISPLAY, DSPVA_PERIPHERAL_DISPLAY},
-	{L4_PERIPHERAL_SSI, DSPVA_PERIPHERAL_SSI},
-	{L4_PERIPHERAL_GDD, DSPVA_PERIPHERAL_GDD},
-	{L4_PERIPHERAL_SS1, DSPVA_PERIPHERAL_SS1},
-	{L4_PERIPHERAL_SS2, DSPVA_PERIPHERAL_SS2},
-	{L4_PERIPHERAL_UART1, DSPVA_PERIPHERAL_UART1},
-	{L4_PERIPHERAL_UART2, DSPVA_PERIPHERAL_UART2},
-	{L4_PERIPHERAL_UART3, DSPVA_PERIPHERAL_UART3},
-	{L4_PERIPHERAL_MCBSP1, DSPVA_PERIPHERAL_MCBSP1},
-	{L4_PERIPHERAL_MCBSP2, DSPVA_PERIPHERAL_MCBSP2},
-	{L4_PERIPHERAL_MCBSP3, DSPVA_PERIPHERAL_MCBSP3},
-	{L4_PERIPHERAL_MCBSP4, DSPVA_PERIPHERAL_MCBSP4},
-	{L4_PERIPHERAL_MCBSP5, DSPVA_PERIPHERAL_MCBSP5},
-	{L4_PERIPHERAL_CAMERA, DSPVA_PERIPHERAL_CAMERA},
-	{L4_PERIPHERAL_SPI1, DSPVA_PERIPHERAL_SPI1},
-	{L4_PERIPHERAL_SPI2, DSPVA_PERIPHERAL_SPI2},
-	{L4_PERIPHERAL_PRM, DSPVA_PERIPHERAL_PRM},
-	{L4_PERIPHERAL_CM, DSPVA_PERIPHERAL_CM},
-	{L4_PERIPHERAL_PER, DSPVA_PERIPHERAL_PER},
-	{PM_GRPSEL_BASE, DSPVA_GRPSEL_BASE},
-	{L4_PERIPHERAL_SIDETONE_MCBSP2, DSPVA_PERIPHERAL_SIDETONE_MCBSP2},
-	{L4_PERIPHERAL_SIDETONE_MCBSP3, DSPVA_PERIPHERAL_SIDETONE_MCBSP3},
-	{L4_PERIPHERAL_NULL, DSPVA_PERIPHERAL_NULL}
+/* Mailbox 4KB */
+{L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB},
+/* SCM 4KB */
+{L4_PERIPHERAL_SCRM, DSPVA_PERIPHERAL_SCRM, HW_PAGE_SIZE_4KB},
+/* PRM 8KB */
+{L4_PERIPHERAL_PRM_P1, DSPVA_PERIPHERAL_PRM_P1, HW_PAGE_SIZE_4KB},
+{L4_PERIPHERAL_PRM_P2, DSPVA_PERIPHERAL_PRM_P2, HW_PAGE_SIZE_4KB},
+
+/* CM1 4KB */
+{L4_PERIPHERAL_CM1, DSPVA_PERIPHERAL_CM1, HW_PAGE_SIZE_4KB},
+/* CM2 8KB */
+{L4_PERIPHERAL_CM2_P1, DSPVA_PERIPHERAL_CM2_P1, HW_PAGE_SIZE_4KB},
+{L4_PERIPHERAL_CM2_P2, DSPVA_PERIPHERAL_CM2_P2, HW_PAGE_SIZE_4KB},
+
+/* GP timer1 4KB */
+{L4_PERIPHERAL_GPTIMER5, DSPVA_PERIPHERAL_GPTIMER5, HW_PAGE_SIZE_4KB},
+/* GP timer6 4KB */
+{L4_PERIPHERAL_GPTIMER6, DSPVA_PERIPHERAL_GPTIMER6, HW_PAGE_SIZE_4KB},
+/* GP timer7 4KB */
+{L4_PERIPHERAL_GPTIMER7, DSPVA_PERIPHERAL_GPTIMER7, HW_PAGE_SIZE_4KB},
+/* GP timer8 4KB */
+{L4_PERIPHERAL_GPTIMER8, DSPVA_PERIPHERAL_GPTIMER8, HW_PAGE_SIZE_4KB},
+/* GPIO1 4KB */
+{L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1, HW_PAGE_SIZE_4KB},
+/* GPIO2 4KB */
+{L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2, HW_PAGE_SIZE_4KB},
+/* GPIO3 4KB */
+{L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3, HW_PAGE_SIZE_4KB},
+/* GPIO4 4KB */
+{L4_PERIPHERAL_GPIO4, DSPVA_PERIPHERAL_GPIO4, HW_PAGE_SIZE_4KB},
+/* GPIO5 4KB */
+{L4_PERIPHERAL_GPIO5, DSPVA_PERIPHERAL_GPIO5, HW_PAGE_SIZE_4KB},
+/* Watch dog timer 4KB */
+{L4_PERIPHERAL_WDT3, DSPVA_PERIPHERAL_WDT3, HW_PAGE_SIZE_4KB},
+/* Mcbsp1 4KB */
+{L4_PERIPHERAL_MCBSP1, DSPVA_PERIPHERAL_MCBSP1, HW_PAGE_SIZE_4KB},
+/* Mcbsp2 4KB */
+{L4_PERIPHERAL_MCBSP2, DSPVA_PERIPHERAL_MCBSP2, HW_PAGE_SIZE_4KB},
+/* Mcbsp3 4KB */
+{L4_PERIPHERAL_MCBSP3, DSPVA_PERIPHERAL_MCBSP3, HW_PAGE_SIZE_4KB},
+/* Mcbsp4 4KB */
+{L4_PERIPHERAL_MCBSP4, DSPVA_PERIPHERAL_MCBSP4, HW_PAGE_SIZE_4KB},
+/* Mcbsp5 4KB */
+{L4_PERIPHERAL_MCBSP5, DSPVA_PERIPHERAL_MCBSP5, HW_PAGE_SIZE_4KB},
+/* UART1 4KB */
+{L4_PERIPHERAL_UART1, DSPVA_PERIPHERAL_UART1, HW_PAGE_SIZE_4KB},
+/* UART2 4KB */
+{L4_PERIPHERAL_UART2, DSPVA_PERIPHERAL_UART2, HW_PAGE_SIZE_4KB},
+/* UART3 4KB */
+{L4_PERIPHERAL_UART3, DSPVA_PERIPHERAL_UART3, HW_PAGE_SIZE_4KB},
+/* SPI1 4KB */
+{L4_PERIPHERAL_MCSPI1, DSPVA_PERIPHERAL_MCSPI1, HW_PAGE_SIZE_4KB},
+/* SPI2 4KB */
+{L4_PERIPHERAL_MCSPI2, DSPVA_PERIPHERAL_MCSPI2, HW_PAGE_SIZE_4KB},
+
+{L4_PERIPHERAL_NULL, DSPVA_PERIPHERAL_NULL}
+
 };
 
+
 /*
  *   15         10                  0
  *   ---------------------------------
@@ -340,7 +373,7 @@ struct WMD_DEV_CONTEXT {
 	 */
 	u32 dwDspExtBaseAddr;	/* See the comment above        */
 	u32 dwAPIRegBase;	/* API memory mapped registers  */
-	void __iomem *dwDSPMmuBase;	/* DSP MMU Mapped registers     */
+	u32 dwDSPMmuBase;	/* DSP MMU Mapped registers     */
 	u32 dwMailBoxBase;	/* Mail box mapped registers    */
 	u32 dwAPIClkBase;	/* CLK Registers                */
 	u32 dwDSPClkM2Base;	/* DSP Clock Module m2          */
@@ -361,6 +394,7 @@ struct WMD_DEV_CONTEXT {
 	u32 dwBrdState;	/* Last known board state.      */
 	u32 ulIntMask;	/* int mask                     */
 	u16 ioBase;	/* Board I/O base               */
+	u16 wIntrVal2Dsp;	/* MBX value to DSP. See mbx_sh.h */
 	u32 numTLBEntries;	/* DSP MMU TLB entry counter    */
 	u32 fixedTLBEntries;	/* Fixed DSPMMU TLB entry count */
 

drivers/dsp/bridge/wmd/io_sm.c

@@ -96,6 +96,14 @@
 #include "_msg_sm.h"
 #include <dspbridge/gt.h>
 
+/*------------------------------------Notify */
+#include <syslink/notify.h>
+#include <syslink/notify_driverdefs.h>
+#include <syslink/notify_tesladriver.h>
+#include <syslink/notify_shmdriver.h>
+#include <syslink/notify_driver.h>
+
+
 /*  ----------------------------------- Defines, Data Structures, Typedefs */
 #define OUTPUTNOTREADY  0xffff
 #define NOTENABLED      0xffff	/* channel(s) not enabled */
@@ -107,6 +115,14 @@
 
 #define MAX_PM_REQS 32
 
+struct notify_driver_handle *handlePtr;
+struct notify_driver_object *handle;
+u32  eventNo;
+struct IO_MGR *ext_pIOMgr;
+extern irqreturn_t (*irq_handler)(int, void *, struct pt_regs *);
+void * external_piomgr;
+
+
 /* IO Manager: only one created per board: */
 struct IO_MGR {
 	/* These four fields must be the first fields in a IO_MGR_ struct: */
@@ -206,6 +222,17 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 	struct CHNL_MGR *hChnlMgr;
        static int ref_count;
 	u32 devType;
+
+        struct notify_config ntfy_config;
+        struct notify_tesladrv_config tesla_cfg;
+        struct notify_tesladrv_params params;
+        u32 mem_va;
+        u32 mem_pa;
+        char  driverName[32] = "NOTIFYMBXDRV";
+        int  ntfystatus;
+        irq_handler = (void *) IO_ISR;
+
+
 	/* Check DBC requirements:  */
 	DBC_Require(phIOMgr != NULL);
 	DBC_Require(pMgrAttrs != NULL);
@@ -273,6 +300,52 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 		pIOMgr->iQuePowerHead = 0;
 		pIOMgr->iQuePowerTail = 0;
 	}
+
+	        notify_get_config(&ntfy_config);
+        ntfystatus = notify_setup(&ntfy_config);
+
+        if (NOTIFY_FAILED(ntfystatus)) {
+                DBG_Trace(DBG_LEVEL7, "Failed notify_setup ntfystatus 0x%x \n",
+                          ntfystatus);
+        } else
+                printk("%s:%d:PASS\n",__func__,__LINE__);
+
+        notify_tesladrv_getconfig(&tesla_cfg);
+
+        ntfystatus = notify_tesladrv_setup(&tesla_cfg);
+
+        notify_tesladrv_params_init(NULL, &params);
+
+        mem_va = dma_alloc_coherent(NULL, 0x4000, &mem_pa,GFP_ATOMIC);
+        if (mem_va == NULL)
+                pr_err("Memory allocation for communication failed\n");
+        params.num_events          = 32;
+        params.num_reserved_events  = 0;
+        params.send_event_poll_count = (int) -1;
+        params.recv_int_id          = 26;
+        params.send_int_id          = 55;
+        params.shared_addr_size     = 0x4000;
+        params.shared_addr                = mem_va;
+        params.remote_proc_id         = 0;
+
+        handle = notify_tesladrv_create(driverName,&params);
+        if (NOTIFY_FAILED(ntfystatus)) {
+                DBG_Trace(DBG_LEVEL7, "Failed notify_get_driver_handle  ntfystatus 0x%x \n",
+                          ntfystatus);
+        } 
+
+        eventNo = ((NOTIFY_SYSTEM_KEY<<16)|NOTIFY_TESLA_EVENTNUMBER);
+
+        ntfystatus = notify_register_event(handle, /*PROC_TESLA*/0, eventNo,(void*)IO_ISR, NULL);
+
+        if (NOTIFY_FAILED(ntfystatus)) {
+                DBG_Trace(DBG_LEVEL7, "Failed notify_register_event ntfystatus 0x%x \n",
+                          ntfystatus);
+        } 
+
+        notify_disable_event(handle, 0, eventNo);
+
+
 	if (DSP_SUCCEEDED(status)) {
 		status = CFG_GetHostResources((struct CFG_DEVNODE *)
 				DRV_GetFirstDevExtension() , &hostRes);
@@ -280,6 +353,10 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 	if (DSP_SUCCEEDED(status)) {
 		pIOMgr->hWmdContext = hWmdContext;
 		pIOMgr->fSharedIRQ = pMgrAttrs->fShared;
+#ifdef OMAP44XX
+		external_piomgr = pIOMgr;
+
+#else
 		IO_DisableInterrupt(hWmdContext);
 		if (devType == DSP_UNIT) {
 			/* Plug the channel ISR:. */
@@ -289,6 +366,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
                        else
                                status = DSP_EFAIL;
 		}
+#endif
        if (DSP_SUCCEEDED(status))
                DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n",
                                pIOMgr);
@@ -317,6 +395,11 @@ func_cont:
 DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr)
 {
 	DSP_STATUS status = DSP_SOK;
+#ifdef OMAP44XX
+	status = notify_tesladrv_delete(&handle);
+        status = notify_tesladrv_destroy();
+        status = notify_destroy();
+#else
 	struct WMD_DEV_CONTEXT *hWmdContext;
 	if (MEM_IsValidHandle(hIOMgr, IO_MGRSIGNATURE)) {
 		/* Unplug IRQ:    */
@@ -338,7 +421,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr)
 		MEM_FreeObject(hIOMgr);
        } else
 		status = DSP_EHANDLE;
-
+#endif
 	return status;
 }
 
@@ -676,15 +759,29 @@ func_cont:
 
 	/* Map the L4 peripherals */
 	i = 0;
-	while (L4PeripheralTable[i].physAddr && DSP_SUCCEEDED(status)) {
-		status = hIOMgr->pIntfFxns->pfnBrdMemMap
-			(hIOMgr->hWmdContext, L4PeripheralTable[i].physAddr,
-			L4PeripheralTable[i].dspVirtAddr, HW_PAGE_SIZE_4KB,
-			mapAttrs);
-		if (DSP_FAILED(status))
-			break;
-		i++;
-	}
+#ifdef OMAP_3430
+		while (L4PeripheralTable[i].physAddr && DSP_SUCCEEDED(status)) {
+			status = hIOMgr->pIntfFxns->pfnBrdMemMap
+				 (hIOMgr->hWmdContext,
+				  L4PeripheralTable[i].physAddr,
+				  L4PeripheralTable[i].dspVirtAddr,
+				  HW_PAGE_SIZE_4KB,
+				  mapAttrs);
+			DBC_Assert(DSP_SUCCEEDED(status));
+			i++;
+		}
+#else
+		while (L4PeripheralTable[i].physAddr && DSP_SUCCEEDED(status)) {
+			status = hIOMgr->pIntfFxns->pfnBrdMemMap
+				 (hIOMgr->hWmdContext,
+				  L4PeripheralTable[i].physAddr,
+				  L4PeripheralTable[i].dspVirtAddr,
+				  L4PeripheralTable[i].ulSize,
+				  mapAttrs);
+			DBC_Assert(DSP_SUCCEEDED(status));
+			i++;
+		}
+#endif
 
 	if (DSP_SUCCEEDED(status)) {
 		for (i = ndx; i < WMDIOCTL_NUMOFMMUTLB; i++) {
@@ -923,6 +1020,8 @@ static void IO_DispatchPM(struct work_struct *work)
 					 "Hibernation command failed\n");
 			}
 		} else if (pArg[0] == MBX_PM_OPP_REQ) {
+#ifndef CONFIG_DISABLE_BRIDGE_PM
+#ifndef CONFIG_DISABLE_BRIDGE_DVFS
 			pArg[1] = pIOMgr->pSharedMem->oppRequest.rqstOppPt;
 			DBG_Trace(DBG_LEVEL7, "IO_DispatchPM : Value of OPP "
 				 "value =0x%x \n", pArg[1]);
@@ -934,6 +1033,8 @@ static void IO_DispatchPM(struct work_struct *work)
 					 "to set constraint = 0x%x \n",
 					 pArg[1]);
 			}
+#endif
+#endif
 
 		} else {
 			DBG_Trace(DBG_LEVEL7, "IO_DispatchPM - clock control - "
@@ -1008,18 +1109,25 @@ void IO_DPC(IN OUT void *pRefData)
  *      Calls the WMD's CHNL_ISR to determine if this interrupt is ours, then
  *      schedules a DPC to dispatch I/O.
  */
-irqreturn_t IO_ISR(int irq, IN void *pRefData)
+
+void IO_ISR(IN  unsigned long int procId,
+	            IN void * pRefData,
+        	    struct pt_regs *reg)
 {
-	struct IO_MGR *hIOMgr = (struct IO_MGR *)pRefData;
+	struct IO_MGR *hIOMgr;
+        pRefData = external_piomgr;
+        hIOMgr = (struct IO_MGR *)pRefData;
+	
 	bool fSchedDPC;
-       DBC_Require(irq == INT_MAIL_MPU_IRQ);
+//       DBC_Require(irq == INT_MAIL_MPU_IRQ);
 	DBC_Require(MEM_IsValidHandle(hIOMgr, IO_MGRSIGNATURE));
 	DBG_Trace(DBG_LEVEL3, "Entering IO_ISR(0x%x)\n", pRefData);
 
+#ifdef OMAP_3430
 	/* Call WMD's CHNLSM_ISR() to see if interrupt is ours, and process. */
 	if (IO_CALLISR(hIOMgr->hWmdContext, &fSchedDPC, &hIOMgr->wIntrVal)) {
-		{
 			DBG_Trace(DBG_LEVEL3, "IO_ISR %x\n", hIOMgr->wIntrVal);
+#endif
 			if (hIOMgr->wIntrVal & MBX_PM_CLASS) {
 				hIOMgr->dQuePowerMbxVal[hIOMgr->iQuePowerHead] =
 					hIOMgr->wIntrVal;
@@ -1032,17 +1140,22 @@ irqreturn_t IO_ISR(int irq, IN void *pRefData)
 			if (hIOMgr->wIntrVal == MBX_DEH_RESET) {
 				DBG_Trace(DBG_LEVEL6, "*** DSP RESET ***\n");
 				hIOMgr->wIntrVal = 0;
+#ifdef OMAP44XX
+			} else {
+#else
 			} else if (fSchedDPC) {
+#endif
 				/* PROC-COPY defer i/o  */
 				DPC_Schedule(hIOMgr->hDPC);
 			}
-		}
+#ifdef OMAP_3430
        } else
 		/* Ensure that, if WMD didn't claim it, the IRQ is shared. */
 		DBC_Ensure(hIOMgr->fSharedIRQ);
        return IRQ_HANDLED;
+#endif
 }
-
+EXPORT_SYMBOL(IO_ISR);
 /*
  *  ======== IO_RequestChnl ========
  *  Purpose:
@@ -1743,8 +1856,6 @@ DSP_STATUS IO_SHMsetting(IN struct IO_MGR *hIOMgr, IN enum SHM_DESCTYPE desc,
 	default:
 		break;
 
-				queue_work(bridge_workqueue,
-							 &(hIOMgr->io_workq));
 	}
 #endif
 	return DSP_SOK;
@@ -1757,6 +1868,7 @@ DSP_STATUS IO_SHMsetting(IN struct IO_MGR *hIOMgr, IN enum SHM_DESCTYPE desc,
 DSP_STATUS WMD_IO_GetProcLoad(IN struct IO_MGR *hIOMgr,
 			     OUT struct DSP_PROCLOADSTAT *pProcStat)
 {
+#ifdef OMAP_3430
 	pProcStat->uCurrLoad = hIOMgr->pSharedMem->loadMonInfo.currDspLoad;
 	pProcStat->uPredictedLoad = hIOMgr->pSharedMem->loadMonInfo.predDspLoad;
 	pProcStat->uCurrDspFreq = hIOMgr->pSharedMem->loadMonInfo.currDspFreq;
@@ -1766,6 +1878,7 @@ DSP_STATUS WMD_IO_GetProcLoad(IN struct IO_MGR *hIOMgr,
 			     "Pred Freq = %d\n", pProcStat->uCurrLoad,
 			     pProcStat->uPredictedLoad, pProcStat->uCurrDspFreq,
 			     pProcStat->uPredictedFreq);
+#endif
 	return DSP_SOK;
 }
 
@@ -1773,8 +1886,8 @@ DSP_STATUS WMD_IO_GetProcLoad(IN struct IO_MGR *hIOMgr,
 void PrintDSPDebugTrace(struct IO_MGR *hIOMgr)
 {
 	u32 ulNewMessageLength = 0, ulGPPCurPointer;
+	volatile unsigned int i;
 
-       GT_0trace(dsp_trace_mask, GT_ENTER, "Entering PrintDSPDebugTrace\n");
 
 	while (true) {
 		/* Get the DSP current pointer */
@@ -1822,6 +1935,10 @@ void PrintDSPDebugTrace(struct IO_MGR *hIOMgr)
                        GT_0trace(dsp_trace_mask, GT_1CLASS, hIOMgr->pMsg);
 		}
 	}
+#ifdef OMAP44XX
+	for (i = 0; i < 0x100; i++)
+		;
+#endif
 }
 #endif
 

drivers/dsp/bridge/wmd/tiomap3430.c

@@ -141,7 +141,7 @@ static DSP_STATUS PteSet(struct PgTableAttrs *pt, u32 pa, u32 va,
 static DSP_STATUS MemMapVmalloc(struct WMD_DEV_CONTEXT *hDevContext,
 			u32 ulMpuAddr, u32 ulVirtAddr,
 			u32 ulNumBytes, struct HW_MMUMapAttrs_t *hwAttrs);
-static void GetHWRegs(void __iomem *prcm_base, void __iomem *cm_base);
+void GetHWRegs(u32 prcm_base, u32 cm1_base, u32 cm2_base);
 
 /*  ----------------------------------- Globals */
 
@@ -253,6 +253,7 @@ static inline void flush_all(struct WMD_DEV_CONTEXT *pDevContext)
 
 	CFG_GetHostResources((struct CFG_DEVNODE *)DRV_GetFirstDevExtension(),
 				&resources);
+#ifdef OMAP_3430
 	HW_PWRST_IVA2RegGet(resources.dwPrmBase, &temp);
 
 	if ((temp & HW_PWR_STATE_ON) == HW_PWR_STATE_OFF ||
@@ -263,6 +264,9 @@ static inline void flush_all(struct WMD_DEV_CONTEXT *pDevContext)
 		CLK_Disable(SERVICESCLK_iva2_ck);
 	} else
 		tlb_flush_all(pDevContext->dwDSPMmuBase);
+#else
+		tlb_flush_all(pDevContext->dwDSPMmuBase);
+#endif
 }
 
 static void bad_page_dump(u32 pa, struct page *pg)
@@ -321,15 +325,47 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext)
 	if (DSP_FAILED(status))
 		goto error_return;
 
+#ifdef OMAP44XX
+    printk("Disabling Clocks... and resources.dwCm1Base = 0x%x \n  resources.dwCm2Base= 0x%x\n"
+		"resources.dwPrmBase = 0x%x", resources.dwCm1Base, resources.dwCm2Base, resources.dwPrmBase);
+    HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
+    printk("Resetting DSP...");
+    HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
+    printk("Enabling Clocks...");
+    HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
+
+
+    HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);/*TODO check if it is correct*/
+    HW_RST_Reset(resources.dwPrmBase, HW_RST2_TESLA);/*Just to ensure that the RST's are enabled*/
+	HW_RST_UnReset(resources.dwPrmBase, HW_RST2_TESLA);
+
+	printk("Calling the MMU_LOCK BaseValue");
+
+	*((REG_UWORD32 *)((u32)(resources.dwDmmuBase)+0x50)) = 0x400;
+#else
+	
 	GetHWRegs(resources.dwPrmBase, resources.dwCmBase);
+	HW_PWRST_RegGet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA, &temp);
+
 	HW_PWRST_IVA2RegGet(resources.dwPrmBase, &temp);
+
 	if ((temp & 0x03) != 0x03 || (temp & 0x03) != 0x02) {
 		/* IVA2 is not in ON state */
 		/* Read and set PM_PWSTCTRL_IVA2  to ON */
+		HW_PWR_PowerStateGet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA,
+				     &pwrState);
+
+		HW_PWR_PowerStateSet(resources.dwPrmBase,
+					  HW_PWR_DOMAIN_TESLA,
+					  HW_PWR_STATE_ON);
+
 		HW_PWR_IVA2PowerStateSet(resources.dwPrmBase,
 					  HW_PWR_DOMAIN_DSP,
 					  HW_PWR_STATE_ON);
 		/* Set the SW supervised state transition */
+
+
+
 		HW_PWR_CLKCTRL_IVA2RegSet(resources.dwCmBase, HW_SW_SUP_WAKEUP);
 		/* Wait until the state has moved to ON */
 		HW_PWR_IVA2StateGet(resources.dwPrmBase, HW_PWR_DOMAIN_DSP,
@@ -341,14 +377,16 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext)
 	GetHWRegs(resources.dwPrmBase, resources.dwCmBase);
 	HW_RST_UnReset(resources.dwPrmBase, HW_RST2_IVA2);
 	CLK_Enable(SERVICESCLK_iva2_ck);
-
+#endif
 	if (DSP_SUCCEEDED(status)) {
 		/* set the device state to IDLE */
 		pDevContext->dwBrdState = BRD_IDLE;
 	}
 error_return:
 	DBG_Trace(DBG_LEVEL6, "WMD_BRD_Monitor - End ****** \n");
-	GetHWRegs(resources.dwPrmBase, resources.dwCmBase);
+#ifdef OMAP44XX
+	GetHWRegs(resources.dwPrmBase, resources.dwCm1Base, resources.dwCm2Base);
+#endif
 	return status;
 }
 
@@ -438,6 +476,8 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 	u32 ulBiosGpTimer;
 	u32 uClkCmd;
 	struct IO_MGR *hIOMgr;
+	register u32 newAdress = ((u32)(dwDSPAddr));
+
 	u32 ulLoadMonitorTimer;
 	u32 extClkId = 0;
 	u32 tmpIndex;
@@ -445,7 +485,11 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 
 	DBG_Trace(DBG_ENTER, "Entering WMD_BRD_Start:\n hDevContext: 0x%x\n\t "
 			     "dwDSPAddr: 0x%x\n", hDevContext, dwDSPAddr);
-
+#ifdef OMAP44XX
+	printk(KERN_ERR "Please break Virtio by typing 'y' in console and start CCS"
+		"set DSP  PC adress to below DSP Start address and Run using CCS\n");
+	printk(KERN_ERR "- - - DSP Start Address [0x%x]- - -\n", dwDSPAddr) ;
+#endif
 	/* The device context contains all the mmu setup info from when the
 	 * last dsp base image was loaded. The first entry is always
 	 * SHMMEM base. */
@@ -476,9 +520,14 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 		status = CFG_GetHostResources(
 			(struct CFG_DEVNODE *)DRV_GetFirstDevExtension(),
 			&resources);
+		newAdress &= 0xFFFFFC0;
+	*((REG_UWORD32 *)((u32)(resources.dwSysCtrlBase)+0x304)) = newAdress;
 		/* Assert RST1 i.e only the RST only for DSP megacell  */
 		/* HW_RST_Reset(resources.dwPrcmBase, HW_RST1_IVA2);*/
 		if (DSP_SUCCEEDED(status)) {
+#ifdef OMAP44XX
+			HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
+#else
 			HW_RST_Reset(resources.dwPrmBase, HW_RST1_IVA2);
 			if (dsp_debug) {
 				/* Set the bootmode to self loop  */
@@ -495,17 +544,29 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 				HW_DSPSS_BootModeSet(resources.dwSysCtrlBase,
 					HW_DSPSYSC_DIRECTBOOT, dwDSPAddr);
 			}
+#endif
 		}
 	}
 	if (DSP_SUCCEEDED(status)) {
 		/* Reset and Unreset the RST2, so that BOOTADDR is copied to
 		 * IVA2 SYSC register */
+#ifdef OMAP44XX
+		HW_RST_Reset(resources.dwPrmBase, HW_RST2_TESLA);
+		udelay(100);
+		HW_RST_UnReset(resources.dwPrmBase, HW_RST2_TESLA);
+		udelay(100);
+		DBG_Trace(DBG_LEVEL6, "WMD_BRD_Start 0 ****** \n");
+		GetHWRegs(resources.dwPrmBase, resources.dwCm1Base,
+					resources.dwCm2Base);
+
+#else
 		HW_RST_Reset(resources.dwPrmBase, HW_RST2_IVA2);
 		udelay(100);
 		HW_RST_UnReset(resources.dwPrmBase, HW_RST2_IVA2);
 		udelay(100);
 		DBG_Trace(DBG_LEVEL6, "WMD_BRD_Start 0 ****** \n");
 		GetHWRegs(resources.dwPrmBase, resources.dwCmBase);
+#endif
 		/* Disbale the DSP MMU */
 		HW_MMU_Disable(resources.dwDmmuBase);
 		/* Disable TWL */
@@ -548,13 +609,16 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 		/* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
 
 
+#ifdef OMAP_3430
 		temp = __raw_readl((resources.dwDmmuBase) + 0x10);
 		temp = (temp & 0xFFFFFFEF) | 0x11;
 		__raw_writel(temp, (resources.dwDmmuBase) + 0x10);
-
+#endif
 		/* Let the DSP MMU run */
 		HW_MMU_Enable(resources.dwDmmuBase);
 
+
+#ifdef OMAP_3430
 		/* Enable the BIOS clock  */
 		(void)DEV_GetSymbol(pDevContext->hDevObject,
 					BRIDGEINIT_BIOSGPTIMER,
@@ -565,8 +629,9 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 				     &ulLoadMonitorTimer);
 		DBG_Trace(DBG_LEVEL7, "Load Monitor Timer : 0x%x\n",
 			  ulLoadMonitorTimer);
+#endif
 	}
-
+#ifdef OMAP_3430
 	if (DSP_SUCCEEDED(status)) {
 		if (ulLoadMonitorTimer != 0xFFFF) {
 			uClkCmd = (BPWR_DisableClock << MBX_PM_CLK_CMDSHIFT) |
@@ -703,27 +768,45 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 		 * stale messages */
 		(void)CHNLSM_EnableInterrupt(pDevContext);
 	}
-
+#else
+		(void)CHNLSM_EnableInterrupt(pDevContext);
+#endif
 	if (DSP_SUCCEEDED(status)) {
+#ifdef OMAP_3430
 		HW_RSTCTRL_RegGet(resources.dwPrmBase, HW_RST1_IVA2, &temp);
 		DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTCTRL_DSP = 0x%x \n",
 				temp);
 		HW_RSTST_RegGet(resources.dwPrmBase, HW_RST1_IVA2, &temp);
 		DBG_Trace(DBG_LEVEL7, "BRD_Start0: RM_RSTST_DSP = 0x%x \n",
 				temp);
-
+#else
+        HW_RSTCTRL_RegGet(resources.dwPrmBase, &temp);
+        DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTCTRL_DSP = 0x%x \n",
+                temp);
+        HW_RSTST_RegGet(resources.dwPrmBase, &temp);
+        DBG_Trace(DBG_LEVEL7, "BRD_Start0: RM_RSTST_DSP = 0x%x \n",
+                temp);
+        /* Let DSP go */
+#endif
 		/* Let DSP go */
 		DBG_Trace(DBG_LEVEL7, "Unreset, WMD_BRD_Start\n");
 		/* Enable DSP MMU Interrupts */
 		HW_MMU_EventEnable(resources.dwDmmuBase,
 				HW_MMU_ALL_INTERRUPTS);
 		/* release the RST1, DSP starts executing now .. */
+#ifdef OMAP44XX
+		HW_RST_UnReset(resources.dwPrmBase, HW_RST1_TESLA);
+        HW_RSTST_RegGet(resources.dwPrmBase, &temp);
+        DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTST_DSP = 0x%x \n",
+                temp);
+        HW_RSTCTRL_RegGet(resources.dwPrmBase, &temp);
+#else
 		HW_RST_UnReset(resources.dwPrmBase, HW_RST1_IVA2);
-
 		HW_RSTST_RegGet(resources.dwPrmBase, HW_RST1_IVA2, &temp);
 		DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTST_DSP = 0x%x \n",
 				temp);
 		HW_RSTCTRL_RegGet(resources.dwPrmBase, HW_RST1_IVA2, &temp);
+#endif
 		DBG_Trace(DBG_LEVEL5, "WMD_BRD_Start: CM_RSTCTRL_DSP: 0x%x \n",
 				temp);
 		DBG_Trace(DBG_LEVEL7, "Driver waiting for Sync @ 0x%x \n",
@@ -805,6 +888,16 @@ static DSP_STATUS WMD_BRD_Stop(struct WMD_DEV_CONTEXT *hDevContext)
 		return DSP_EFAIL;
 	}
 
+#ifdef OMAP44XX
+        DBG_Trace(DBG_LEVEL7, "Resetting DSP...");
+        printk("Stop:Disabling Clocks...");
+         HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
+         printk("Stop:Resetting DSP...");
+         HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
+         /*  Enable DSP */
+         printk("Stop:Enabling Clocks...");
+         HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
+#else
 	HW_PWRST_IVA2RegGet(resources.dwPrmBase, &dspPwrState);
 	if (dspPwrState != HW_PWR_STATE_OFF) {
 		CHNLSM_InterruptDSP2(pDevContext, MBX_PM_DSPIDLE);
@@ -849,6 +942,7 @@ static DSP_STATUS WMD_BRD_Stop(struct WMD_DEV_CONTEXT *hDevContext)
 		memset((u8 *) pPtAttrs->pgInfo, 0x00,
 		       (pPtAttrs->L2NumPages * sizeof(struct PageInfo)));
 	}
+#endif
 	DBG_Trace(DBG_LEVEL6, "WMD_BRD_Stop - End ****** \n");
 	return status;
 }
@@ -891,12 +985,17 @@ static DSP_STATUS WMD_BRD_Delete(struct WMD_DEV_CONTEXT *hDevContext)
 		DBG_Trace(DBG_LEVEL1, "Device Delete failed \n ");
 		return DSP_EFAIL;
 	}
+#ifdef OMAP44XX
+	 HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
+#else
+
 	status = SleepDSP(pDevContext, PWR_EMERGENCYDEEPSLEEP, NULL);
 	clk_status = CLK_Disable(SERVICESCLK_iva2_ck);
 	if (DSP_FAILED(clk_status)) {
 		DBG_Trace(DBG_LEVEL6, "\n WMD_BRD_Stop: CLK_Disable failed for"
 			  " iva2_fck\n");
 	}
+#endif
 	/* Release the Ext Base virtual Address as the next DSP Program
 	 * may have a different load address */
 	if (pDevContext->dwDspExtBaseAddr)
@@ -913,8 +1012,10 @@ static DSP_STATUS WMD_BRD_Delete(struct WMD_DEV_CONTEXT *hDevContext)
 			(pPtAttrs->L2NumPages * sizeof(struct PageInfo)));
 	}
 	DBG_Trace(DBG_LEVEL6, "WMD_BRD_Stop - End ****** \n");
+#ifdef OMAP_3430
 	HW_RST_Reset(resources.dwPrmBase, HW_RST1_IVA2);
 	HW_RST_Reset(resources.dwPrmBase, HW_RST2_IVA2);
+#endif
 
 	return status;
 }
@@ -987,6 +1088,9 @@ static DSP_STATUS WMD_DEV_Create(OUT struct WMD_DEV_CONTEXT **ppDevContext,
 	u32   pg_tbl_va;
 	u32   align_size;
 
+	enum HW_PwrState_t pwrState;
+	u32 PwrCtrl;
+	u32 iIterations = 0;
 	DBG_Trace(DBG_ENTER, "WMD_DEV_Create, ppDevContext: 0x%x\n\t\t "
 		  "hDevObject: 0x%x\n\t\tpConfig: 0x%x\n\t\tpDspConfig: 0x%x\n",
 		  ppDevContext, hDevObject, pConfig, pDspConfig);
@@ -1029,7 +1133,7 @@ static DSP_STATUS WMD_DEV_Create(OUT struct WMD_DEV_CONTEXT **ppDevContext,
 		/* Assuming that we use only DSP's memory map
 		 * until 0x4000:0000 , we would need only 1024
 		 * L1 enties i.e L1 size = 4K */
-		pPtAttrs->L1size = 0x1000;
+		pPtAttrs->L1size = 0x4000;
 		align_size = pPtAttrs->L1size;
 		/* Align sizes are expected to be power of 2 */
 		/* we like to get aligned on L1 table size */
@@ -1106,6 +1210,7 @@ static DSP_STATUS WMD_DEV_Create(OUT struct WMD_DEV_CONTEXT **ppDevContext,
 
 	if (DSP_SUCCEEDED(status)) {
 		/* Set the Endianism Register */ /* Need to set this */
+		pDevContext->wIntrVal2Dsp = MBX_PCPY_CLASS;
 		/* Retrieve the TC u16 SWAP Option */
 		status = REG_GetValue(NULL, CURRENTCONFIG, TCWORDSWAP,
 				     (u8 *)&tcWordSwap, &tcWordSwapSize);
@@ -1116,6 +1221,22 @@ static DSP_STATUS WMD_DEV_Create(OUT struct WMD_DEV_CONTEXT **ppDevContext,
 		/* Set the Clock Divisor for the DSP module */
 		DBG_Trace(DBG_LEVEL7, "WMD_DEV_create:Reset mail box and "
 			  "enable the clock \n");
+#ifdef OMAP44XX
+			HW_PWR_ForceStateSet(resources.dwCm1Base, HW_PWR_DOMAIN_TESLA, HW_SW_SUP_WAKEUP);
+			HW_PWR_PowerStateSet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA, HW_PWR_STATE_ON);
+			HW_PWR_PowerStateGet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA, &pwrState);
+				while (HW_PWR_STATE_ON != pwrState) {
+						iIterations++;
+						if (iIterations >= 500) {
+							HW_PWRSTCTRL_RegGet(resources.dwPrmBase, &PwrCtrl);
+							printk("Error: Failed to put the DSP domain into ON"
+								"state PRM_TESLA_PWRSTCTRL = 0x%x", PwrCtrl);
+								return DSP_EFAIL;
+						}
+						HW_PWR_PowerStateGet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA, &pwrState);
+				}
+/*			HW_CLK_Enable (resources.dwPrmBase, HW_CLK_IF_MBOX);*/
+#else
 		status = CLK_Enable(SERVICESCLK_mailbox_ick);
 		if (DSP_FAILED(status)) {
 			DBG_Trace(DBG_LEVEL7,
@@ -1125,6 +1246,7 @@ static DSP_STATUS WMD_DEV_Create(OUT struct WMD_DEV_CONTEXT **ppDevContext,
 		udelay(5);
 		/* 24xx-Linux MMU address is obtained from the host
 		 * resources struct */
+#endif
 		pDevContext->dwDSPMmuBase = resources.dwDmmuBase;
 	}
 	if (DSP_SUCCEEDED(status)) {
@@ -1211,6 +1333,8 @@ static DSP_STATUS WMD_DEV_Ctrl(struct WMD_DEV_CONTEXT *pDevContext, u32 dwCmd,
 		DBG_Trace(DBG_LEVEL5, "WMDIOCTL_PWR_HIBERNATE\n");
 		status = handle_hibernation_fromDSP(pDevContext);
 		break;
+#ifndef CONFIG_DISABLE_BRIDGE_PM
+#ifndef CONFIG_DISABLE_BRIDGE_DVFS
 	case WMDIOCTL_PRESCALE_NOTIFY:
 		DBG_Trace(DBG_LEVEL5, "WMDIOCTL_PRESCALE_NOTIFY\n");
 		status = PreScale_DSP(pDevContext, pArgs);
@@ -1223,6 +1347,8 @@ static DSP_STATUS WMD_DEV_Ctrl(struct WMD_DEV_CONTEXT *pDevContext, u32 dwCmd,
 		DBG_Trace(DBG_LEVEL5, "WMDIOCTL_CONSTRAINT_REQUEST\n");
 		status = handle_constraints_set(pDevContext, pArgs);
 		break;
+#endif
+#endif
 	default:
 		status = DSP_EFAIL;
 		DBG_Trace(DBG_LEVEL7, "Error in WMD_BRD_Ioctl \n");
@@ -2017,9 +2143,13 @@ static DSP_STATUS MemMapVmalloc(struct WMD_DEV_CONTEXT *pDevContext,
 	DBG_Trace(DBG_LEVEL7, "< WMD_BRD_MemMap at end status %x\n", status);
 	return status;
 }
+#ifdef OMAP44XX
+void GetHWRegs(u32 prm_base, u32 cm1_base, u32 cm2_base) { }
 
+#else
 static void GetHWRegs(void __iomem *prm_base, void __iomem *cm_base)
 {
+
 	u32 temp;
 	temp = __raw_readl((cm_base) + 0x00);
 	DBG_Trace(DBG_LEVEL6, "CM_FCLKEN_IVA2 = 0x%x \n", temp);
@@ -2042,6 +2172,7 @@ static void GetHWRegs(void __iomem *prm_base, void __iomem *cm_base)
 	temp = __raw_readl((cm_base) + 0xA10);
 	DBG_Trace(DBG_LEVEL6, "CM_ICLKEN1_CORE = 0x%x \n", temp);
 }
+#endif
 
 /*
  *  ======== configureDspMmu ========

drivers/dsp/bridge/wmd/tiomap_io.c

@@ -59,6 +59,7 @@ static u32 ulDynExtBase;
 static u32 ulTraceSecBeg;
 static u32 ulTraceSecEnd;
 static u32 ulShmBaseVirt;
+static u32 ulshmBeg;
 
 bool bSymbolsReloaded = true;
 
@@ -279,15 +280,21 @@ DSP_STATUS WriteExtDspData(struct WMD_DEV_CONTEXT *pDevContext,
 		 "ulNumBytes 0x%x \n", dwDSPAddr, ulNumBytes);
 	  if (bSymbolsReloaded) {
 		/* Check if it is a load to Trace section */
+#ifndef DSP_TRACEBUF_DISABLED
 		retVal = DEV_GetSymbol(pDevContext->hDevObject,
 					DSP_TRACESEC_BEG, &ulTraceSecBeg);
+#endif
 		if (DSP_SUCCEEDED(retVal))
+#ifndef DSP_TRACEBUF_DISABLED
 			retVal = DEV_GetSymbol(pDevContext->hDevObject,
 				 DSP_TRACESEC_END, &ulTraceSecEnd);
+#endif
+			retVal = DEV_GetSymbol(pDevContext->hDevObject,
+				 SHMBASENAME, &ulshmBeg);
 	}
 	if (DSP_SUCCEEDED(retVal)) {
 		if ((dwDSPAddr <= ulTraceSecEnd) &&
-		   (dwDSPAddr >= ulTraceSecBeg)) {
+		   (dwDSPAddr >= ulshmBeg)) {
 			DBG_Trace(DBG_LEVEL5, "Writing to DSP Trace "
 				 "section 0x%x \n", dwDSPAddr);
 			bTraceLoad = true;

drivers/dsp/bridge/wmd/tiomap_sm.c

@@ -25,6 +25,45 @@
 
 #include "_tiomap.h"
 #include "_tiomap_pwr.h"
+#include <hw_defs.h>
+#include <hw_mbox.h>
+
+
+
+#ifndef CONFIG_DISABLE_BRIDGE_PM
+#ifndef CONFIG_DISABLE_BRIDGE_DVFS
+#ifndef CONFIG_OMAP3_PM
+#include <mach/omap-pm.h>
+#else
+#include <mach/resource.h>
+extern struct constraint_handle *dsp_constraint_handle;
+#endif
+#endif
+#endif
+/*------------------------------------- Noitfy */
+#include <syslink/notify.h>
+#include <syslink/notify_driverdefs.h>
+#include <syslink/notify_tesladriver.h>
+extern struct notify_driver_object *handle;
+
+/*  ----------------------------------- Defines, Data Structures, Typedefs */
+#ifndef DEBUG
+#define TIHELEN_INT_TIMEOUT     1
+#define LOOP_COUNT              1000000
+#endif
+
+#ifdef OMAP44XX
+#define PROCESSOR_TESLA 0
+#define KEY 0
+#endif
+
+
+extern struct MAILBOX_CONTEXT mboxsetting;
+
+extern DSP_STATUS DSP_PeripheralClocks_Enable(struct WMD_DEV_CONTEXT
+                                             *pDevContext, IN void *pArgs);
+
+
 
 #define MAILBOX_FIFOSTATUS(m) (0x80 + 4 * (m))
 
@@ -41,6 +80,8 @@ DSP_STATUS CHNLSM_EnableInterrupt(struct WMD_DEV_CONTEXT *pDevContext)
 	struct CFG_HOSTRES resources;
 	u32 devType;
 	struct IO_MGR *hIOMgr;
+	u32 eventNo;
+	u32 hwStatus;
 
 	DBG_Trace(DBG_ENTER, "CHNLSM_EnableInterrupt(0x%x)\n", pDevContext);
 
@@ -50,68 +91,75 @@ DSP_STATUS CHNLSM_EnableInterrupt(struct WMD_DEV_CONTEXT *pDevContext)
 			     &resources);
 	DEV_GetDevType(pDevContext->hDevObject, &devType);
 	status = DEV_GetIOMgr(pDevContext->hDevObject, &hIOMgr);
-	if (devType == DSP_UNIT) {
-		HW_MBOX_NumMsgGet(resources.dwMboxBase,
-				  MBOX_DSP2ARM, &numMbxMsg);
-		while (numMbxMsg != 0) {
-			HW_MBOX_MsgRead(resources.dwMboxBase,
-					MBOX_DSP2ARM,
-					&mbxValue);
-			numMbxMsg--;
-		}
-		/* clear the DSP mailbox as well...*/
-		HW_MBOX_NumMsgGet(resources.dwMboxBase,
-				  MBOX_ARM2DSP, &numMbxMsg);
-		while (numMbxMsg != 0) {
-			HW_MBOX_MsgRead(resources.dwMboxBase,
-					MBOX_ARM2DSP, &mbxValue);
-			numMbxMsg--;
-			udelay(10);
-
-			HW_MBOX_EventAck(resources.dwMboxBase, MBOX_ARM2DSP,
-					 HW_MBOX_U1_DSP1,
-					 HW_MBOX_INT_NEW_MSG);
-		}
-		/* Enable the new message events on this IRQ line */
-		HW_MBOX_EventEnable(resources.dwMboxBase,
-				    MBOX_DSP2ARM,
-				    MBOX_ARM,
-				    HW_MBOX_INT_NEW_MSG);
-	}
 
-	return status;
+#ifdef OMAP44XX
+       eventNo = ((NOTIFY_SYSTEM_KEY<<16)|NOTIFY_TESLA_EVENTNUMBER);
+
+        notify_enable_event(handle, 0, eventNo);
+
+    if (devType == DSP_UNIT) {
+		notify_restore(KEY, PROCESSOR_TESLA);
+    }
+
+#else
+        if (devType == DSP_UNIT) {
+                hwStatus = HW_MBOX_EventDisable(resources.dwMboxBase,
+                                                MBOX_DSP2ARM,
+                                                MBOX_ARM,
+                                                HW_MBOX_INT_NEW_MSG);
+        }
+#endif
+        return status;
 }
 
+
 DSP_STATUS CHNLSM_DisableInterrupt(struct WMD_DEV_CONTEXT *pDevContext)
 {
-	struct CFG_HOSTRES resources;
+        DSP_STATUS status = DSP_SOK;
+        int  Notifystatus;
+        u32 eventNo;
+        struct CFG_HOSTRES resources;
+        u32 hwStatus;
 
 	DBG_Trace(DBG_ENTER, "CHNLSM_DisableInterrupt(0x%x)\n", pDevContext);
 
 	CFG_GetHostResources((struct CFG_DEVNODE *)DRV_GetFirstDevExtension(),
 			     &resources);
-	HW_MBOX_EventDisable(resources.dwMboxBase, MBOX_DSP2ARM,
+#ifdef OMAP44XX
+
+        eventNo = ((NOTIFY_SYSTEM_KEY<<16)|NOTIFY_TESLA_EVENTNUMBER);
+        notify_disable_event(handle, 0, eventNo);
+		notify_disable(PROCESSOR_TESLA);
+#else
+	
+		HW_MBOX_EventDisable(resources.dwMboxBase, MBOX_DSP2ARM,
 			     MBOX_ARM, HW_MBOX_INT_NEW_MSG);
+#endif
 	return DSP_SOK;
 }
 
 DSP_STATUS CHNLSM_InterruptDSP2(struct WMD_DEV_CONTEXT *pDevContext,
 				u16 wMbVal)
 {
+#ifndef CONFIG_DISABLE_BRIDGE_PM
 #ifdef CONFIG_BRIDGE_DVFS
 	struct dspbridge_platform_data *pdata =
 		omap_dspbridge_dev->dev.platform_data;
 	u32 opplevel = 0;
+#endif
 #endif
 	struct CFG_HOSTRES resources;
 	DSP_STATUS status = DSP_SOK;
 	unsigned long timeout;
 	u32 temp;
+	int  notifyStatus;
 
 	status = CFG_GetHostResources((struct CFG_DEVNODE *)DRV_GetFirstDevExtension(),
 				      &resources);
 	if (DSP_FAILED(status))
 		return DSP_EFAIL;
+#ifdef OMAP_3430
+#ifndef CONFIG_DISABLE_BRIDGE_PM
 #ifdef CONFIG_BRIDGE_DVFS
 	if (pDevContext->dwBrdState == BRD_DSP_HIBERNATION ||
 	    pDevContext->dwBrdState == BRD_HIBERNATION) {
@@ -122,6 +170,7 @@ DSP_STATUS CHNLSM_InterruptDSP2(struct WMD_DEV_CONTEXT *pDevContext,
 				(*pdata->dsp_set_min_opp)(opplevel+1);
 		}
 	}
+#endif
 #endif
 
 	if (pDevContext->dwBrdState == BRD_DSP_HIBERNATION ||
@@ -159,37 +208,48 @@ DSP_STATUS CHNLSM_InterruptDSP2(struct WMD_DEV_CONTEXT *pDevContext,
 			return WMD_E_TIMEOUT;
 		}
 	}
+#else
 	DBG_Trace(DBG_LEVEL3, "writing %x to Mailbox\n",
 		  wMbVal);
 
-	HW_MBOX_MsgWrite(resources.dwMboxBase, MBOX_ARM2DSP,
-			 wMbVal);
+	
+	notifyStatus = notify_sendevent(handle,/*PROC_TESLA*/0,
+                ((NOTIFY_SYSTEM_KEY<<16)|NOTIFY_TESLA_EVENTNUMBER),
+                pDevContext->wIntrVal2Dsp, true);
+#endif
+
 	return DSP_SOK;
 }
 
 bool CHNLSM_ISR(struct WMD_DEV_CONTEXT *pDevContext, bool *pfSchedDPC,
 		u16 *pwIntrVal)
 {
-	struct CFG_HOSTRES resources;
-	u32 numMbxMsg;
-	u32 mbxValue;
 
-	DBG_Trace(DBG_ENTER, "CHNLSM_ISR(0x%x)\n", pDevContext);
+        bool fMyInterrupt = true;       
+#ifdef OMAP_3430
+        struct CFG_HOSTRES resources;
+        u32 numMbxMsg;
+        u32 mbxValue;
 
-	CFG_GetHostResources((struct CFG_DEVNODE *)DRV_GetFirstDevExtension(), &resources);
+        CFG_GetHostResources(
+                (struct CFG_DEVNODE *)DRV_GetFirstDevExtension(), &resources);
 
-	HW_MBOX_NumMsgGet(resources.dwMboxBase, MBOX_DSP2ARM, &numMbxMsg);
+        HW_MBOX_NumMsgGet(resources.dwMboxBase, MBOX_DSP2ARM, &numMbxMsg);
+
+        if (numMbxMsg > 0) {
+                HW_MBOX_MsgRead(resources.dwMboxBase, MBOX_DSP2ARM, &mbxValue);
+
+                HW_MBOX_EventAck(resources.dwMboxBase, MBOX_DSP2ARM,
+                                 HW_MBOX_U0_ARM, HW_MBOX_INT_NEW_MSG);
+
+                DBG_Trace(DBG_LEVEL3, "Read %x from Mailbox\n", mbxValue);
+                *pwIntrVal = (u16) mbxValue;
+        }
+        /* Set *pfSchedDPC to true; */
+        *pfSchedDPC = true;
+#endif
+        return fMyInterrupt;
 
-	if (numMbxMsg > 0) {
-		HW_MBOX_MsgRead(resources.dwMboxBase, MBOX_DSP2ARM, &mbxValue);
 
-		HW_MBOX_EventAck(resources.dwMboxBase, MBOX_DSP2ARM,
-				 HW_MBOX_U0_ARM, HW_MBOX_INT_NEW_MSG);
 
-		DBG_Trace(DBG_LEVEL3, "Read %x from Mailbox\n", mbxValue);
-		*pwIntrVal = (u16) mbxValue;
-	}
-	/* Set *pfSchedDPC to true; */
-	*pfSchedDPC = true;
-	return true;
 }

drivers/dsp/bridge/wmd/ue_deh.c

@@ -62,6 +62,11 @@
 #include <hw_defs.h>
 #include <hw_mmu.h>
 
+/*--------------------------------------Notify*/
+#include <syslink/notify.h>
+#include <syslink/notify_driverdefs.h>
+
+
 /*  ----------------------------------- This */
 #include "mmu_fault.h"
 #include "_tiomap.h"
@@ -70,6 +75,9 @@
 #include "_tiomap_pwr.h"
 #include <dspbridge/io_sm.h>
 
+extern struct notify_driver_handle *handlePtr;
+
+
 static struct HW_MMUMapAttrs_t  mapAttrs = { HW_LITTLE_ENDIAN,
 					HW_ELEM_SIZE_16BIT,
 					HW_MMU_CPUES} ;
@@ -208,6 +216,7 @@ void WMD_DEH_Notify(struct DEH_MGR *hDehMgr, u32 ulEventMask,
 	u32 extern faultAddr;
 	struct CFG_HOSTRES resources;
 	HW_STATUS hwStatus;
+	u32 NotifyStatus;
 
 	status = CFG_GetHostResources(
 			(struct CFG_DEVNODE *)DRV_GetFirstDevExtension(),
@@ -275,8 +284,16 @@ DBG_Trace(DBG_LEVEL6, "WMD_DEH_Notify: DSP_MMUFAULT, "
 					HW_SET, HW_SET);
 			}
 			/* send an interrupt to DSP */
+#ifdef OMAP_3430
 			HW_MBOX_MsgWrite(resources.dwMboxBase, MBOX_ARM2DSP,
 					 MBX_DEH_CLASS | MBX_DEH_EMMU);
+			
+#else
+			 NotifyStatus = notify_sendevent(handlePtr,/*PROC_TESLA*/0,
+                                 /*eventNo*/4,MBX_DEH_CLASS | MBX_DEH_EMMU,true);
+#endif
+			
+					 
 			/* Clear MMU interrupt */
 			HW_MMU_EventAck(resources.dwDmmuBase,
 					 HW_MMU_TRANSLATION_FAULT);