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Commit 66768eb2 authored by Al Viro's avatar Al Viro Committed by Linus Torvalds
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[PATCH] ppc-opc NULL noise removal 

Signed-off-by: default avatarAl Viro <viro@parcelfarce.linux.theplanet.co.uk>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 0d3e8fe6
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Showing with 60 additions and 59 deletions
arch/ppc64/xmon/ppc-opc.c
View file @ 66768eb2
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
Software Foundation, 59 Temple Place - Suite 330, Boston, MA Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */ 02111-1307, USA. */
#include <linux/stddef.h>
#include "nonstdio.h" #include "nonstdio.h"
#include "ppc.h" #include "ppc.h"
...@@ -110,12 +111,12 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -110,12 +111,12 @@ const struct powerpc_operand powerpc_operands[] =
/* The zero index is used to indicate the end of the list of /* The zero index is used to indicate the end of the list of
operands. */ operands. */
#define UNUSED 0 #define UNUSED 0
{ 0, 0, 0, 0, 0 }, { 0, 0, NULL, NULL, 0 },
/* The BA field in an XL form instruction. */ /* The BA field in an XL form instruction. */
#define BA UNUSED + 1 #define BA UNUSED + 1
#define BA_MASK (0x1f << 16) #define BA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_CR }, { 5, 16, NULL, NULL, PPC_OPERAND_CR },
/* The BA field in an XL form instruction when it must be the same /* The BA field in an XL form instruction when it must be the same
as the BT field in the same instruction. */ as the BT field in the same instruction. */
...@@ -125,7 +126,7 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -125,7 +126,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The BB field in an XL form instruction. */ /* The BB field in an XL form instruction. */
#define BB BAT + 1 #define BB BAT + 1
#define BB_MASK (0x1f << 11) #define BB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_CR }, { 5, 11, NULL, NULL, PPC_OPERAND_CR },
/* The BB field in an XL form instruction when it must be the same /* The BB field in an XL form instruction when it must be the same
as the BA field in the same instruction. */ as the BA field in the same instruction. */
...@@ -168,21 +169,21 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -168,21 +169,21 @@ const struct powerpc_operand powerpc_operands[] =
/* The BF field in an X or XL form instruction. */ /* The BF field in an X or XL form instruction. */
#define BF BDPA + 1 #define BF BDPA + 1
{ 3, 23, 0, 0, PPC_OPERAND_CR }, { 3, 23, NULL, NULL, PPC_OPERAND_CR },
/* An optional BF field. This is used for comparison instructions, /* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */ in which an omitted BF field is taken as zero. */
#define OBF BF + 1 #define OBF BF + 1
{ 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */ /* The BFA field in an X or XL form instruction. */
#define BFA OBF + 1 #define BFA OBF + 1
{ 3, 18, 0, 0, PPC_OPERAND_CR }, { 3, 18, NULL, NULL, PPC_OPERAND_CR },
/* The BI field in a B form or XL form instruction. */ /* The BI field in a B form or XL form instruction. */
#define BI BFA + 1 #define BI BFA + 1
#define BI_MASK (0x1f << 16) #define BI_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_CR }, { 5, 16, NULL, NULL, PPC_OPERAND_CR },
/* The BO field in a B form instruction. Certain values are /* The BO field in a B form instruction. Certain values are
illegal. */ illegal. */
...@@ -197,36 +198,36 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -197,36 +198,36 @@ const struct powerpc_operand powerpc_operands[] =
/* The BT field in an X or XL form instruction. */ /* The BT field in an X or XL form instruction. */
#define BT BOE + 1 #define BT BOE + 1
{ 5, 21, 0, 0, PPC_OPERAND_CR }, { 5, 21, NULL, NULL, PPC_OPERAND_CR },
/* The condition register number portion of the BI field in a B form /* The condition register number portion of the BI field in a B form
or XL form instruction. This is used for the extended or XL form instruction. This is used for the extended
conditional branch mnemonics, which set the lower two bits of the conditional branch mnemonics, which set the lower two bits of the
BI field. This field is optional. */ BI field. This field is optional. */
#define CR BT + 1 #define CR BT + 1
{ 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The CRB field in an X form instruction. */ /* The CRB field in an X form instruction. */
#define CRB CR + 1 #define CRB CR + 1
{ 5, 6, 0, 0, 0 }, { 5, 6, NULL, NULL, 0 },
/* The CRFD field in an X form instruction. */ /* The CRFD field in an X form instruction. */
#define CRFD CRB + 1 #define CRFD CRB + 1
{ 3, 23, 0, 0, PPC_OPERAND_CR }, { 3, 23, NULL, NULL, PPC_OPERAND_CR },
/* The CRFS field in an X form instruction. */ /* The CRFS field in an X form instruction. */
#define CRFS CRFD + 1 #define CRFS CRFD + 1
{ 3, 0, 0, 0, PPC_OPERAND_CR }, { 3, 0, NULL, NULL, PPC_OPERAND_CR },
/* The CT field in an X form instruction. */ /* The CT field in an X form instruction. */
#define CT CRFS + 1 #define CT CRFS + 1
{ 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off /* The D field in a D form instruction. This is a displacement off
a register, and implies that the next operand is a register in a register, and implies that the next operand is a register in
parentheses. */ parentheses. */
#define D CT + 1 #define D CT + 1
{ 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The DE field in a DE form instruction. This is like D, but is 12 /* The DE field in a DE form instruction. This is like D, but is 12
bits only. */ bits only. */
...@@ -252,40 +253,40 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -252,40 +253,40 @@ const struct powerpc_operand powerpc_operands[] =
/* The E field in a wrteei instruction. */ /* The E field in a wrteei instruction. */
#define E DS + 1 #define E DS + 1
{ 1, 15, 0, 0, 0 }, { 1, 15, NULL, NULL, 0 },
/* The FL1 field in a POWER SC form instruction. */ /* The FL1 field in a POWER SC form instruction. */
#define FL1 E + 1 #define FL1 E + 1
{ 4, 12, 0, 0, 0 }, { 4, 12, NULL, NULL, 0 },
/* The FL2 field in a POWER SC form instruction. */ /* The FL2 field in a POWER SC form instruction. */
#define FL2 FL1 + 1 #define FL2 FL1 + 1
{ 3, 2, 0, 0, 0 }, { 3, 2, NULL, NULL, 0 },
/* The FLM field in an XFL form instruction. */ /* The FLM field in an XFL form instruction. */
#define FLM FL2 + 1 #define FLM FL2 + 1
{ 8, 17, 0, 0, 0 }, { 8, 17, NULL, NULL, 0 },
/* The FRA field in an X or A form instruction. */ /* The FRA field in an X or A form instruction. */
#define FRA FLM + 1 #define FRA FLM + 1
#define FRA_MASK (0x1f << 16) #define FRA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_FPR }, { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
/* The FRB field in an X or A form instruction. */ /* The FRB field in an X or A form instruction. */
#define FRB FRA + 1 #define FRB FRA + 1
#define FRB_MASK (0x1f << 11) #define FRB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_FPR }, { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
/* The FRC field in an A form instruction. */ /* The FRC field in an A form instruction. */
#define FRC FRB + 1 #define FRC FRB + 1
#define FRC_MASK (0x1f << 6) #define FRC_MASK (0x1f << 6)
{ 5, 6, 0, 0, PPC_OPERAND_FPR }, { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
/* The FRS field in an X form instruction or the FRT field in a D, X /* The FRS field in an X form instruction or the FRT field in a D, X
or A form instruction. */ or A form instruction. */
#define FRS FRC + 1 #define FRS FRC + 1
#define FRT FRS #define FRT FRS
{ 5, 21, 0, 0, PPC_OPERAND_FPR }, { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
/* The FXM field in an XFX instruction. */ /* The FXM field in an XFX instruction. */
#define FXM FRS + 1 #define FXM FRS + 1
...@@ -298,11 +299,11 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -298,11 +299,11 @@ const struct powerpc_operand powerpc_operands[] =
/* The L field in a D or X form instruction. */ /* The L field in a D or X form instruction. */
#define L FXM4 + 1 #define L FXM4 + 1
{ 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The LEV field in a POWER SC form instruction. */ /* The LEV field in a POWER SC form instruction. */
#define LEV L + 1 #define LEV L + 1
{ 7, 5, 0, 0, 0 }, { 7, 5, NULL, NULL, 0 },
/* The LI field in an I form instruction. The lower two bits are /* The LI field in an I form instruction. The lower two bits are
forced to zero. */ forced to zero. */
...@@ -316,24 +317,24 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -316,24 +317,24 @@ const struct powerpc_operand powerpc_operands[] =
/* The LS field in an X (sync) form instruction. */ /* The LS field in an X (sync) form instruction. */
#define LS LIA + 1 #define LS LIA + 1
{ 2, 21, 0, 0, PPC_OPERAND_OPTIONAL }, { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The MB field in an M form instruction. */ /* The MB field in an M form instruction. */
#define MB LS + 1 #define MB LS + 1
#define MB_MASK (0x1f << 6) #define MB_MASK (0x1f << 6)
{ 5, 6, 0, 0, 0 }, { 5, 6, NULL, NULL, 0 },
/* The ME field in an M form instruction. */ /* The ME field in an M form instruction. */
#define ME MB + 1 #define ME MB + 1
#define ME_MASK (0x1f << 1) #define ME_MASK (0x1f << 1)
{ 5, 1, 0, 0, 0 }, { 5, 1, NULL, NULL, 0 },
/* The MB and ME fields in an M form instruction expressed a single /* The MB and ME fields in an M form instruction expressed a single
operand which is a bitmask indicating which bits to select. This operand which is a bitmask indicating which bits to select. This
is a two operand form using PPC_OPERAND_NEXT. See the is a two operand form using PPC_OPERAND_NEXT. See the
description in opcode/ppc.h for what this means. */ description in opcode/ppc.h for what this means. */
#define MBE ME + 1 #define MBE ME + 1
{ 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
{ 32, 0, insert_mbe, extract_mbe, 0 }, { 32, 0, insert_mbe, extract_mbe, 0 },
/* The MB or ME field in an MD or MDS form instruction. The high /* The MB or ME field in an MD or MDS form instruction. The high
...@@ -345,7 +346,7 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -345,7 +346,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The MO field in an mbar instruction. */ /* The MO field in an mbar instruction. */
#define MO MB6 + 1 #define MO MB6 + 1
{ 5, 21, 0, 0, 0 }, { 5, 21, NULL, NULL, 0 },
/* The NB field in an X form instruction. The value 32 is stored as /* The NB field in an X form instruction. The value 32 is stored as
0. */ 0. */
...@@ -361,34 +362,34 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -361,34 +362,34 @@ const struct powerpc_operand powerpc_operands[] =
/* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
#define RA NSI + 1 #define RA NSI + 1
#define RA_MASK (0x1f << 16) #define RA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_GPR }, { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
/* The RA field in the DQ form lq instruction, which has special /* The RA field in the DQ form lq instruction, which has special
value restrictions. */ value restrictions. */
#define RAQ RA + 1 #define RAQ RA + 1
{ 5, 16, insert_raq, 0, PPC_OPERAND_GPR }, { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR },
/* The RA field in a D or X form instruction which is an updating /* The RA field in a D or X form instruction which is an updating
load, which means that the RA field may not be zero and may not load, which means that the RA field may not be zero and may not
equal the RT field. */ equal the RT field. */
#define RAL RAQ + 1 #define RAL RAQ + 1
{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR },
/* The RA field in an lmw instruction, which has special value /* The RA field in an lmw instruction, which has special value
restrictions. */ restrictions. */
#define RAM RAL + 1 #define RAM RAL + 1
{ 5, 16, insert_ram, 0, PPC_OPERAND_GPR }, { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR },
/* The RA field in a D or X form instruction which is an updating /* The RA field in a D or X form instruction which is an updating
store or an updating floating point load, which means that the RA store or an updating floating point load, which means that the RA
field may not be zero. */ field may not be zero. */
#define RAS RAM + 1 #define RAS RAM + 1
{ 5, 16, insert_ras, 0, PPC_OPERAND_GPR }, { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR },
/* The RB field in an X, XO, M, or MDS form instruction. */ /* The RB field in an X, XO, M, or MDS form instruction. */
#define RB RAS + 1 #define RB RAS + 1
#define RB_MASK (0x1f << 11) #define RB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_GPR }, { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
/* The RB field in an X form instruction when it must be the same as /* The RB field in an X form instruction when it must be the same as
the RS field in the instruction. This is used for extended the RS field in the instruction. This is used for extended
...@@ -402,22 +403,22 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -402,22 +403,22 @@ const struct powerpc_operand powerpc_operands[] =
#define RS RBS + 1 #define RS RBS + 1
#define RT RS #define RT RS
#define RT_MASK (0x1f << 21) #define RT_MASK (0x1f << 21)
{ 5, 21, 0, 0, PPC_OPERAND_GPR }, { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
/* The RS field of the DS form stq instruction, which has special /* The RS field of the DS form stq instruction, which has special
value restrictions. */ value restrictions. */
#define RSQ RS + 1 #define RSQ RS + 1
{ 5, 21, insert_rsq, 0, PPC_OPERAND_GPR }, { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR },
/* The RT field of the DQ form lq instruction, which has special /* The RT field of the DQ form lq instruction, which has special
value restrictions. */ value restrictions. */
#define RTQ RSQ + 1 #define RTQ RSQ + 1
{ 5, 21, insert_rtq, 0, PPC_OPERAND_GPR }, { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR },
/* The SH field in an X or M form instruction. */ /* The SH field in an X or M form instruction. */
#define SH RTQ + 1 #define SH RTQ + 1
#define SH_MASK (0x1f << 11) #define SH_MASK (0x1f << 11)
{ 5, 11, 0, 0, 0 }, { 5, 11, NULL, NULL, 0 },
/* The SH field in an MD form instruction. This is split. */ /* The SH field in an MD form instruction. This is split. */
#define SH6 SH + 1 #define SH6 SH + 1
...@@ -426,12 +427,12 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -426,12 +427,12 @@ const struct powerpc_operand powerpc_operands[] =
/* The SI field in a D form instruction. */ /* The SI field in a D form instruction. */
#define SI SH6 + 1 #define SI SH6 + 1
{ 16, 0, 0, 0, PPC_OPERAND_SIGNED }, { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
/* The SI field in a D form instruction when we accept a wide range /* The SI field in a D form instruction when we accept a wide range
of positive values. */ of positive values. */
#define SISIGNOPT SI + 1 #define SISIGNOPT SI + 1
{ 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
/* The SPR field in an XFX form instruction. This is flipped--the /* The SPR field in an XFX form instruction. This is flipped--the
lower 5 bits are stored in the upper 5 and vice- versa. */ lower 5 bits are stored in the upper 5 and vice- versa. */
...@@ -443,25 +444,25 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -443,25 +444,25 @@ const struct powerpc_operand powerpc_operands[] =
/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
#define SPRBAT SPR + 1 #define SPRBAT SPR + 1
#define SPRBAT_MASK (0x3 << 17) #define SPRBAT_MASK (0x3 << 17)
{ 2, 17, 0, 0, 0 }, { 2, 17, NULL, NULL, 0 },
/* The SPRG register number in an XFX form m[ft]sprg instruction. */ /* The SPRG register number in an XFX form m[ft]sprg instruction. */
#define SPRG SPRBAT + 1 #define SPRG SPRBAT + 1
#define SPRG_MASK (0x3 << 16) #define SPRG_MASK (0x3 << 16)
{ 2, 16, 0, 0, 0 }, { 2, 16, NULL, NULL, 0 },
/* The SR field in an X form instruction. */ /* The SR field in an X form instruction. */
#define SR SPRG + 1 #define SR SPRG + 1
{ 4, 16, 0, 0, 0 }, { 4, 16, NULL, NULL, 0 },
/* The STRM field in an X AltiVec form instruction. */ /* The STRM field in an X AltiVec form instruction. */
#define STRM SR + 1 #define STRM SR + 1
#define STRM_MASK (0x3 << 21) #define STRM_MASK (0x3 << 21)
{ 2, 21, 0, 0, 0 }, { 2, 21, NULL, NULL, 0 },
/* The SV field in a POWER SC form instruction. */ /* The SV field in a POWER SC form instruction. */
#define SV STRM + 1 #define SV STRM + 1
{ 14, 2, 0, 0, 0 }, { 14, 2, NULL, NULL, 0 },
/* The TBR field in an XFX form instruction. This is like the SPR /* The TBR field in an XFX form instruction. This is like the SPR
field, but it is optional. */ field, but it is optional. */
...@@ -471,52 +472,52 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -471,52 +472,52 @@ const struct powerpc_operand powerpc_operands[] =
/* The TO field in a D or X form instruction. */ /* The TO field in a D or X form instruction. */
#define TO TBR + 1 #define TO TBR + 1
#define TO_MASK (0x1f << 21) #define TO_MASK (0x1f << 21)
{ 5, 21, 0, 0, 0 }, { 5, 21, NULL, NULL, 0 },
/* The U field in an X form instruction. */ /* The U field in an X form instruction. */
#define U TO + 1 #define U TO + 1
{ 4, 12, 0, 0, 0 }, { 4, 12, NULL, NULL, 0 },
/* The UI field in a D form instruction. */ /* The UI field in a D form instruction. */
#define UI U + 1 #define UI U + 1
{ 16, 0, 0, 0, 0 }, { 16, 0, NULL, NULL, 0 },
/* The VA field in a VA, VX or VXR form instruction. */ /* The VA field in a VA, VX or VXR form instruction. */
#define VA UI + 1 #define VA UI + 1
#define VA_MASK (0x1f << 16) #define VA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_VR }, { 5, 16, NULL, NULL, PPC_OPERAND_VR },
/* The VB field in a VA, VX or VXR form instruction. */ /* The VB field in a VA, VX or VXR form instruction. */
#define VB VA + 1 #define VB VA + 1
#define VB_MASK (0x1f << 11) #define VB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_VR }, { 5, 11, NULL, NULL, PPC_OPERAND_VR },
/* The VC field in a VA form instruction. */ /* The VC field in a VA form instruction. */
#define VC VB + 1 #define VC VB + 1
#define VC_MASK (0x1f << 6) #define VC_MASK (0x1f << 6)
{ 5, 6, 0, 0, PPC_OPERAND_VR }, { 5, 6, NULL, NULL, PPC_OPERAND_VR },
/* The VD or VS field in a VA, VX, VXR or X form instruction. */ /* The VD or VS field in a VA, VX, VXR or X form instruction. */
#define VD VC + 1 #define VD VC + 1
#define VS VD #define VS VD
#define VD_MASK (0x1f << 21) #define VD_MASK (0x1f << 21)
{ 5, 21, 0, 0, PPC_OPERAND_VR }, { 5, 21, NULL, NULL, PPC_OPERAND_VR },
/* The SIMM field in a VX form instruction. */ /* The SIMM field in a VX form instruction. */
#define SIMM VD + 1 #define SIMM VD + 1
{ 5, 16, 0, 0, PPC_OPERAND_SIGNED}, { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
/* The UIMM field in a VX form instruction. */ /* The UIMM field in a VX form instruction. */
#define UIMM SIMM + 1 #define UIMM SIMM + 1
{ 5, 16, 0, 0, 0 }, { 5, 16, NULL, NULL, 0 },
/* The SHB field in a VA form instruction. */ /* The SHB field in a VA form instruction. */
#define SHB UIMM + 1 #define SHB UIMM + 1
{ 4, 6, 0, 0, 0 }, { 4, 6, NULL, NULL, 0 },
/* The other UIMM field in a EVX form instruction. */ /* The other UIMM field in a EVX form instruction. */
#define EVUIMM SHB + 1 #define EVUIMM SHB + 1
{ 5, 11, 0, 0, 0 }, { 5, 11, NULL, NULL, 0 },
/* The other UIMM field in a half word EVX form instruction. */ /* The other UIMM field in a half word EVX form instruction. */
#define EVUIMM_2 EVUIMM + 1 #define EVUIMM_2 EVUIMM + 1
...@@ -533,11 +534,11 @@ const struct powerpc_operand powerpc_operands[] = ...@@ -533,11 +534,11 @@ const struct powerpc_operand powerpc_operands[] =
/* The WS field. */ /* The WS field. */
#define WS EVUIMM_8 + 1 #define WS EVUIMM_8 + 1
#define WS_MASK (0x7 << 11) #define WS_MASK (0x7 << 11)
{ 3, 11, 0, 0, 0 }, { 3, 11, NULL, NULL, 0 },
/* The L field in an mtmsrd instruction */ /* The L field in an mtmsrd instruction */
#define MTMSRD_L WS + 1 #define MTMSRD_L WS + 1
{ 1, 16, 0, 0, PPC_OPERAND_OPTIONAL }, { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
}; };
......
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