Commit 592578a1 authored by Richard Retanubun's avatar Richard Retanubun Committed by Greg Ungerer

m68knommu: Fixed GPIO pin initialization for CONFIG_M5271 FEC.

This processor only have one FEC and its MDIO pins are
located at a different offset than the code used for
the current CONFIG_M527x.

Tesed on M5271EVB eval platform.
Without this patch the FEC driver will report no PHY attached
if the bootloader does not pre-initialize the PAR_FECI2C GPIO register.
Signed-off-by: default avatarRichard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent ccc5ff94
...@@ -189,10 +189,15 @@ static void __init m527x_fec_init(void) ...@@ -189,10 +189,15 @@ static void __init m527x_fec_init(void)
m527x_fec_irq_init(0); m527x_fec_irq_init(0);
/* Set multi-function pins to ethernet mode for fec0 */ /* Set multi-function pins to ethernet mode for fec0 */
#if defined(CONFIG_M5271)
v = readb(MCF_IPSBAR + 0x100047);
writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
#else
par = readw(MCF_IPSBAR + 0x100082); par = readw(MCF_IPSBAR + 0x100082);
writew(par | 0xf00, MCF_IPSBAR + 0x100082); writew(par | 0xf00, MCF_IPSBAR + 0x100082);
v = readb(MCF_IPSBAR + 0x100078); v = readb(MCF_IPSBAR + 0x100078);
writeb(v | 0xc0, MCF_IPSBAR + 0x100078); writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
#endif
#ifdef CONFIG_FEC2 #ifdef CONFIG_FEC2
m527x_fec_irq_init(1); m527x_fec_irq_init(1);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment