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linux-davinci
Commit 5250703e authored by Michael Buesch's avatar Michael Buesch Committed by David S. Miller
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b43: Fix PHY register routing 

This fixes the PHY routing bit handling.
This is needed for N-PHY.
No functional change to A-PHY and G-PHY code.
Signed-off-by: default avatarMichael Buesch <mb@bu3sch.de>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 424047e6
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Showing with 145 additions and 114 deletions
drivers/net/wireless/b43/lo.c
View file @ 5250703e
......@@ -555,20 +555,20 @@ struct lo_g_saved_values {
u16 phy_extg_01;
u16 phy_dacctl_hwpctl;
u16 phy_dacctl;
u16 phy_base_14;
u16 phy_cck_14;
u16 phy_hpwr_tssictl;
u16 phy_analogover;
u16 phy_analogoverval;
u16 phy_rfover;
u16 phy_rfoverval;
u16 phy_classctl;
u16 phy_base_3E;
u16 phy_cck_3E;
u16 phy_crs0;
u16 phy_pgactl;
u16 phy_base_2A;
u16 phy_cck_2A;
u16 phy_syncctl;
u16 phy_base_30;
u16 phy_base_06;
u16 phy_cck_30;
u16 phy_cck_06;
/* Radio registers */
u16 radio_43;
......@@ -588,7 +588,7 @@ static void lo_measure_setup(struct b43_wldev *dev,
sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01));
sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL);
sav->phy_base_14 = b43_phy_read(dev, B43_PHY_BASE(0x14));
sav->phy_cck_14 = b43_phy_read(dev, B43_PHY_CCK(0x14));
sav->phy_hpwr_tssictl = b43_phy_read(dev, B43_PHY_HPWR_TSSICTL);
b43_phy_write(dev, B43_PHY_HPWR_TSSICTL,
......@@ -600,14 +600,14 @@ static void lo_measure_setup(struct b43_wldev *dev,
b43_phy_write(dev, B43_PHY_DACCTL,
b43_phy_read(dev, B43_PHY_DACCTL)
| 0x40);
b43_phy_write(dev, B43_PHY_BASE(0x14),
b43_phy_read(dev, B43_PHY_BASE(0x14))
b43_phy_write(dev, B43_PHY_CCK(0x14),
b43_phy_read(dev, B43_PHY_CCK(0x14))
| 0x200);
}
if (phy->type == B43_PHYTYPE_B &&
phy->radio_ver == 0x2050 && phy->radio_rev < 6) {
b43_phy_write(dev, B43_PHY_BASE(0x16), 0x410);
b43_phy_write(dev, B43_PHY_BASE(0x17), 0x820);
b43_phy_write(dev, B43_PHY_CCK(0x16), 0x410);
b43_phy_write(dev, B43_PHY_CCK(0x17), 0x820);
}
if (!lo->rebuild && b43_has_hardware_pctl(phy))
lo_read_power_vector(dev);
......@@ -618,7 +618,7 @@ static void lo_measure_setup(struct b43_wldev *dev,
sav->phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
sav->phy_base_3E = b43_phy_read(dev, B43_PHY_BASE(0x3E));
sav->phy_cck_3E = b43_phy_read(dev, B43_PHY_CCK(0x3E));
sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
b43_phy_write(dev, B43_PHY_CLASSCTL,
......@@ -642,14 +642,14 @@ static void lo_measure_setup(struct b43_wldev *dev,
} else {
b43_phy_write(dev, B43_PHY_RFOVER, 0);
}
b43_phy_write(dev, B43_PHY_BASE(0x3E), 0);
b43_phy_write(dev, B43_PHY_CCK(0x3E), 0);
}
sav->reg_3F4 = b43_read16(dev, 0x3F4);
sav->reg_3E2 = b43_read16(dev, 0x3E2);
sav->radio_43 = b43_radio_read16(dev, 0x43);
sav->radio_7A = b43_radio_read16(dev, 0x7A);
sav->phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
sav->phy_base_2A = b43_phy_read(dev, B43_PHY_BASE(0x2A));
sav->phy_cck_2A = b43_phy_read(dev, B43_PHY_CCK(0x2A));
sav->phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
sav->phy_dacctl = b43_phy_read(dev, B43_PHY_DACCTL);
......@@ -658,10 +658,10 @@ static void lo_measure_setup(struct b43_wldev *dev,
sav->radio_52 &= 0x00F0;
}
if (phy->type == B43_PHYTYPE_B) {
sav->phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30));
sav->phy_base_06 = b43_phy_read(dev, B43_PHY_BASE(0x06));
b43_phy_write(dev, B43_PHY_BASE(0x30), 0x00FF);
b43_phy_write(dev, B43_PHY_BASE(0x06), 0x3F3F);
sav->phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
sav->phy_cck_06 = b43_phy_read(dev, B43_PHY_CCK(0x06));
b43_phy_write(dev, B43_PHY_CCK(0x30), 0x00FF);
b43_phy_write(dev, B43_PHY_CCK(0x06), 0x3F3F);
} else {
b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2)
| 0x8000);
......@@ -670,7 +670,7 @@ static void lo_measure_setup(struct b43_wldev *dev,
& 0xF000);
tmp =
(phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_BASE(0x2E);
(phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_CCK(0x2E);
b43_phy_write(dev, tmp, 0x007F);
tmp = sav->phy_syncctl;
......@@ -678,26 +678,26 @@ static void lo_measure_setup(struct b43_wldev *dev,
tmp = sav->radio_7A;
b43_radio_write16(dev, 0x007A, tmp & 0xFFF0);
b43_phy_write(dev, B43_PHY_BASE(0x2A), 0x8A3);
b43_phy_write(dev, B43_PHY_CCK(0x2A), 0x8A3);
if (phy->type == B43_PHYTYPE_G ||
(phy->type == B43_PHYTYPE_B &&
phy->radio_ver == 0x2050 && phy->radio_rev >= 6)) {
b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1003);
b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1003);
} else
b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x0802);
b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x0802);
if (phy->rev >= 2)
b43_dummy_transmission(dev);
b43_radio_selectchannel(dev, 6, 0);
b43_radio_read16(dev, 0x51); /* dummy read */
if (phy->type == B43_PHYTYPE_G)
b43_phy_write(dev, B43_PHY_BASE(0x2F), 0);
b43_phy_write(dev, B43_PHY_CCK(0x2F), 0);
if (lo->rebuild)
lo_measure_txctl_values(dev);
if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) {
b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078);
} else {
if (phy->type == B43_PHYTYPE_B)
b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8078);
b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078);
else
b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
}
......@@ -732,17 +732,17 @@ static void lo_measure_restore(struct b43_wldev *dev,
}
if (phy->type == B43_PHYTYPE_G) {
if (phy->rev >= 3)
b43_phy_write(dev, B43_PHY_BASE(0x2E), 0xC078);
b43_phy_write(dev, B43_PHY_CCK(0x2E), 0xC078);
else
b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8078);
b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078);
if (phy->rev >= 2)
b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x0202);
b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0202);
else
b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x0101);
b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0101);
}
b43_write16(dev, 0x3F4, sav->reg_3F4);
b43_phy_write(dev, B43_PHY_PGACTL, sav->phy_pgactl);
b43_phy_write(dev, B43_PHY_BASE(0x2A), sav->phy_base_2A);
b43_phy_write(dev, B43_PHY_CCK(0x2A), sav->phy_cck_2A);
b43_phy_write(dev, B43_PHY_SYNCCTL, sav->phy_syncctl);
b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl);
b43_radio_write16(dev, 0x43, sav->radio_43);
......@@ -755,8 +755,8 @@ static void lo_measure_restore(struct b43_wldev *dev,
b43_write16(dev, 0x3E2, sav->reg_3E2);
if (phy->type == B43_PHYTYPE_B &&
phy->radio_ver == 0x2050 && phy->radio_rev <= 5) {
b43_phy_write(dev, B43_PHY_BASE(0x30), sav->phy_base_30);
b43_phy_write(dev, B43_PHY_BASE(0x06), sav->phy_base_06);
b43_phy_write(dev, B43_PHY_CCK(0x30), sav->phy_cck_30);
b43_phy_write(dev, B43_PHY_CCK(0x06), sav->phy_cck_06);
}
if (phy->rev >= 2) {
b43_phy_write(dev, B43_PHY_ANALOGOVER, sav->phy_analogover);
......@@ -765,7 +765,7 @@ static void lo_measure_restore(struct b43_wldev *dev,
b43_phy_write(dev, B43_PHY_CLASSCTL, sav->phy_classctl);
b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover);
b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval);
b43_phy_write(dev, B43_PHY_BASE(0x3E), sav->phy_base_3E);
b43_phy_write(dev, B43_PHY_CCK(0x3E), sav->phy_cck_3E);
b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
}
if (b43_has_hardware_pctl(phy)) {
......@@ -773,7 +773,7 @@ static void lo_measure_restore(struct b43_wldev *dev,
b43_phy_write(dev, B43_PHY_LO_MASK, tmp);
b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01);
b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl_hwpctl);
b43_phy_write(dev, B43_PHY_BASE(0x14), sav->phy_base_14);
b43_phy_write(dev, B43_PHY_CCK(0x14), sav->phy_cck_14);
b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl);
}
b43_radio_selectchannel(dev, sav->old_channel, 1);
......
drivers/net/wireless/b43/phy.c
View file @ 5250703e
......@@ -274,15 +274,30 @@ static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
{
if (phy->type == B43_PHYTYPE_A) {
/* OFDM registers are base-registers for the A-PHY. */
offset &= ~B43_PHYROUTE_OFDM_GPHY;
if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
offset &= ~B43_PHYROUTE;
offset |= B43_PHYROUTE_BASE;
}
}
if (offset & B43_PHYROUTE_EXT_GPHY) {
#if B43_DEBUG
if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
/* Ext-G registers are only available on G-PHYs */
if (phy->type != B43_PHYTYPE_G) {
b43dbg(dev->wl, "EXT-G PHY access at "
"0x%04X on %u type PHY\n", offset, phy->type);
b43err(dev->wl, "Invalid EXT-G PHY access at "
"0x%04X on PHY type %u\n", offset, phy->type);
dump_stack();
}
}
if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
/* N-BMODE registers are only available on N-PHYs */
if (phy->type != B43_PHYTYPE_N) {
b43err(dev->wl, "Invalid N-BMODE PHY access at "
"0x%04X on PHY type %u\n", offset, phy->type);
dump_stack();
}
}
#endif /* B43_DEBUG */
return offset;
}
......@@ -302,7 +317,6 @@ void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
offset = adjust_phyreg_for_phytype(phy, offset, dev);
b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
mmiowb();
b43_write16(dev, B43_MMIO_PHY_DATA, val);
}
......@@ -1273,14 +1287,14 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
}
backup_phy[6] = b43_phy_read(dev, B43_PHY_BASE(0x5A));
backup_phy[7] = b43_phy_read(dev, B43_PHY_BASE(0x59));
backup_phy[8] = b43_phy_read(dev, B43_PHY_BASE(0x58));
backup_phy[9] = b43_phy_read(dev, B43_PHY_BASE(0x0A));
backup_phy[10] = b43_phy_read(dev, B43_PHY_BASE(0x03));
backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
backup_phy[13] = b43_phy_read(dev, B43_PHY_BASE(0x2B));
backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
backup_bband = phy->bbatt.att;
......@@ -1322,12 +1336,12 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
(b43_phy_read(dev, B43_PHY_RFOVERVAL)
& 0xFFCF) | 0x10);
b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0780);
b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
b43_phy_write(dev, B43_PHY_BASE(0x0A),
b43_phy_read(dev, B43_PHY_BASE(0x0A)) | 0x2000);
b43_phy_write(dev, B43_PHY_CCK(0x0A),
b43_phy_read(dev, B43_PHY_CCK(0x0A)) | 0x2000);
if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
b43_phy_write(dev, B43_PHY_ANALOGOVER,
b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
......@@ -1335,8 +1349,8 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
b43_phy_read(dev,
B43_PHY_ANALOGOVERVAL) & 0xFFFB);
}
b43_phy_write(dev, B43_PHY_BASE(0x03),
(b43_phy_read(dev, B43_PHY_BASE(0x03))
b43_phy_write(dev, B43_PHY_CCK(0x03),
(b43_phy_read(dev, B43_PHY_CCK(0x03))
& 0xFF9F) | 0x40);
if (phy->radio_rev == 8) {
......@@ -1354,11 +1368,11 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
b43_phy_write(dev, B43_PHY_LO_CTL, 0);
b43_phy_write(dev, B43_PHY_BASE(0x2B),
(b43_phy_read(dev, B43_PHY_BASE(0x2B))
b43_phy_write(dev, B43_PHY_CCK(0x2B),
(b43_phy_read(dev, B43_PHY_CCK(0x2B))
& 0xFFC0) | 0x01);
b43_phy_write(dev, B43_PHY_BASE(0x2B),
(b43_phy_read(dev, B43_PHY_BASE(0x2B))
b43_phy_write(dev, B43_PHY_CCK(0x2B),
(b43_phy_read(dev, B43_PHY_CCK(0x2B))
& 0xC0FF) | 0x800);
b43_phy_write(dev, B43_PHY_RFOVER,
......@@ -1429,14 +1443,14 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
}
b43_phy_write(dev, B43_PHY_BASE(0x5A), backup_phy[6]);
b43_phy_write(dev, B43_PHY_BASE(0x59), backup_phy[7]);
b43_phy_write(dev, B43_PHY_BASE(0x58), backup_phy[8]);
b43_phy_write(dev, B43_PHY_BASE(0x0A), backup_phy[9]);
b43_phy_write(dev, B43_PHY_BASE(0x03), backup_phy[10]);
b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
b43_phy_write(dev, B43_PHY_BASE(0x2B), backup_phy[13]);
b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
b43_phy_set_baseband_attenuation(dev, backup_bband);
......@@ -1528,19 +1542,19 @@ static void b43_phy_initg(struct b43_wldev *dev)
| phy->lo_control->tx_bias);
}
if (phy->rev >= 6) {
b43_phy_write(dev, B43_PHY_BASE(0x36),
(b43_phy_read(dev, B43_PHY_BASE(0x36))
b43_phy_write(dev, B43_PHY_CCK(0x36),
(b43_phy_read(dev, B43_PHY_CCK(0x36))
& 0x0FFF) | (phy->lo_control->
tx_bias << 12));
}
if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8075);
b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
else
b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x807F);
b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
if (phy->rev < 2)
b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x101);
b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
else
b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x202);
b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
}
if (phy->gmode || phy->rev >= 2) {
b43_lo_g_adjust(dev);
......@@ -2168,9 +2182,12 @@ u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
{
struct b43_phy *phy = &dev->phy;
/* Offset 1 is a 32-bit register. */
B43_WARN_ON(offset == 1);
switch (phy->type) {
case B43_PHYTYPE_A:
offset |= 0x0040;
offset |= 0x40;
break;
case B43_PHYTYPE_B:
if (phy->radio_ver == 0x2053) {
......@@ -2186,6 +2203,14 @@ u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
case B43_PHYTYPE_G:
offset |= 0x80;
break;
case B43_PHYTYPE_N:
offset |= 0x100;
break;
case B43_PHYTYPE_LP:
/* No adjustment required. */
break;
default:
B43_WARN_ON(1);
}
b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
......@@ -2194,8 +2219,10 @@ u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
{
/* Offset 1 is a 32-bit register. */
B43_WARN_ON(offset == 1);
b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
mmiowb();
b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
}
......@@ -3480,10 +3507,10 @@ struct init2050_saved_values {
u16 radio_52;
/* PHY registers */
u16 phy_pgactl;
u16 phy_base_5A;
u16 phy_base_59;
u16 phy_base_58;
u16 phy_base_30;
u16 phy_cck_5A;
u16 phy_cck_59;
u16 phy_cck_58;
u16 phy_cck_30;
u16 phy_rfover;
u16 phy_rfoverval;
u16 phy_analogover;
......@@ -3511,15 +3538,15 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
sav.radio_51 = b43_radio_read16(dev, 0x51);
sav.radio_52 = b43_radio_read16(dev, 0x52);
sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
sav.phy_base_5A = b43_phy_read(dev, B43_PHY_BASE(0x5A));
sav.phy_base_59 = b43_phy_read(dev, B43_PHY_BASE(0x59));
sav.phy_base_58 = b43_phy_read(dev, B43_PHY_BASE(0x58));
sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
if (phy->type == B43_PHYTYPE_B) {
sav.phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30));
sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
sav.reg_3EC = b43_read16(dev, 0x3EC);
b43_phy_write(dev, B43_PHY_BASE(0x30), 0xFF);
b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
b43_write16(dev, 0x3EC, 0x3F3F);
} else if (phy->gmode || phy->rev >= 2) {
sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
......@@ -3570,8 +3597,8 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
b43_write16(dev, 0x03E6, 0x0122);
} else {
if (phy->analog >= 2) {
b43_phy_write(dev, B43_PHY_BASE(0x03),
(b43_phy_read(dev, B43_PHY_BASE(0x03))
b43_phy_write(dev, B43_PHY_CCK(0x03),
(b43_phy_read(dev, B43_PHY_CCK(0x03))
& 0xFFBF) | 0x40);
}
b43_write16(dev, B43_MMIO_CHANNEL_EXT,
......@@ -3588,7 +3615,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
LPD(0, 1, 1)));
}
b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1403);
b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
if (phy->gmode || phy->rev >= 2) {
b43_phy_write(dev, B43_PHY_RFOVERVAL,
radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
......@@ -3604,12 +3631,12 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
& 0xFFF0) | 0x0009);
}
b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
for (i = 0; i < 16; i++) {
b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0480);
b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
if (phy->gmode || phy->rev >= 2) {
b43_phy_write(dev, B43_PHY_RFOVERVAL,
radio2050_rfover_val(dev,
......@@ -3635,7 +3662,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
udelay(20);
tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
if (phy->gmode || phy->rev >= 2) {
b43_phy_write(dev, B43_PHY_RFOVERVAL,
radio2050_rfover_val(dev,
......@@ -3646,7 +3673,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
}
udelay(10);
b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
tmp1++;
tmp1 >>= 9;
......@@ -3655,9 +3682,9 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
b43_radio_write16(dev, 0x78, radio78);
udelay(10);
for (j = 0; j < 16; j++) {
b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0D80);
b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
if (phy->gmode || phy->rev >= 2) {
b43_phy_write(dev, B43_PHY_RFOVERVAL,
radio2050_rfover_val(dev,
......@@ -3686,7 +3713,7 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
udelay(10);
tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
if (phy->gmode || phy->rev >= 2) {
b43_phy_write(dev, B43_PHY_RFOVERVAL,
radio2050_rfover_val(dev,
......@@ -3707,16 +3734,16 @@ u16 b43_radio_init2050(struct b43_wldev *dev)
b43_radio_write16(dev, 0x51, sav.radio_51);
b43_radio_write16(dev, 0x52, sav.radio_52);
b43_radio_write16(dev, 0x43, sav.radio_43);
b43_phy_write(dev, B43_PHY_BASE(0x5A), sav.phy_base_5A);
b43_phy_write(dev, B43_PHY_BASE(0x59), sav.phy_base_59);
b43_phy_write(dev, B43_PHY_BASE(0x58), sav.phy_base_58);
b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
b43_write16(dev, 0x3E6, sav.reg_3E6);
if (phy->analog != 0)
b43_write16(dev, 0x3F4, sav.reg_3F4);
b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
b43_synth_pu_workaround(dev, phy->channel);
if (phy->type == B43_PHYTYPE_B) {
b43_phy_write(dev, B43_PHY_BASE(0x30), sav.phy_base_30);
b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
b43_write16(dev, 0x3EC, sav.reg_3EC);
} else if (phy->gmode) {
b43_write16(dev, B43_MMIO_PHY_RADIO,
......
drivers/net/wireless/b43/phy.h
View file @ 5250703e
......@@ -9,17 +9,21 @@ struct b43_phy;
/*** PHY Registers ***/
/* Routing */
#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
#define B43_PHYROUTE_N_BMODE 0x3000 /* N-PHY BMODE registers */
/* Base registers. */
#define B43_PHY_BASE(reg) (reg)
#define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */
#define B43_PHYROUTE_BASE 0x0000 /* Base registers */
#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
#define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */
/* CCK (B-PHY) registers. */
#define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE)
/* N-PHY registers. */
#define B43_PHY_N(reg) (reg)
/* OFDM (A) registers of a G-PHY */
#define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE)
/* N-PHY BMODE registers. */
#define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE)
/* OFDM (A-PHY) registers. */
#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
/* Extended G-PHY registers */
/* Extended G-PHY registers. */
#define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY)
/* OFDM (A) PHY Registers */
......@@ -79,20 +83,20 @@ struct b43_phy;
#define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */
/* CCK (B) PHY Registers */
#define B43_PHY_VERSION_CCK B43_PHY_BASE(0x00) /* Versioning register for B-PHY */
#define B43_PHY_CCKBBANDCFG B43_PHY_BASE(0x01) /* Contains antenna 0/1 control bit */
#define B43_PHY_PGACTL B43_PHY_BASE(0x15) /* PGA control */
#define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */
#define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */
#define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */
#define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */
#define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */
#define B43_PHY_PGACTL_UNKNOWN 0xEFA0
#define B43_PHY_FBCTL1 B43_PHY_BASE(0x18) /* Frequency bandwidth control 1 */
#define B43_PHY_ITSSI B43_PHY_BASE(0x29) /* Idle TSSI */
#define B43_PHY_LO_LEAKAGE B43_PHY_BASE(0x2D) /* Measured LO leakage */
#define B43_PHY_ENERGY B43_PHY_BASE(0x33) /* Energy */
#define B43_PHY_SYNCCTL B43_PHY_BASE(0x35)
#define B43_PHY_FBCTL2 B43_PHY_BASE(0x38) /* Frequency bandwidth control 2 */
#define B43_PHY_DACCTL B43_PHY_BASE(0x60) /* DAC control */
#define B43_PHY_RCCALOVER B43_PHY_BASE(0x78) /* RC calibration override */
#define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */
#define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */
#define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */
#define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */
#define B43_PHY_SYNCCTL B43_PHY_CCK(0x35)
#define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */
#define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */
#define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */
/* Extended G-PHY Registers */
#define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */
......
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