SYSLINK:proc-print l4 info and fix tlb entries print

This patch address the following
	- Prints the L4 peripherals that are mapped
	- Renamed peripherals that starts with DSPVA_
	  to DUCATI_
	- Fixed the hw_mmu.c bug in reading RAM and CAM registers
Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>

arch/arm/plat-omap/include/syslink/MMURegAcM.h

@@ -346,7 +346,7 @@
 
 
 #define MMUMMU_CAMReadRegister32(base_address)\
-	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_CAM_OFFSET))
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_READ_CAM_OFFSET))
 
 
 #define MMUMMU_CAMWriteRegister32(base_address, value)\
@@ -357,7 +357,7 @@
 }
 
 #define MMUMMU_RAMReadRegister32(base_address)\
-	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_RAM_OFFSET))
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_READ_RAM_OFFSET))
 
 
 #define MMUMMU_RAMWriteRegister32(base_address, value)\

arch/arm/plat-omap/include/syslink/ducatienabler.h

@@ -28,33 +28,33 @@
 
 /* Define the Peripheral PAs and their Ducati VAs. */
 #define L4_PERIPHERAL_MBOX			0x4A0F4000
-#define DSPVA_PERIPHERAL_MBOX			0xAA0F4000
+#define DUCATI_PERIPHERAL_MBOX			0xAA0F4000
 
 #define L4_PERIPHERAL_I2C1			0x48070000
-#define DSPVA_PERIPHERAL_I2C1			0xA8070000
+#define DUCATI_PERIPHERAL_I2C1			0xA8070000
 #define L4_PERIPHERAL_I2C2			0x48072000
-#define DSPVA_PERIPHERAL_I2C2			0xA8072000
+#define DUCATI_PERIPHERAL_I2C2			0xA8072000
 #define L4_PERIPHERAL_I2C3			0x48060000
-#define DSPVA_PERIPHERAL_I2C3			0xA8060000
+#define DUCATI_PERIPHERAL_I2C3			0xA8060000
 
 #define L4_PERIPHERAL_DMA			0x4A056000
-#define DSPVA_PERIPHERAL_DMA			0xAA056000
+#define DUCATI_PERIPHERAL_DMA			0xAA056000
 
 #define L4_PERIPHERAL_GPIO1			0x4A310000
-#define DSPVA_PERIPHERAL_GPIO1		0xAA310000
+#define DUCATI_PERIPHERAL_GPIO1			0xAA310000
 #define L4_PERIPHERAL_GPIO2			0x48055000
-#define DSPVA_PERIPHERAL_GPIO2		0xA8055000
+#define DUCATI_PERIPHERAL_GPIO2			0xA8055000
 #define L4_PERIPHERAL_GPIO3			0x48057000
-#define DSPVA_PERIPHERAL_GPIO3		0xA8057000
+#define DUCATI_PERIPHERAL_GPIO3			0xA8057000
 
 #define L4_PERIPHERAL_GPTIMER3			0x48034000
-#define DSPVA_PERIPHERAL_GPTIMER3		0xA8034000
+#define DUCATI_PERIPHERAL_GPTIMER3		0xA8034000
 #define L4_PERIPHERAL_GPTIMER4			0x48036000
-#define DSPVA_PERIPHERAL_GPTIMER4		0xA8036000
+#define DUCATI_PERIPHERAL_GPTIMER4		0xA8036000
 #define L4_PERIPHERAL_GPTIMER9			0x48040000
-#define DSPVA_PERIPHERAL_GPTIMER9		0xA8040000
+#define DUCATI_PERIPHERAL_GPTIMER9		0xA8040000
 #define L4_PERIPHERAL_GPTIMER11			0x48088000
-#define DSPVA_PERIPHERAL_GPTIMER11		0xA8088000
+#define DUCATI_PERIPHERAL_GPTIMER11		0xA8088000
 
 
 #define L3_TILER_VIEW0_ADDR			0x60000000
@@ -134,22 +134,23 @@ struct memory_entry {
 
 static const struct mmu_entry l4_map[] = {
 	/*  Mailbox 4KB*/
-	{L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_MBOX, DUCATI_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB},
 	/* I2C 4KB each */
-	{L4_PERIPHERAL_I2C1, DSPVA_PERIPHERAL_I2C1, HW_PAGE_SIZE_4KB},
-	{L4_PERIPHERAL_I2C2, DSPVA_PERIPHERAL_I2C2, HW_PAGE_SIZE_4KB},
-	{L4_PERIPHERAL_I2C3, DSPVA_PERIPHERAL_I2C3, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_I2C1, DUCATI_PERIPHERAL_I2C1, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_I2C2, DUCATI_PERIPHERAL_I2C2, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_I2C3, DUCATI_PERIPHERAL_I2C3, HW_PAGE_SIZE_4KB},
 	/* DMA 4KB */
-	{L4_PERIPHERAL_DMA, DSPVA_PERIPHERAL_DMA, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_DMA, DUCATI_PERIPHERAL_DMA, HW_PAGE_SIZE_4KB},
 	/* GPIO Banks 4KB each */
-	{L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1, HW_PAGE_SIZE_4KB},
-	{L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2, HW_PAGE_SIZE_4KB},
-	{L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPIO1, DUCATI_PERIPHERAL_GPIO1, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPIO2, DUCATI_PERIPHERAL_GPIO2, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPIO3, DUCATI_PERIPHERAL_GPIO3, HW_PAGE_SIZE_4KB},
 	/* GPTimers 4KB each */
-	{L4_PERIPHERAL_GPTIMER3, DSPVA_PERIPHERAL_GPTIMER3, HW_PAGE_SIZE_4KB},
-	{L4_PERIPHERAL_GPTIMER4, DSPVA_PERIPHERAL_GPTIMER4, HW_PAGE_SIZE_4KB},
-	{L4_PERIPHERAL_GPTIMER9, DSPVA_PERIPHERAL_GPTIMER9, HW_PAGE_SIZE_4KB},
-	{L4_PERIPHERAL_GPTIMER11, DSPVA_PERIPHERAL_GPTIMER11, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPTIMER3, DUCATI_PERIPHERAL_GPTIMER3, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPTIMER4, DUCATI_PERIPHERAL_GPTIMER4, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPTIMER9, DUCATI_PERIPHERAL_GPTIMER9, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPTIMER11, DUCATI_PERIPHERAL_GPTIMER11,
+							HW_PAGE_SIZE_4KB},
 };
 
 static const struct  memory_entry l3_memory_regions[] = {

drivers/dsp/syslink/procmgr/proc4430/ducatienabler.c

@@ -1022,7 +1022,7 @@ int  ducati_mmu_init(u32 a_phy_addr)
 	hw_mmu_victim_numset(ducati_mmu_linear_addr,
 						mmu_index_next);
 	printk(KERN_ALERT "  Programming Ducati memory regions\n");
-	printk(KERN_ALERT "================================\n");
+	printk(KERN_ALERT "=========================================\n");
 	for (i = 0; i < num_l3_mem_entries; i++) {
 		printk(KERN_ALERT "VA = [0x%x] of size [0x%x] at PA = [0x%x]\n",
 				l3_memory_regions[i].ul_virt_addr,
@@ -1051,8 +1051,12 @@ int  ducati_mmu_init(u32 a_phy_addr)
 	map_attrs |= DSP_MAPLITTLEENDIAN;
 	map_attrs |= DSP_MAPPHYSICALADDR;
 	map_attrs |= DSP_MAPELEMSIZE32;
-
+	printk(KERN_ALERT "  Programming Ducati L4 peripherals\n");
+	printk(KERN_ALERT "=========================================\n");
 	for (i = 0; i < num_l4_entries; i++) {
+		printk(KERN_INFO "PA [0x%x] VA [0x%x] size [0x%x]\n",
+				l4_map[i].ul_phy_addr, l4_map[i].ul_virt_addr,
+				l4_map[i].ul_size);
 		ret_val = ducati_mem_map(l4_map[i].ul_phy_addr,
 			l4_map[i].ul_virt_addr, l4_map[i].ul_size, map_attrs);
 		if (WARN_ON(ret_val < 0)) {
@@ -1210,7 +1214,7 @@ error_exit:
 				get_order(p_pt_attrs->ls_tbl_alloc_sz));
 	}
 	WARN_ON(1);
-	printk("init_mmu_page_attribs FAILED !!!!!\n");
+	printk(KERN_ALERT "init_mmu_page_attribs FAILED !!!!!\n");
 	return status;
 }
 

drivers/dsp/syslink/procmgr/proc4430/hw_mmu.c

@@ -588,19 +588,19 @@ long hw_mmu_tlb_dump(const u32 base_address, bool shw_inv_entries)
 
 	lockSave = mmu_lckread_reg_32(base_address);
 
-	printk(KERN_ALERT "TLB locked entries = %u, current victim = %u\n",
+	printk(KERN_INFO "TLB locked entries = %u, current victim = %u\n",
 		((lockSave & MMU_MMU_LOCK_BaseValue_MASK)
 		>> MMU_MMU_LOCK_BaseValue_OFFSET),
 		((lockSave & MMU_MMU_LOCK_CurrentVictim_MASK)
 		>> MMU_MMU_LOCK_CurrentVictim_OFFSET));
-
+	printk(KERN_INFO "=============================================\n");
 	for (i = 0; i < NUM_TLB_ENTRIES; i++) {
 		mmu_lck_crnt_vctmwite32(base_address, i);
 		cam = MMUMMU_CAMReadRegister32(base_address);
 		ram = MMUMMU_RAMReadRegister32(base_address);
 
 		if ((cam & 0x4) != 0) {
-			printk(KERN_ALERT "TLB Entry [0x%x]: VA = 0x%x"
+			printk(KERN_INFO "TLB Entry [0x%x]: VA = 0x%x"
 				"PA = 0x%x Protected = 0x%x\n)",
 				i, (cam & MMU_ADDR_MASK), (ram & MMU_ADDR_MASK),
 				(cam & 0x8) ? 1 : 0);