Skip to content

L
linux-davinci
Commit 52378445 authored by Peter Horton's avatar Peter Horton Committed by Ralf Baechle
Browse files
Options

[MIPS] Fix Cobalt PCI cache line sizes 

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c315a2b5
Show whitespace changes
Inline Side-by-side
Showing with 2 additions and 2 deletions
arch/mips/pci/fixup-cobalt.c
View file @ 52378445
......@@ -52,7 +52,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
if (lt < 64)
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
......@@ -69,7 +69,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
* host bridge.
*/
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
/*
* The code described by the comment below has been removed
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment