sdhci: Add support for bus-specific IO memory accessors
Currently the SDHCI driver works with PCI accessors (write{l,b,w} and read{l,b,w}). With this patch drivers may change memory accessors, so that we can support hosts with "weird" IO memory access requirments. For example, in "FSL eSDHC" SDHCI hardware all registers are 32 bit width, with big-endian addressing. That is, readb(0x2f) should turn into readb(0x2c), and readw(0x2c) should be translated to le16_to_cpu(readw(0x2e)). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
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