Commit 3ec2a2b8 authored by Bruce Allan's avatar Bruce Allan Committed by David S. Miller

e1000e: correct flow control thresholds

The flow control thresholds, i.e. high and low watermarks of the Rx
FIFO for when the hardware should transmit PAUSE frames (XON and XOFF,
respectively), need to be tuned for more efficient use of the FIFO.
The logic to set the thresholds for parts that support early-receive
(ERT) was also wrong in that it should check whether jumbo frames are
in use.
Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 918d7197
...@@ -469,6 +469,8 @@ ...@@ -469,6 +469,8 @@
#define AUTO_READ_DONE_TIMEOUT 10 #define AUTO_READ_DONE_TIMEOUT 10
/* Flow Control */ /* Flow Control */
#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
/* Transmit Configuration Word */ /* Transmit Configuration Word */
......
...@@ -2751,23 +2751,25 @@ void e1000e_reset(struct e1000_adapter *adapter) ...@@ -2751,23 +2751,25 @@ void e1000e_reset(struct e1000_adapter *adapter)
/* /*
* flow control settings * flow control settings
* *
* The high water mark must be low enough to fit one full frame * The high water mark must be low enough to fit two full frame
* (or the size used for early receive) above it in the Rx FIFO. * (or the size used for early receive) above it in the Rx FIFO.
* Set it to the lower of: * Set it to the lower of:
* - 90% of the Rx FIFO size, and * - 90% of the Rx FIFO size, and
* - the full Rx FIFO size minus the early receive size (for parts * - the full Rx FIFO size minus the early receive size (for parts
* with ERT support assuming ERT set to E1000_ERT_2048), or * with ERT support assuming ERT set to E1000_ERT_2048), or
* - the full Rx FIFO size minus one full frame * - the full Rx FIFO size minus two full frames
*/ */
if (adapter->flags & FLAG_HAS_ERT) if ((adapter->flags & FLAG_HAS_ERT) &&
(adapter->netdev->mtu > ETH_DATA_LEN))
hwm = min(((pba << 10) * 9 / 10), hwm = min(((pba << 10) * 9 / 10),
((pba << 10) - (E1000_ERT_2048 << 3))); ((pba << 10) - (E1000_ERT_2048 << 3)));
else else
hwm = min(((pba << 10) * 9 / 10), hwm = min(((pba << 10) * 9 / 10),
((pba << 10) - adapter->max_frame_size)); ((pba << 10) - (2 * adapter->max_frame_size)));
fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
fc->low_water = fc->high_water - 8; fc->low_water = (fc->high_water - (2 * adapter->max_frame_size));
fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */
if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
fc->pause_time = 0xFFFF; fc->pause_time = 0xFFFF;
......
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