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linux
linux-davinci
Commits
38310772
Commit
38310772
authored
Apr 26, 2007
by
Tony Lindgren
Browse files
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Merge omap-drivers
parents
74adb813
a043909d
Changes
3
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3 changed files
with
255 additions
and
154 deletions
+255
-154
drivers/char/watchdog/omap_wdt.c
drivers/char/watchdog/omap_wdt.c
+156
-96
drivers/char/watchdog/omap_wdt.h
drivers/char/watchdog/omap_wdt.h
+9
-19
drivers/i2c/busses/i2c-omap.c
drivers/i2c/busses/i2c-omap.c
+90
-39
No files found.
drivers/char/watchdog/omap_wdt.c
View file @
38310772
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Click to expand it.
drivers/char/watchdog/omap_wdt.h
View file @
38310772
...
@@ -30,25 +30,15 @@
...
@@ -30,25 +30,15 @@
#ifndef _OMAP_WATCHDOG_H
#ifndef _OMAP_WATCHDOG_H
#define _OMAP_WATCHDOG_H
#define _OMAP_WATCHDOG_H
#define OMAP1610_WATCHDOG_BASE 0xfffeb000
#define OMAP_WATCHDOG_REV (0x00)
#define OMAP2420_WATCHDOG_BASE 0x48022000
/*WDT Timer 2 */
#define OMAP_WATCHDOG_SYS_CONFIG (0x10)
#define OMAP_WATCHDOG_STATUS (0x14)
#ifdef CONFIG_ARCH_OMAP24XX
#define OMAP_WATCHDOG_CNTRL (0x24)
#define OMAP_WATCHDOG_BASE OMAP2420_WATCHDOG_BASE
#define OMAP_WATCHDOG_CRR (0x28)
#else
#define OMAP_WATCHDOG_LDR (0x2c)
#define OMAP_WATCHDOG_BASE OMAP1610_WATCHDOG_BASE
#define OMAP_WATCHDOG_TGR (0x30)
#define RM_RSTST_WKUP 0
#define OMAP_WATCHDOG_WPS (0x34)
#endif
#define OMAP_WATCHDOG_SPR (0x48)
#define OMAP_WATCHDOG_REV (OMAP_WATCHDOG_BASE + 0x00)
#define OMAP_WATCHDOG_SYS_CONFIG (OMAP_WATCHDOG_BASE + 0x10)
#define OMAP_WATCHDOG_STATUS (OMAP_WATCHDOG_BASE + 0x14)
#define OMAP_WATCHDOG_CNTRL (OMAP_WATCHDOG_BASE + 0x24)
#define OMAP_WATCHDOG_CRR (OMAP_WATCHDOG_BASE + 0x28)
#define OMAP_WATCHDOG_LDR (OMAP_WATCHDOG_BASE + 0x2c)
#define OMAP_WATCHDOG_TGR (OMAP_WATCHDOG_BASE + 0x30)
#define OMAP_WATCHDOG_WPS (OMAP_WATCHDOG_BASE + 0x34)
#define OMAP_WATCHDOG_SPR (OMAP_WATCHDOG_BASE + 0x48)
/* Using the prescaler, the OMAP watchdog could go for many
/* Using the prescaler, the OMAP watchdog could go for many
* months before firing. These limits work without scaling,
* months before firing. These limits work without scaling,
...
...
drivers/i2c/busses/i2c-omap.c
View file @
38310772
...
@@ -2,13 +2,15 @@
...
@@ -2,13 +2,15 @@
* TI OMAP I2C master mode driver
* TI OMAP I2C master mode driver
*
*
* Copyright (C) 2003 MontaVista Software, Inc.
* Copyright (C) 2003 MontaVista Software, Inc.
* Copyright (C) 2004 Texas Instruments.
*
* Updated to work with multiple I2C interfaces on 24xx by
* Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
* Copyright (C) 2005 Nokia Corporation
* Copyright (C) 2005 Nokia Corporation
* Copyright (C) 2004 - 2007 Texas Instruments.
*
*
* Cleaned up by Juha Yrjl <juha.yrjola@nokia.com>
* Originally written by MontaVista Software, Inc.
* Additional contributions by:
* Tony Lindgren <tony@atomide.com>
* Imre Deak <imre.deak@nokia.com>
* Juha Yrjl <juha.yrjola@nokia.com>
* Syed Khasim <x0khasim@ti.com>
*
*
* This program is free software; you can redistribute it and/or modify
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
...
@@ -87,6 +89,7 @@
...
@@ -87,6 +89,7 @@
/* I2C Configuration Register (OMAP_I2C_CON): */
/* I2C Configuration Register (OMAP_I2C_CON): */
#define OMAP_I2C_CON_EN (1 << 15)
/* I2C module enable */
#define OMAP_I2C_CON_EN (1 << 15)
/* I2C module enable */
#define OMAP_I2C_CON_BE (1 << 14)
/* Big endian mode */
#define OMAP_I2C_CON_BE (1 << 14)
/* Big endian mode */
#define OMAP_I2C_CON_OPMODE (1 << 12)
/* High Speed support */
#define OMAP_I2C_CON_STB (1 << 11)
/* Start byte mode (master) */
#define OMAP_I2C_CON_STB (1 << 11)
/* Start byte mode (master) */
#define OMAP_I2C_CON_MST (1 << 10)
/* Master/slave mode */
#define OMAP_I2C_CON_MST (1 << 10)
/* Master/slave mode */
#define OMAP_I2C_CON_TRX (1 << 9)
/* TX/RX mode (master only) */
#define OMAP_I2C_CON_TRX (1 << 9)
/* TX/RX mode (master only) */
...
@@ -95,6 +98,10 @@
...
@@ -95,6 +98,10 @@
#define OMAP_I2C_CON_STP (1 << 1)
/* Stop cond (master only) */
#define OMAP_I2C_CON_STP (1 << 1)
/* Stop cond (master only) */
#define OMAP_I2C_CON_STT (1 << 0)
/* Start condition (master) */
#define OMAP_I2C_CON_STT (1 << 0)
/* Start condition (master) */
/* I2C SCL time value when Master */
#define OMAP_I2C_SCLL_HSSCLL 8
#define OMAP_I2C_SCLH_HSSCLH 8
/* I2C System Test Register (OMAP_I2C_SYSTEST): */
/* I2C System Test Register (OMAP_I2C_SYSTEST): */
#ifdef DEBUG
#ifdef DEBUG
#define OMAP_I2C_SYSTEST_ST_EN (1 << 15)
/* System test enable */
#define OMAP_I2C_SYSTEST_ST_EN (1 << 15)
/* System test enable */
...
@@ -113,12 +120,6 @@
...
@@ -113,12 +120,6 @@
/* I2C System Configuration Register (OMAP_I2C_SYSC): */
/* I2C System Configuration Register (OMAP_I2C_SYSC): */
#define OMAP_I2C_SYSC_SRST (1 << 1)
/* Soft Reset */
#define OMAP_I2C_SYSC_SRST (1 << 1)
/* Soft Reset */
/* REVISIT: Use platform_data instead of module parameters */
/* Fast Mode = 400 kHz, Standard = 100 kHz */
static
int
clock
=
100
;
/* Default: 100 kHz */
module_param
(
clock
,
int
,
0
);
MODULE_PARM_DESC
(
clock
,
"Set I2C clock in kHz: 400=fast mode (default == 100)"
);
struct
omap_i2c_dev
{
struct
omap_i2c_dev
{
struct
device
*
dev
;
struct
device
*
dev
;
void
__iomem
*
base
;
/* virtual */
void
__iomem
*
base
;
/* virtual */
...
@@ -127,6 +128,7 @@ struct omap_i2c_dev {
...
@@ -127,6 +128,7 @@ struct omap_i2c_dev {
struct
clk
*
fclk
;
/* Functional clock */
struct
clk
*
fclk
;
/* Functional clock */
struct
completion
cmd_complete
;
struct
completion
cmd_complete
;
struct
resource
*
ioarea
;
struct
resource
*
ioarea
;
u32
speed
;
/* Speed of bus in Khz */
u16
cmd_err
;
u16
cmd_err
;
u8
*
buf
;
u8
*
buf
;
size_t
buf_len
;
size_t
buf_len
;
...
@@ -154,7 +156,18 @@ static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
...
@@ -154,7 +156,18 @@ static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
return
-
ENODEV
;
return
-
ENODEV
;
}
}
}
}
/* For I2C operations on 2430 we need 96Mhz clock */
if
(
cpu_is_omap2430
())
{
dev
->
fclk
=
clk_get
(
dev
->
dev
,
"i2chs_fck"
);
if
(
IS_ERR
(
dev
->
fclk
))
{
if
(
dev
->
iclk
!=
NULL
)
{
clk_put
(
dev
->
iclk
);
dev
->
iclk
=
NULL
;
}
dev
->
fclk
=
NULL
;
return
-
ENODEV
;
}
}
else
{
dev
->
fclk
=
clk_get
(
dev
->
dev
,
"i2c_fck"
);
dev
->
fclk
=
clk_get
(
dev
->
dev
,
"i2c_fck"
);
if
(
IS_ERR
(
dev
->
fclk
))
{
if
(
IS_ERR
(
dev
->
fclk
))
{
if
(
dev
->
iclk
!=
NULL
)
{
if
(
dev
->
iclk
!=
NULL
)
{
...
@@ -164,7 +177,7 @@ static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
...
@@ -164,7 +177,7 @@ static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
dev
->
fclk
=
NULL
;
dev
->
fclk
=
NULL
;
return
-
ENODEV
;
return
-
ENODEV
;
}
}
}
return
0
;
return
0
;
}
}
...
@@ -194,9 +207,11 @@ static void omap_i2c_disable_clocks(struct omap_i2c_dev *dev)
...
@@ -194,9 +207,11 @@ static void omap_i2c_disable_clocks(struct omap_i2c_dev *dev)
static
int
omap_i2c_init
(
struct
omap_i2c_dev
*
dev
)
static
int
omap_i2c_init
(
struct
omap_i2c_dev
*
dev
)
{
{
u16
psc
=
0
;
u16
psc
=
0
,
scll
=
0
,
sclh
=
0
;
u16
fsscll
=
0
,
fssclh
=
0
,
hsscll
=
0
,
hssclh
=
0
;
unsigned
long
fclk_rate
=
12000000
;
unsigned
long
fclk_rate
=
12000000
;
unsigned
long
timeout
;
unsigned
long
timeout
;
unsigned
long
internal_clk
=
0
;
if
(
!
dev
->
rev1
)
{
if
(
!
dev
->
rev1
)
{
omap_i2c_write_reg
(
dev
,
OMAP_I2C_SYSC_REG
,
OMAP_I2C_SYSC_SRST
);
omap_i2c_write_reg
(
dev
,
OMAP_I2C_SYSC_REG
,
OMAP_I2C_SYSC_SRST
);
...
@@ -239,18 +254,47 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
...
@@ -239,18 +254,47 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
psc
=
fclk_rate
/
12000000
;
psc
=
fclk_rate
/
12000000
;
}
}
/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
if
(
cpu_is_omap2430
())
{
omap_i2c_write_reg
(
dev
,
OMAP_I2C_PSC_REG
,
psc
);
/* HSI2C controller internal clk rate should be 19.2 Mhz */
internal_clk
=
19200
;
fclk_rate
=
clk_get_rate
(
dev
->
fclk
)
/
1000
;
/* Compute prescaler divisor */
psc
=
fclk_rate
/
internal_clk
;
psc
=
psc
-
1
;
/* If configured for High Speed */
if
(
dev
->
speed
>
400
)
{
/* For first phase of HS mode */
fsscll
=
internal_clk
/
(
400
*
2
)
-
6
;
fssclh
=
internal_clk
/
(
400
*
2
)
-
6
;
/* For second phase of HS mode */
hsscll
=
fclk_rate
/
(
dev
->
speed
*
2
)
-
6
;
hssclh
=
fclk_rate
/
(
dev
->
speed
*
2
)
-
6
;
}
else
{
/* To handle F/S modes */
fsscll
=
internal_clk
/
(
dev
->
speed
*
2
)
-
6
;
fssclh
=
internal_clk
/
(
dev
->
speed
*
2
)
-
6
;
}
scll
=
(
hsscll
<<
OMAP_I2C_SCLL_HSSCLL
)
|
fsscll
;
sclh
=
(
hssclh
<<
OMAP_I2C_SCLH_HSSCLH
)
|
fssclh
;
}
else
{
/* Program desired operating rate */
/* Program desired operating rate */
fclk_rate
/=
(
psc
+
1
)
*
1000
;
fclk_rate
/=
(
psc
+
1
)
*
1000
;
if
(
psc
>
2
)
if
(
psc
>
2
)
psc
=
2
;
psc
=
2
;
scll
=
fclk_rate
/
(
dev
->
speed
*
2
)
-
7
+
psc
;
sclh
=
fclk_rate
/
(
dev
->
speed
*
2
)
-
7
+
psc
;
}
/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
omap_i2c_write_reg
(
dev
,
OMAP_I2C_PSC_REG
,
psc
);
omap_i2c_write_reg
(
dev
,
OMAP_I2C_SCLL_REG
,
/* SCL low and high time values */
fclk_rate
/
(
clock
*
2
)
-
7
+
psc
);
omap_i2c_write_reg
(
dev
,
OMAP_I2C_SCLL_REG
,
scll
);
omap_i2c_write_reg
(
dev
,
OMAP_I2C_SCLH_REG
,
omap_i2c_write_reg
(
dev
,
OMAP_I2C_SCLH_REG
,
sclh
);
fclk_rate
/
(
clock
*
2
)
-
7
+
psc
);
/* Take the I2C module out of reset: */
/* Take the I2C module out of reset: */
omap_i2c_write_reg
(
dev
,
OMAP_I2C_CON_REG
,
OMAP_I2C_CON_EN
);
omap_i2c_write_reg
(
dev
,
OMAP_I2C_CON_REG
,
OMAP_I2C_CON_EN
);
...
@@ -335,6 +379,11 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
...
@@ -335,6 +379,11 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
dev
->
cmd_err
=
0
;
dev
->
cmd_err
=
0
;
w
=
OMAP_I2C_CON_EN
|
OMAP_I2C_CON_MST
|
OMAP_I2C_CON_STT
;
w
=
OMAP_I2C_CON_EN
|
OMAP_I2C_CON_MST
|
OMAP_I2C_CON_STT
;
/* High speed configuration */
if
(
dev
->
speed
>
400
)
w
|=
OMAP_I2C_CON_OPMODE
;
if
(
msg
->
flags
&
I2C_M_TEN
)
if
(
msg
->
flags
&
I2C_M_TEN
)
w
|=
OMAP_I2C_CON_XA
;
w
|=
OMAP_I2C_CON_XA
;
if
(
!
(
msg
->
flags
&
I2C_M_RD
))
if
(
!
(
msg
->
flags
&
I2C_M_RD
))
...
@@ -581,6 +630,7 @@ omap_i2c_probe(struct platform_device *pdev)
...
@@ -581,6 +630,7 @@ omap_i2c_probe(struct platform_device *pdev)
struct
i2c_adapter
*
adap
;
struct
i2c_adapter
*
adap
;
struct
resource
*
mem
,
*
irq
,
*
ioarea
;
struct
resource
*
mem
,
*
irq
,
*
ioarea
;
int
r
;
int
r
;
u32
*
speed
=
NULL
;
/* NOTE: driver uses the static register mapping */
/* NOTE: driver uses the static register mapping */
mem
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
mem
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
...
@@ -601,17 +651,18 @@ omap_i2c_probe(struct platform_device *pdev)
...
@@ -601,17 +651,18 @@ omap_i2c_probe(struct platform_device *pdev)
return
-
EBUSY
;
return
-
EBUSY
;
}
}
if
(
clock
>
200
)
clock
=
400
;
/* Fast mode */
else
clock
=
100
;
/* Standard mode */
dev
=
kzalloc
(
sizeof
(
struct
omap_i2c_dev
),
GFP_KERNEL
);
dev
=
kzalloc
(
sizeof
(
struct
omap_i2c_dev
),
GFP_KERNEL
);
if
(
!
dev
)
{
if
(
!
dev
)
{
r
=
-
ENOMEM
;
r
=
-
ENOMEM
;
goto
err_release_region
;
goto
err_release_region
;
}
}
if
(
pdev
->
dev
.
platform_data
!=
NULL
)
speed
=
(
u32
*
)
pdev
->
dev
.
platform_data
;
else
*
speed
=
100
;
/* Defualt speed */
dev
->
speed
=
*
speed
;
dev
->
dev
=
&
pdev
->
dev
;
dev
->
dev
=
&
pdev
->
dev
;
dev
->
irq
=
irq
->
start
;
dev
->
irq
=
irq
->
start
;
dev
->
base
=
(
void
__iomem
*
)
IO_ADDRESS
(
mem
->
start
);
dev
->
base
=
(
void
__iomem
*
)
IO_ADDRESS
(
mem
->
start
);
...
@@ -637,7 +688,7 @@ omap_i2c_probe(struct platform_device *pdev)
...
@@ -637,7 +688,7 @@ omap_i2c_probe(struct platform_device *pdev)
}
}
r
=
omap_i2c_read_reg
(
dev
,
OMAP_I2C_REV_REG
)
&
0xff
;
r
=
omap_i2c_read_reg
(
dev
,
OMAP_I2C_REV_REG
)
&
0xff
;
dev_info
(
dev
->
dev
,
"bus %d rev%d.%d at %d kHz
\n
"
,
dev_info
(
dev
->
dev
,
"bus %d rev%d.%d at %d kHz
\n
"
,
pdev
->
id
,
r
>>
4
,
r
&
0xf
,
clock
);
pdev
->
id
,
r
>>
4
,
r
&
0xf
,
dev
->
speed
);
adap
=
&
dev
->
adapter
;
adap
=
&
dev
->
adapter
;
i2c_set_adapdata
(
adap
,
dev
);
i2c_set_adapdata
(
adap
,
dev
);
...
...
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