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Commit 35189fad authored by Ralf Baechle's avatar Ralf Baechle
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[MIPS] Support for the RM9000-based Basler eXcite smart camera platform. 

Signed-off-by: default avatarThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 355c471f
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arch/mips/Kconfig
View file @ 35189fad
......@@ -119,6 +119,32 @@ config MIPS_MIRAGE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config BASLER_EXCITE
bool "Basler eXcite smart camera support"
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select IRQ_CPU_RM9K
select SERIAL_RM9000
select SYS_HAS_CPU_RM9000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
The eXcite is a smart camera platform manufactured by
Basler Vision Technologies AG
config BASLER_EXCITE_PROTOTYPE
bool "Support for pre-release units"
depends on BASLER_EXCITE
default n
help
Pre-series (prototype) units are different from later ones in
some ways. Select this option if you have one of these. Please
note that a kernel built with this option selected will not be
able to run on normal units.
config MIPS_COBALT
bool "Cobalt Server"
select DMA_NONCOHERENT
......
arch/mips/Makefile
View file @ 35189fad
......@@ -387,6 +387,13 @@ core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/
cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3
load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000
#
# Basler eXcite
#
core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
load-$(CONFIG_BASLER_EXCITE) += 0x80100000
#
# Momentum Jaguar ATX
#
......
arch/mips/basler/excite/Makefile 0 → 100644
View file @ 35189fad
#
# Makefile for Basler eXcite
#
obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
excite_device.o excite_procfs.o
obj-$(CONFIG_KGDB) += excite_dbg_io.o
obj-m += excite_iodev.o
arch/mips/basler/excite/excite_dbg_io.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/gdb-stub.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
#error Debug port used by serial driver
#endif
#define UART_CLK 25000000
#define BASE_BAUD (UART_CLK / 16)
#define REGISTER_BASE_0 0x0208UL
#define REGISTER_BASE_1 0x0238UL
#define REGISTER_BASE_DBG REGISTER_BASE_1
#define CPRR 0x0004
#define UACFG 0x0200
#define UAINTS 0x0204
#define UARBR (REGISTER_BASE_DBG + 0x0000)
#define UATHR (REGISTER_BASE_DBG + 0x0004)
#define UADLL (REGISTER_BASE_DBG + 0x0008)
#define UAIER (REGISTER_BASE_DBG + 0x000c)
#define UADLH (REGISTER_BASE_DBG + 0x0010)
#define UAIIR (REGISTER_BASE_DBG + 0x0014)
#define UAFCR (REGISTER_BASE_DBG + 0x0018)
#define UALCR (REGISTER_BASE_DBG + 0x001c)
#define UAMCR (REGISTER_BASE_DBG + 0x0020)
#define UALSR (REGISTER_BASE_DBG + 0x0024)
#define UAMSR (REGISTER_BASE_DBG + 0x0028)
#define UASCR (REGISTER_BASE_DBG + 0x002c)
#define PARITY_NONE 0
#define PARITY_ODD 0x08
#define PARITY_EVEN 0x18
#define PARITY_MARK 0x28
#define PARITY_SPACE 0x38
#define DATA_5BIT 0x0
#define DATA_6BIT 0x1
#define DATA_7BIT 0x2
#define DATA_8BIT 0x3
#define STOP_1BIT 0x0
#define STOP_2BIT 0x4
#define BAUD_DBG 57600
#define PARITY_DBG PARITY_NONE
#define DATA_DBG DATA_8BIT
#define STOP_DBG STOP_1BIT
/* Initialize the serial port for KGDB debugging */
void __init excite_kgdb_init(void)
{
const u32 divisor = BASE_BAUD / BAUD_DBG;
/* Take the UART out of reset */
titan_writel(0x00ff1cff, CPRR);
titan_writel(0x00000000, UACFG);
titan_writel(0x00000002, UACFG);
titan_writel(0x0, UALCR);
titan_writel(0x0, UAIER);
/* Disable FIFOs */
titan_writel(0x00, UAFCR);
titan_writel(0x80, UALCR);
titan_writel(divisor & 0xff, UADLL);
titan_writel((divisor & 0xff00) >> 8, UADLH);
titan_writel(0x0, UALCR);
titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
/* Enable receiver interrupt */
titan_readl(UARBR);
titan_writel(0x1, UAIER);
}
int getDebugChar(void)
{
while (!(titan_readl(UALSR) & 0x1));
return titan_readl(UARBR);
}
int putDebugChar(int data)
{
while (!(titan_readl(UALSR) & 0x20));
titan_writel(data, UATHR);
return 1;
}
/* KGDB interrupt handler */
asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
{
if (unlikely(
((titan_readl(UAIIR) & 0x7) == 4)
&& ((titan_readl(UARBR) & 0xff) == 0x3)))
set_async_breakpoint(&regs->cp0_epc);
}
arch/mips/basler/excite/excite_device.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ioport.h>
#include <linux/err.h>
#include <linux/jiffies.h>
#include <linux/sched.h>
#include <asm/types.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
#include <rm9k_eth.h>
#include <rm9k_wdt.h>
#include <rm9k_xicap.h>
#include <excite_nandflash.h>
#include "excite_iodev.h"
#define RM9K_GE_UNIT 0
#define XICAP_UNIT 0
#define NAND_UNIT 0
#define DLL_TIMEOUT 3 /* seconds */
#define RINIT(__start__, __end__, __name__, __parent__) { \
.name = __name__ "_0", \
.start = (__start__), \
.end = (__end__), \
.flags = 0, \
.parent = (__parent__) \
}
#define RINIT_IRQ(__irq__, __name__) { \
.name = __name__ "_0", \
.start = (__irq__), \
.end = (__irq__), \
.flags = IORESOURCE_IRQ, \
.parent = NULL \
}
enum {
slice_xicap,
slice_eth
};
static struct resource
excite_ctr_resource = {
.name = "GPI counters",
.start = 0,
.end = 5,
.flags = 0,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_gpislice_resource = {
.name = "GPI slices",
.start = 0,
.end = 1,
.flags = 0,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_mdio_channel_resource = {
.name = "MDIO channels",
.start = 0,
.end = 1,
.flags = 0,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_fifomem_resource = {
.name = "FIFO memory",
.start = 0,
.end = 767,
.flags = 0,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_scram_resource = {
.name = "Scratch RAM",
.start = EXCITE_PHYS_SCRAM,
.end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
.flags = IORESOURCE_MEM,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_fpga_resource = {
.name = "System FPGA",
.start = EXCITE_PHYS_FPGA,
.end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
.flags = IORESOURCE_MEM,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_nand_resource = {
.name = "NAND flash control",
.start = EXCITE_PHYS_NAND,
.end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
.flags = IORESOURCE_MEM,
.parent = NULL,
.sibling = NULL,
.child = NULL
},
excite_titan_resource = {
.name = "TITAN registers",
.start = EXCITE_PHYS_TITAN,
.end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
.flags = IORESOURCE_MEM,
.parent = NULL,
.sibling = NULL,
.child = NULL
};
static void adjust_resources(struct resource *res, unsigned int n)
{
struct resource *p;
const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
| IORESOURCE_IRQ | IORESOURCE_DMA;
for (p = res; p < res + n; p++) {
const struct resource * const parent = p->parent;
if (parent) {
p->start += parent->start;
p->end += parent->start;
p->flags = parent->flags & mask;
}
}
}
#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
static struct resource xicap_rsrc[] = {
RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
};
static struct platform_device xicap_pdev = {
.name = XICAP_NAME,
.id = XICAP_UNIT,
.num_resources = ARRAY_SIZE(xicap_rsrc),
.resource = xicap_rsrc
};
/*
* Create a platform device for the GPI port that receives the
* image data from the embedded camera.
*/
static int __init xicap_devinit(void)
{
unsigned long tend;
u32 reg;
int retval;
adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
/* Power up the slice and configure it. */
reg = titan_readl(CPTC1R);
reg &= ~(0x11100 << slice_xicap);
titan_writel(reg, CPTC1R);
/* Enable slice & DLL. */
reg= titan_readl(CPRR);
reg &= ~(0x00030003 << (slice_xicap * 2));
titan_writel(reg, CPRR);
/* Wait for DLLs to lock */
tend = jiffies + DLL_TIMEOUT * HZ;
while (time_before(jiffies, tend)) {
if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
break;
yield();
}
if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
xicap_pdev.name, DLL_TIMEOUT);
retval = -ETIME;
} else {
/* Register platform device */
retval = platform_device_register(&xicap_pdev);
}
return retval;
}
device_initcall(xicap_devinit);
#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
static struct resource wdt_rsrc[] = {
RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
};
static struct platform_device wdt_pdev = {
.name = WDT_NAME,
.id = -1,
.num_resources = ARRAY_SIZE(wdt_rsrc),
.resource = wdt_rsrc
};
/*
* Create a platform device for the GPI port that receives the
* image data from the embedded camera.
*/
static int __init wdt_devinit(void)
{
adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
return platform_device_register(&wdt_pdev);
}
device_initcall(wdt_devinit);
#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
static struct resource excite_nandflash_rsrc[] = {
RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
};
static struct platform_device excite_nandflash_pdev = {
.name = "excite_nand",
.id = NAND_UNIT,
.num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
.resource = excite_nandflash_rsrc
};
/*
* Create a platform device for the access to the nand-flash
* port
*/
static int __init excite_nandflash_devinit(void)
{
adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
/* nothing to be done here */
/* Register platform device */
return platform_device_register(&excite_nandflash_pdev);
}
device_initcall(excite_nandflash_devinit);
static struct resource iodev_rsrc[] = {
RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
};
static struct platform_device io_pdev = {
.name = IODEV_NAME,
.id = -1,
.num_resources = ARRAY_SIZE(iodev_rsrc),
.resource = iodev_rsrc
};
/*
* Create a platform device for the external I/O ports.
*/
static int __init io_devinit(void)
{
adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
return platform_device_register(&io_pdev);
}
device_initcall(io_devinit);
#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
static struct resource rm9k_ge_rsrc[] = {
RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
};
static struct platform_device rm9k_ge_pdev = {
.name = RM9K_GE_NAME,
.id = RM9K_GE_UNIT,
.num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
.resource = rm9k_ge_rsrc
};
/*
* Create a platform device for the Ethernet port.
*/
static int __init rm9k_ge_devinit(void)
{
u32 reg;
adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
/* Power up the slice and configure it. */
reg = titan_readl(CPTC1R);
reg &= ~(0x11000 << slice_eth);
reg |= 0x100 << slice_eth;
titan_writel(reg, CPTC1R);
/* Take the MAC out of reset, reset the DLLs. */
reg = titan_readl(CPRR);
reg &= ~(0x00030000 << (slice_eth * 2));
reg |= 0x3 << (slice_eth * 2);
titan_writel(reg, CPRR);
return platform_device_register(&rm9k_ge_pdev);
}
device_initcall(rm9k_ge_devinit);
#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
static int __init excite_setup_devs(void)
{
int res;
u32 reg;
/* Enable xdma and fifo interrupts */
reg = titan_readl(0x0050);
titan_writel(reg | 0x18000000, 0x0050);
res = request_resource(&iomem_resource, &excite_titan_resource);
if (res)
return res;
res = request_resource(&iomem_resource, &excite_scram_resource);
if (res)
return res;
res = request_resource(&iomem_resource, &excite_fpga_resource);
if (res)
return res;
res = request_resource(&iomem_resource, &excite_nand_resource);
if (res)
return res;
excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
( IORESOURCE_IO | IORESOURCE_MEM
| IORESOURCE_IRQ | IORESOURCE_DMA);
excite_nand_resource.flags = excite_nand_resource.parent->flags &
( IORESOURCE_IO | IORESOURCE_MEM
| IORESOURCE_IRQ | IORESOURCE_DMA);
return 0;
}
arch_initcall(excite_setup_devs);
arch/mips/basler/excite/excite_flashtest.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2005 by Basler Vision Technologies AG
* Author: Thies Moeller <thies.moeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <excite.h>
#include <asm/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <asm/rm9k-ocd.h> // for ocd_write
#include <linux/workqueue.h> // for queue
#include "excite_nandflash.h"
#include "nandflash.h"
#define PFX "excite flashtest: "
typedef void __iomem *io_reg_t;
#define io_readb(__a__) __raw_readb((__a__))
#define io_writeb(__v__, __a__) __raw_writeb((__v__), (__a__))
static inline const struct resource *excite_nandflash_get_resource(
struct platform_device *d, unsigned long flags, const char *basename)
{
const char fmt[] = "%s_%u";
char buf[80];
if (unlikely(snprintf(buf, sizeof buf, fmt, basename, d->id) >= sizeof buf))
return NULL;
return platform_get_resource_byname(d, flags, buf);
}
static inline io_reg_t
excite_nandflash_map_regs(struct platform_device *d, const char *basename)
{
void *result = NULL;
const struct resource *const r =
excite_nandflash_get_resource(d, IORESOURCE_MEM, basename);
if (r)
result = ioremap_nocache(r->start, r->end + 1 - r->start);
return result;
}
/* controller and mtd information */
struct excite_nandflash_drvdata {
struct mtd_info board_mtd;
struct nand_chip board_chip;
io_reg_t regs;
};
/* command and control functions */
static void excite_nandflash_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
io_reg_t regs = container_of(mtd,struct excite_nandflash_drvdata,board_mtd)->regs;
switch (cmd) {
/* Select the command latch */
case NAND_CTL_SETCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_CMD;
break;
/* Deselect the command latch */
case NAND_CTL_CLRCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
break;
/* Select the address latch */
case NAND_CTL_SETALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_ADDR;
break;
/* Deselect the address latch */
case NAND_CTL_CLRALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
break;
/* Select the chip -- not used */
case NAND_CTL_SETNCE:
break;
/* Deselect the chip -- not used */
case NAND_CTL_CLRNCE:
break;
}
this->IO_ADDR_R = this->IO_ADDR_W;
}
/* excite_nandflash_devready()
*
* returns 0 if the nand is busy, 1 if it is ready
*/
static int excite_nandflash_devready(struct mtd_info *mtd)
{
struct excite_nandflash_drvdata *drvdata =
container_of(mtd, struct excite_nandflash_drvdata, board_mtd);
return io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
}
/* device management functions */
/* excite_nandflash_remove
*
* called by device layer to remove the driver
* the binding to the mtd and all allocated
* resources are released
*/
static int excite_nandflash_remove(struct device *dev)
{
struct excite_nandflash_drvdata *this = dev_get_drvdata(dev);
pr_info(PFX "remove");
dev_set_drvdata(dev, NULL);
if (this == NULL) {
pr_debug(PFX "call remove without private data!!");
return 0;
}
/* free the common resources */
if (this->regs != NULL) {
iounmap(this->regs);
this->regs = NULL;
}
kfree(this);
return 0;
}
static int elapsed;
void my_workqueue_handler(void *arg)
{
elapsed = 1;
}
DECLARE_WORK(sigElapsed, my_workqueue_handler, 0);
/* excite_nandflash_probe
*
* called by device layer when it finds a device matching
* one our driver can handled. This code checks to see if
* it can allocate all necessary resources then calls the
* nand layer to look for devices
*/
static int excite_nandflash_probe(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct excite_nandflash_drvdata *drvdata; /* private driver data */
struct nand_chip *board_chip; /* private flash chip data */
struct mtd_info *board_mtd; /* mtd info for this board */
int err = 0;
int count = 0;
struct timeval tv,endtv;
unsigned int dt;
pr_info(PFX "probe dev: (%p)\n", dev);
pr_info(PFX "adjust LB timing\n");
ocd_writel(0x00000330, LDP2);
drvdata = kmalloc(sizeof(*drvdata), GFP_KERNEL);
if (unlikely(!drvdata)) {
printk(KERN_ERR PFX "no memory for drvdata\n");
err = -ENOMEM;
goto mem_error;
}
/* Initialize structures */
memset(drvdata, 0, sizeof(*drvdata));
/* bind private data into driver */
dev_set_drvdata(dev, drvdata);
/* allocate and map the resource */
drvdata->regs =
excite_nandflash_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
if (unlikely(!drvdata->regs)) {
printk(KERN_ERR PFX "cannot reserve register region\n");
err = -ENXIO;
goto io_error;
}
/* initialise our chip */
board_chip = &drvdata->board_chip;
board_chip->IO_ADDR_R = drvdata->regs + EXCITE_NANDFLASH_DATA;
board_chip->IO_ADDR_W = drvdata->regs + EXCITE_NANDFLASH_DATA;
board_chip->hwcontrol = excite_nandflash_hwcontrol;
board_chip->dev_ready = excite_nandflash_devready;
board_chip->chip_delay = 25;
#if 0
/* TODO: speedup the initial scan */
board_chip->options = NAND_USE_FLASH_BBT;
#endif
board_chip->eccmode = NAND_ECC_SOFT;
/* link chip to mtd */
board_mtd = &drvdata->board_mtd;
board_mtd->priv = board_chip;
pr_info(PFX "FlashTest\n");
elapsed = 0;
/* schedule_delayed_work(&sigElapsed, 1*HZ);
while (!elapsed) {
io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
count++;
}
pr_info(PFX "reads in 1 sec --> %d\n",count);
*/
do_gettimeofday(&tv);
for (count = 0 ; count < 1000000; count ++) {
io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
}
do_gettimeofday(&endtv);
dt = (endtv.tv_sec - tv.tv_sec) * 1000000 + endtv.tv_usec - tv.tv_usec;
pr_info(PFX "%8d us timeval\n",dt);
pr_info(PFX "EndFlashTest\n");
/* return with error to unload everything
*/
io_error:
iounmap(drvdata->regs);
mem_error:
kfree(drvdata);
if (err == 0)
err = -EINVAL;
return err;
}
static struct device_driver excite_nandflash_driver = {
.name = "excite_nand",
.bus = &platform_bus_type,
.probe = excite_nandflash_probe,
.remove = excite_nandflash_remove,
};
static int __init excite_nandflash_init(void)
{
pr_info(PFX "register Driver (Rev: $Revision:$)\n");
return driver_register(&excite_nandflash_driver);
}
static void __exit excite_nandflash_exit(void)
{
driver_unregister(&excite_nandflash_driver);
pr_info(PFX "Driver unregistered");
}
module_init(excite_nandflash_init);
module_exit(excite_nandflash_exit);
MODULE_AUTHOR("Thies Moeller <thies.moeller@baslerweb.com>");
MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
MODULE_LICENSE("GPL");
arch/mips/basler/excite/excite_fpga.h 0 → 100644
View file @ 35189fad
#ifndef EXCITE_FPGA_H_INCLUDED
#define EXCITE_FPGA_H_INCLUDED
/**
* Adress alignment of the individual FPGA bytes.
* The address arrangement of the individual bytes of the FPGA is two
* byte aligned at the embedded MK2 platform.
*/
#ifdef EXCITE_CCI_FPGA_MK2
typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
#else
typedef unsigned char excite_cci_fpga_align_t;
#endif
/**
* Size of Dual Ported RAM.
*/
#define EXCITE_DPR_SIZE 263
/**
* Size of Reserved Status Fields in Dual Ported RAM.
*/
#define EXCITE_DPR_STATUS_SIZE 7
/**
* FPGA.
* Hardware register layout of the FPGA interface. The FPGA must accessed
* byte wise solely.
* @see EXCITE_CCI_DPR_MK2
*/
typedef struct excite_fpga {
/**
* Dual Ported RAM.
*/
excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
/**
* Status.
*/
excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
#ifdef EXCITE_CCI_FPGA_MK2
/**
* RM9000 Interrupt.
* Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
*/
excite_cci_fpga_align_t rm9k_int;
#else
/**
* MK2 Interrupt.
* Write access initiates interrupt at the ARM processor of the MK2.
*/
excite_cci_fpga_align_t mk2_int;
excite_cci_fpga_align_t gap[0x1000-0x10f];
/**
* IRQ Source/Acknowledge.
*/
excite_cci_fpga_align_t rm9k_irq_src;
/**
* IRQ Mask.
* Set bits enable the related interrupt.
*/
excite_cci_fpga_align_t rm9k_irq_mask;
#endif
} excite_fpga;
#endif /* ndef EXCITE_FPGA_H_INCLUDED */
arch/mips/basler/excite/excite_iodev.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2005 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/poll.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/miscdevice.h>
#include "excite_iodev.h"
static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
static int __init iodev_probe(struct device *);
static int __exit iodev_remove(struct device *);
static int iodev_open(struct inode *, struct file *);
static int iodev_release(struct inode *, struct file *);
static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *);
static const char iodev_name[] = "iodev";
static unsigned int iodev_irq;
static DECLARE_WAIT_QUEUE_HEAD(wq);
static struct file_operations fops =
{
.owner = THIS_MODULE,
.open = iodev_open,
.release = iodev_release,
.read = iodev_read,
.poll = iodev_poll
};
static struct miscdevice miscdev =
{
.minor = MISC_DYNAMIC_MINOR,
.name = iodev_name,
.fops = &fops
};
static struct device_driver iodev_driver =
{
.name = (char *) iodev_name,
.bus = &platform_bus_type,
.owner = THIS_MODULE,
.probe = iodev_probe,
.remove = __exit_p(iodev_remove)
};
static const struct resource *
iodev_get_resource(struct platform_device *pdv, const char *name,
unsigned int type)
{
char buf[80];
if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
return NULL;
return platform_get_resource_byname(pdv, type, buf);
}
/* No hotplugging on the platform bus - use __init */
static int __init iodev_probe(struct device *dev)
{
struct platform_device * const pdv = to_platform_device(dev);
const struct resource * const ri =
iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
if (unlikely(!ri))
return -ENXIO;
iodev_irq = ri->start;
return misc_register(&miscdev);
}
static int __exit iodev_remove(struct device *dev)
{
return misc_deregister(&miscdev);
}
static int iodev_open(struct inode *i, struct file *f)
{
return request_irq(iodev_irq, iodev_irqhdl, SA_INTERRUPT,
iodev_name, &miscdev);
}
static int iodev_release(struct inode *i, struct file *f)
{
free_irq(iodev_irq, &miscdev);
return 0;
}
static ssize_t
iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
{
ssize_t ret;
DEFINE_WAIT(w);
prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
if (!signal_pending(current))
schedule();
ret = signal_pending(current) ? -ERESTARTSYS : 0;
finish_wait(&wq, &w);
return ret;
}
static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
{
poll_wait(f, &wq, p);
return POLLOUT | POLLWRNORM;
}
static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
{
wake_up(&wq);
return IRQ_HANDLED;
}
static int __init iodev_init_module(void)
{
return driver_register(&iodev_driver);
}
static void __exit iodev_cleanup_module(void)
{
driver_unregister(&iodev_driver);
}
module_init(iodev_init_module);
module_exit(iodev_cleanup_module);
MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
MODULE_VERSION("0.0");
MODULE_LICENSE("GPL");
arch/mips/basler/excite/excite_iodev.h 0 → 100644
View file @ 35189fad
#ifndef __EXCITE_IODEV_H__
#define __EXCITE_IODEV_H__
/* Device name */
#define IODEV_NAME "iodev"
/* Resource names */
#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
#endif /* __EXCITE_IODEV_H__ */
arch/mips/basler/excite/excite_irq.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslereb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
extern asmlinkage void excite_handle_int(void);
/*
* Initialize the interrupt handler
*/
void __init arch_init_irq(void)
{
mips_cpu_irq_init(0);
rm7k_cpu_irq_init(8);
rm9k_cpu_irq_init(12);
#ifdef CONFIG_KGDB
excite_kgdb_init();
#endif
}
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
const u32
interrupts = read_c0_cause() >> 8,
mask = ((read_c0_status() >> 8) & 0x000000ff) |
(read_c0_intcontrol() & 0x0000ff00),
pending = interrupts & mask;
u32 msgintflags, msgintmask, msgint;
/* process timer interrupt */
if (pending & (1 << TIMER_IRQ)) {
do_IRQ(TIMER_IRQ, regs);
return;
}
/* Process PCI interrupts */
#if USB_IRQ < 10
msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
if ((pending & (1 << USB_IRQ)) && msgint) {
#else
if (pending & (1 << USB_IRQ)) {
#endif
do_IRQ(USB_IRQ, regs);
return;
}
/* Process TITAN interrupts */
msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
if ((pending & (1 << TITAN_IRQ)) && msgint) {
ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
#if defined(CONFIG_KGDB)
excite_kgdb_inthdl(regs);
#endif
do_IRQ(TITAN_IRQ, regs);
return;
}
/* Process FPGA line #0 interrupts */
msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
if ((pending & (1 << FPGA0_IRQ)) && msgint) {
do_IRQ(FPGA0_IRQ, regs);
return;
}
/* Process FPGA line #1 interrupts */
msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
if ((pending & (1 << FPGA1_IRQ)) && msgint) {
do_IRQ(FPGA1_IRQ, regs);
return;
}
/* Process PHY interrupts */
msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
if ((pending & (1 << PHY_IRQ)) && msgint) {
do_IRQ(PHY_IRQ, regs);
return;
}
/* Process spurious interrupts */
spurious_interrupt(regs);
}
arch/mips/basler/excite/excite_procfs.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2004, 2005 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* Procfs support for Basler eXcite
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/proc_fs.h>
#include <linux/stat.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
static int excite_get_unit_id(char *buf, char **addr, off_t offs, int size)
{
const int len = snprintf(buf, PAGE_SIZE, "%06x", unit_id);
const int w = len - offs;
*addr = buf + offs;
return w < size ? w : size;
}
static int
excite_bootrom_read(char *page, char **start, off_t off, int count,
int *eof, void *data)
{
void __iomem * src;
if (off >= EXCITE_SIZE_BOOTROM) {
*eof = 1;
return 0;
}
if ((off + count) > EXCITE_SIZE_BOOTROM)
count = EXCITE_SIZE_BOOTROM - off;
src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
if (src) {
memcpy_fromio(page, src, count);
iounmap(src);
*start = page;
} else {
count = -ENOMEM;
}
return count;
}
void excite_procfs_init(void)
{
/* Create & populate /proc/excite */
struct proc_dir_entry * const pdir = proc_mkdir("excite", &proc_root);
if (pdir) {
struct proc_dir_entry * e;
e = create_proc_info_entry("unit_id", S_IRUGO, pdir,
excite_get_unit_id);
if (e) e->size = 6;
e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
excite_bootrom_read, NULL);
if (e) e->size = EXCITE_SIZE_BOOTROM;
}
}
arch/mips/basler/excite/excite_prom.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
* Manish Lachwani.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/module.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/string.h>
#include <excite.h>
/* This struct is used by Redboot to pass arguments to the kernel */
typedef struct
{
char *name;
char *val;
} t_env_var;
struct parmblock {
t_env_var memsize;
t_env_var modetty0;
t_env_var ethaddr;
t_env_var env_end;
char *argv[2];
char text[0];
};
static unsigned int prom_argc;
static const char ** prom_argv;
static const t_env_var * prom_env;
static void prom_halt(void) __attribute__((noreturn));
static void prom_exit(void) __attribute__((noreturn));
const char *get_system_type(void)
{
return "Basler eXcite";
}
/*
* Halt the system
*/
static void prom_halt(void)
{
printk(KERN_NOTICE "\n** System halted.\n");
while (1)
asm volatile (
"\t.set\tmips3\n"
"\twait\n"
"\t.set\tmips0\n"
);
}
/*
* Reset the CPU and re-enter Redboot
*/
static void prom_exit(void)
{
unsigned int i;
volatile unsigned char * const flg =
(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
/* Clear the watchdog reset flag, set the reboot flag */
*flg &= ~0x01;
*flg |= 0x80;
for (i = 0; i < 10; i++) {
*(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
iob();
mdelay(1000);
}
printk(KERN_NOTICE "Reset failed\n");
prom_halt();
}
static const char __init *prom_getenv(char *name)
{
const t_env_var * p;
for (p = prom_env; p->name != NULL; p++)
if(strcmp(name, p->name) == 0)
break;
return p->val;
}
/*
* Init routine which accepts the variables from Redboot
*/
void __init prom_init(void)
{
const struct parmblock * const pb = (struct parmblock *) fw_arg2;
prom_argc = fw_arg0;
prom_argv = (const char **) fw_arg1;
prom_env = &pb->memsize;
/* Callbacks for halt, restart */
_machine_restart = (void (*)(char *)) prom_exit;
_machine_halt = prom_halt;
#ifdef CONFIG_32BIT
/* copy command line */
strcpy(arcs_cmdline, prom_argv[1]);
memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
strcpy(modetty, prom_getenv("modetty0"));
#endif /* CONFIG_32BIT */
#ifdef CONFIG_64BIT
# error 64 bit support not implemented
#endif /* CONFIG_64BIT */
mips_machgroup = MACH_GROUP_TITAN;
mips_machtype = MACH_TITAN_EXCITE;
}
/* This is called from free_initmem(), so we need to provide it */
void __init prom_free_prom_memory(void)
{
/* Nothing to do */
}
arch/mips/basler/excite/excite_setup.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2004, 2005 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
* Manish Lachwani.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <asm/pgtable-32.h>
#include <asm/io.h>
#include <asm/time.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
#define TITAN_UART_CLK 25000000
#if 1
/* normal serial port assignment */
#define REGBASE_SER0 0x0208
#define REGBASE_SER1 0x0238
#define MASK_SER0 0x1
#define MASK_SER1 0x2
#else
/* serial ports swapped */
#define REGBASE_SER0 0x0238
#define REGBASE_SER1 0x0208
#define MASK_SER0 0x2
#define MASK_SER1 0x1
#endif
unsigned long memsize;
char modetty[30];
unsigned int titan_irq = TITAN_IRQ;
static void __iomem * ctl_regs;
u32 unit_id;
volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
/* Protect access to shared GPI registers */
spinlock_t titan_lock = SPIN_LOCK_UNLOCKED;
int titan_irqflags;
static void excite_timer_init(void)
{
const u32 modebit5 = ocd_readl(0x00e4);
unsigned int
mult = ((modebit5 >> 11) & 0x1f) + 2,
div = ((modebit5 >> 16) & 0x1f) + 2;
if (div == 33) div = 1;
mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
}
static void excite_timer_setup(struct irqaction *irq)
{
/* The eXcite platform uses the alternate timer interrupt */
set_c0_intcontrol(0x80);
setup_irq(TIMER_IRQ, irq);
}
static int __init excite_init_console(void)
{
#if defined(CONFIG_SERIAL_8250)
static __initdata char serr[] =
KERN_ERR "Serial port #%u setup failed\n";
struct uart_port up;
/* Take the DUART out of reset */
titan_writel(0x00ff1cff, CPRR);
#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
/* Enable both ports */
titan_writel(MASK_SER0 | MASK_SER1, UACFG);
#else
/* Enable port #0 only */
titan_writel(MASK_SER0, UACFG);
#endif /* defined(CONFIG_KGDB) */
/*
* Set up serial port #0. Do not use autodetection; the result is
* not what we want.
*/
memset(&up, 0, sizeof(up));
up.membase = (char *) titan_addr(REGBASE_SER0);
up.irq = TITAN_IRQ;
up.uartclk = TITAN_UART_CLK;
up.regshift = 0;
up.iotype = UPIO_MEM32;
up.type = PORT_RM9000;
up.flags = UPF_SHARE_IRQ;
up.line = 0;
if (early_serial_setup(&up))
printk(serr, up.line);
#if CONFIG_SERIAL_8250_NR_UARTS > 1
/* And now for port #1. */
up.membase = (char *) titan_addr(REGBASE_SER1);
up.line = 1;
if (early_serial_setup(&up))
printk(serr, up.line);
#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
#else
/* Leave the DUART in reset */
titan_writel(0x00ff3cff, CPRR);
#endif /* defined(CONFIG_SERIAL_8250) */
return 0;
}
static int __init excite_platform_init(void)
{
unsigned int i;
unsigned char buf[3];
u8 reg;
void __iomem * dpr;
/* BIU buffer allocations */
ocd_writel(8, CPURSLMT); /* CPU */
titan_writel(4, CPGRWL); /* GPI / Ethernet */
/* Map control registers located in FPGA */
ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
if (!ctl_regs)
panic("eXcite: failed to map platform control registers\n");
memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
/* Clear the reboot flag */
dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
reg = __raw_readb(dpr);
__raw_writeb(reg & 0x7f, dpr);
iounmap(dpr);
/* Interrupt controller setup */
for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
ocd_writel(0x00000000, i + 0x04);
ocd_writel(0xffffffff, i + 0x0c);
}
ocd_writel(0x2, NMICONFIG);
ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
| ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
| ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
ocd_writel((0x1 << (PHY_MSGINT % 0x20))
| ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
#if USB_IRQ < 10
ocd_writel((0x1 << (USB_MSGINT % 0x20))
| ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
#endif
/* Enable the packet FIFO, XDMA and XDMA arbiter */
titan_writel(0x00ff18ff, CPRR);
/*
* Set up the PADMUX. Power down all ethernet slices,
* they will be powered up and configured at device startup.
*/
titan_writel(0x00878206, CPTC1R);
titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
/* Reset and enable the FIFO block */
titan_writel(0x00000001, SDRXFCIE);
titan_writel(0x00000001, SDTXFCIE);
titan_writel(0x00000100, SDRXFCIE);
titan_writel(0x00000000, SDTXFCIE);
/*
* Initialize the common interrupt shared by all components of
* the GPI/Ethernet subsystem.
*/
titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
titan_writel(TITAN_MSGINT, CPCFG1);
/*
* XDMA configuration.
* In order for the XDMA to be sharable among multiple drivers,
* the setup must be done here in the platform. The reason is that
* this setup can only be done while the XDMA is in reset. If this
* were done in a driver, it would interrupt all other drivers
* using the XDMA.
*/
titan_writel(0x80021dff, GXCFG); /* XDMA reset */
titan_writel(0x00000000, CPXCISRA);
titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
#if defined (CONFIG_HIGHMEM)
# error change for HIGHMEM support!
#else
titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
#endif
titan_writel(0, GXDMA_DESCADR);
for (i = 0x5040; i <= 0x5300; i += 0x0040)
titan_writel(0x80080000, i); /* reset channel */
titan_writel((0x1 << 29) /* no sparse tx descr. */
| (0x1 << 28) /* no sparse rx descr. */
| (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
| (0x1 << 21) | (0x1 << 22) /* data coherency */
| (0x1 << 17)
| 0x1dff,
GXCFG);
#if defined(CONFIG_SMP)
# error No SMP support
#else
/* All interrupts go to core #0 only. */
titan_writel(0x1f007fff, CPDST0A);
titan_writel(0x00000000, CPDST0B);
titan_writel(0x0000ff3f, CPDST1A);
titan_writel(0x00000000, CPDST1B);
titan_writel(0x00ffffff, CPXDSTA);
titan_writel(0x00000000, CPXDSTB);
#endif
/* Enable DUART interrupts, disable everything else. */
titan_writel(0x04000000, CPGIG0ER);
titan_writel(0x000000c0, CPGIG1ER);
excite_procfs_init();
return 0;
}
void __init plat_setup(void)
{
volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
/* Announce RAM to system */
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
/* Set up timer initialization hooks */
board_time_init = excite_timer_init;
board_timer_setup = excite_timer_setup;
/* Set up the peripheral address map */
*(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
*(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
*(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
*(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
wmb();
*(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
wmb();
ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
/* Local bus slot #0 */
ocd_writel(0x00040510, LDP0);
ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
/* Local bus slot #2 */
ocd_writel(0x00000330, LDP2);
ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
/* Local bus slot #3 */
ocd_writel(0x00123413, LDP3);
ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
}
console_initcall(excite_init_console);
arch_initcall(excite_platform_init);
EXPORT_SYMBOL(titan_lock);
EXPORT_SYMBOL(titan_irqflags);
EXPORT_SYMBOL(titan_irq);
EXPORT_SYMBOL(ocd_base);
EXPORT_SYMBOL(titan_base);
arch/mips/configs/excite_defconfig 0 → 100644
View file @ 35189fad
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.16-rc4
# Thu Feb 23 13:15:27 2006
#
CONFIG_MIPS=y
#
# Machine selection
#
# CONFIG_MIPS_MTX1 is not set
# CONFIG_MIPS_BOSPORUS is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_MIPS_PB1100 is not set
# CONFIG_MIPS_PB1500 is not set
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_PB1200 is not set
# CONFIG_MIPS_DB1000 is not set
# CONFIG_MIPS_DB1100 is not set
# CONFIG_MIPS_DB1500 is not set
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_LASAT is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
CONFIG_BASLER_EXCITE=y
# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_QEMU is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_TOSHIBA_RBTX4938 is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_DMA_COHERENT=y
CONFIG_SERIAL_RM9000=y
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_IRQ_CPU=y
CONFIG_IRQ_CPU_RM7K=y
CONFIG_IRQ_CPU_RM9K=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
#
# CPU selection
#
# CONFIG_CPU_MIPS32_R1 is not set
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
CONFIG_CPU_RM9000=y
# CONFIG_CPU_SB1 is not set
CONFIG_SYS_HAS_CPU_RM9000=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
#
# Kernel type
#
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_CPU_HAS_PREFETCH=y
# CONFIG_MIPS_MT is not set
# CONFIG_64BIT_PHYS_ADDR is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_SMP is not set
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_BKL=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SHMEM=y
CONFIG_CC_ALIGN_FUNCTIONS=0
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
CONFIG_SLAB=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Block layer
#
# CONFIG_LBD is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_HW_HAS_PCI=y
CONFIG_PCI=y
# CONFIG_PCI_LEGACY_PROC is not set
CONFIG_MMU=y
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# PCI Hotplug Support
#
# CONFIG_HOTPLUG_PCI is not set
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_TRAD_SIGNALS=y
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
# CONFIG_NETDEBUG is not set
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_BIC=y
# CONFIG_IPV6 is not set
# CONFIG_NETFILTER is not set
#
# DCCP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
#
# TIPC Configuration (EXPERIMENTAL)
#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_IEEE80211 is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
#
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_OBSOLETE_CHIPS is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
#
# NAND Flash Device Drivers
#
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_VERIFY_WRITE=y
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
CONFIG_MTD_NAND_BASLER_EXCITE=y
# CONFIG_MTD_NAND_BASLER_EXCITE_RDNBY is not set
# CONFIG_MTD_NAND_BASLER_EXCITE_PERF is not set
# CONFIG_MTD_NAND_NANDSIM is not set
#
# OneNAND Flash Device Drivers
#
# CONFIG_MTD_ONENAND is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=m
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_UB is not set
# CONFIG_BLK_DEV_RAM is not set
CONFIG_BLK_DEV_RAM_COUNT=16
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
#
# SCSI Transport Attributes
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
#
# SCSI low-level drivers
#
# CONFIG_ISCSI_TCP is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_FC is not set
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
# CONFIG_FUSION_SPI is not set
# CONFIG_FUSION_FC is not set
# CONFIG_FUSION_SAS is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# PHY device support
#
#
# Ethernet (10 or 100Mbit)
#
# CONFIG_NET_ETHERNET is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
# CONFIG_TITAN_GE is not set
CONFIG_RM9K_GE=m
#
# Ethernet (10000 Mbit)
#
# CONFIG_CHELSIO_T1 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=m
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_WDT_RM9K_GPI=m
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
# CONFIG_HWMON is not set
# CONFIG_HWMON_VID is not set
#
# Misc devices
#
#
# Multimedia Capabilities Port drivers
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# Graphics support
#
CONFIG_FB=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON_OLD is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_SMIVGX is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_VIRTUAL is not set
CONFIG_FB_DD=y
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=m
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
#
# Logo configuration
#
# CONFIG_LOGO is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_BANDWIDTH is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
#
# USB Host Controller Drivers
#
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_SPLIT_ISO is not set
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# may also be needed; see USB_STORAGE Help for more information
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_LIBUSUAL is not set
#
# USB Input Devices
#
CONFIG_USB_HID=m
CONFIG_USB_HIDINPUT=y
# CONFIG_USB_HIDINPUT_POWERBOOK is not set
# CONFIG_HID_FF is not set
# CONFIG_USB_HIDDEV is not set
#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
# CONFIG_USB_AIPTEK is not set
# CONFIG_USB_WACOM is not set
# CONFIG_USB_ACECAD is not set
# CONFIG_USB_KBTAB is not set
# CONFIG_USB_POWERMATE is not set
# CONFIG_USB_MTOUCH is not set
# CONFIG_USB_ITMTOUCH is not set
# CONFIG_USB_EGALAX is not set
# CONFIG_USB_YEALINK is not set
# CONFIG_USB_XPAD is not set
# CONFIG_USB_ATI_REMOTE is not set
# CONFIG_USB_ATI_REMOTE2 is not set
# CONFIG_USB_KEYSPAN_REMOTE is not set
# CONFIG_USB_APPLETOUCH is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
#
# USB Multimedia devices
#
# CONFIG_USB_DABUSB is not set
#
# Video4Linux support is needed for USB Multimedia device support
#
#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_MON is not set
#
# USB port drivers
#
#
# USB Serial Converter support
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
CONFIG_USB_ARTTFT=m
# CONFIG_USB_ARTTOUCH is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_PHIDGETKIT is not set
# CONFIG_USB_PHIDGETSERVO is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TEST is not set
#
# USB DSL modem support
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# InfiniBand support
#
# CONFIG_INFINIBAND is not set
#
# SN Devices
#
#
# EDAC - error detection and reporting (RAS)
#
#
# eXcite frame capture support
#
CONFIG_EXCITE_FCAP=m
CONFIG_EXCITE_FCAP_GPI=m
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
# CONFIG_QUOTA is not set
# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_RELAYFS_FS is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
CONFIG_NLS_CODEPAGE_850=m
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=m
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
CONFIG_CRYPTO=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_TEST is not set
#
# Hardware crypto devices
#
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
arch/mips/pci/Makefile
View file @ 35189fad
......@@ -23,6 +23,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
#
# These are still pretty much in the old state, watch, go blind.
#
obj-$(CONFIG_BASLER_EXCITE) = ops-titan.o pci-excite.o fixup-excite.o
obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
......
arch/mips/pci/fixup-excite.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <excite.h>
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
if (pin == 0)
return -1;
return USB_IRQ; /* USB controller is the only PCI device */
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
arch/mips/pci/ops-titan.c
View file @ 35189fad
......@@ -26,8 +26,19 @@
#include <linux/pci.h>
#include <linux/kernel.h>
#include <asm/titan_dep.h>
#include <asm/pci.h>
#include <asm/io.h>
#include <asm/rm9k-ocd.h>
/*
* PCI specific defines
*/
#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
#define TITAN_PCI_0_CONFIG_DATA 0x784
/*
* Titan PCI Config Read Byte
*/
static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
int size, u32 * val)
{
......@@ -43,8 +54,8 @@ static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
/* start the configuration cycle */
TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
tmp = TITAN_READ(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
switch (size) {
case 1:
......@@ -71,20 +82,20 @@ static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
(reg & 0xfc) | 0x80000000;
/* start the configuration cycle */
TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
/* write the data */
switch (size) {
case 1:
TITAN_WRITE_8(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3), val);
ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
break;
case 2:
TITAN_WRITE_16(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2), val);
ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
break;
case 4:
TITAN_WRITE(TITAN_PCI_0_CONFIG_DATA, val);
ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
break;
}
......
arch/mips/pci/pci-excite.c 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
extern struct pci_ops titan_pci_ops;
static struct resource
mem_resource = {
.name = "PCI memory",
.start = EXCITE_PHYS_PCI_MEM,
.end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
.flags = IORESOURCE_MEM
},
io_resource = {
.name = "PCI I/O",
.start = EXCITE_PHYS_PCI_IO,
.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
.flags = IORESOURCE_IO
};
static struct pci_controller bx_controller = {
.pci_ops = &titan_pci_ops,
.mem_resource = &mem_resource,
.mem_offset = 0x00000000UL,
.io_resource = &io_resource,
.io_offset = 0x00000000UL
};
static char
iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
#define RM9000x2_OCD_HTSC 0x0604
#define RM9000x2_OCD_HTBHL 0x060c
#define RM9000x2_OCD_PCIHRST 0x078c
#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
#define PCISC_FB2B 0x00000200
#define PCISC_MWICG 0x00000010
#define PCISC_EMC 0x00000004
#define PCISC_ERMA 0x00000002
static int __init basler_excite_pci_setup(void)
{
const unsigned int fullbars = memsize / (256 << 20);
unsigned int i;
/* Check modebits to see if PCI is really enabled. */
if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
panic(modebits_no_pci);
if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
"Memory-mapped PCI I/O page"))
panic(iopage_failed);
/* Enable PCI 0 as master for config cycles */
ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
/* Set up latency timer */
ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
/* Setup host IO and Memory space */
ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
/* Set up PCI BARs to map all installed memory */
for (i = 0; i < 6; i++) {
const unsigned int bar = 0x610 + i * 4;
if (i < fullbars) {
ocd_writel(0x10000000 * i, bar);
ocd_writel(0x01000000 * i, bar + 0x140);
ocd_writel(0x0ffff029, bar + 0x100);
continue;
}
if (i == fullbars) {
int o;
u32 mask;
const unsigned long rem = memsize - i * 0x10000000;
if (!rem) {
ocd_writel(0x00000000, bar + 0x100);
continue;
}
o = ffs(rem) - 1;
if (rem & ~(0x1 << o))
o++;
mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
ocd_writel(0x10000000 * i, bar);
ocd_writel(0x01000000 * i, bar + 0x140);
ocd_writel(0x00000029 | mask, bar + 0x100);
continue;
}
ocd_writel(0x00000000, bar + 0x100);
}
/* Finally, enable the PCI interupt */
#if USB_IRQ > 7
set_c0_intcontrol(1 << USB_IRQ);
#else
set_c0_status(1 << (USB_IRQ + 8));
#endif
ioport_resource.start = EXCITE_PHYS_PCI_IO;
ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
register_pci_controller(&bx_controller);
return 0;
}
arch_initcall(basler_excite_pci_setup);
include/asm-mips/bootinfo.h
View file @ 35189fad
......@@ -217,6 +217,7 @@
*/
#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
/*
* Valid machtype for group NEC EMMA2RH
......
include/asm-mips/mach-excite/cpu-feature-overrides.h 0 → 100644
View file @ 35189fad
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
*/
#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
/*
* Basler eXcite has an RM9122 processor.
*/
#define cpu_has_watch 1
#define cpu_has_mips16 0
#define cpu_has_divec 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-excite/excite.h 0 → 100644
View file @ 35189fad
#ifndef __EXCITE_H__
#define __EXCITE_H__
#include <linux/config.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#define EXCITE_CPU_EXT_CLOCK 100000000
#if !defined(__ASSEMBLER__)
void __init excite_kgdb_init(void);
void excite_procfs_init(void);
extern unsigned long memsize;
extern char modetty[];
extern u32 unit_id;
#endif
/* Base name for XICAP devices */
#define XICAP_NAME "xicap_gpi"
/* OCD register offsets */
#define LKB0 0x0038
#define LKB5 0x0128
#define LKM5 0x012C
#define LKB7 0x0138
#define LKM7 0x013c
#define LKB8 0x0140
#define LKM8 0x0144
#define LKB9 0x0148
#define LKM9 0x014c
#define LKB10 0x0150
#define LKM10 0x0154
#define LKB11 0x0158
#define LKM11 0x015c
#define LKB12 0x0160
#define LKM12 0x0164
#define LKB13 0x0168
#define LKM13 0x016c
#define LDP0 0x0200
#define LDP1 0x0210
#define LDP2 0x0220
#define LDP3 0x0230
#define INTPIN0 0x0A40
#define INTPIN1 0x0A44
#define INTPIN2 0x0A48
#define INTPIN3 0x0A4C
#define INTPIN4 0x0A50
#define INTPIN5 0x0A54
#define INTPIN6 0x0A58
#define INTPIN7 0x0A5C
/* TITAN register offsets */
#define CPRR 0x0004
#define CPDSR 0x0008
#define CPTC0R 0x000c
#define CPTC1R 0x0010
#define CPCFG0 0x0020
#define CPCFG1 0x0024
#define CPDST0A 0x0028
#define CPDST0B 0x002c
#define CPDST1A 0x0030
#define CPDST1B 0x0034
#define CPXDSTA 0x0038
#define CPXDSTB 0x003c
#define CPXCISRA 0x0048
#define CPXCISRB 0x004c
#define CPGIG0ER 0x0050
#define CPGIG1ER 0x0054
#define CPGRWL 0x0068
#define CPURSLMT 0x00f8
#define UACFG 0x0200
#define UAINTS 0x0204
#define SDRXFCIE 0x4828
#define SDTXFCIE 0x4928
#define INTP0Status0 0x1B00
#define INTP0Mask0 0x1B04
#define INTP0Set0 0x1B08
#define INTP0Clear0 0x1B0C
#define GXCFG 0x5000
#define GXDMADRPFX 0x5018
#define GXDMA_DESCADR 0x501c
#define GXCH0TDESSTRT 0x5054
/* IRQ definitions */
#define NMICONFIG 0xac0
#define TITAN_MSGINT 0xc4
#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
#define FPGA0_MSGINT 0x5a
#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
#define FPGA1_MSGINT 0x7b
#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
#define PHY_MSGINT 0x9c
#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
/* Pre-release units used interrupt pin #9 */
#define USB_IRQ 11
#else
/* Re-designed units use interrupt pin #1 */
#define USB_MSGINT 0x39
#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
#endif
#define TIMER_IRQ 12
/* Device address ranges */
#define EXCITE_OFFS_OCD 0x1fffc000
#define EXCITE_SIZE_OCD (16 * 1024)
#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
#define EXCITE_OFFS_SCRAM 0x1fffa000
#define EXCITE_SIZE_SCRAM (8 << 10)
#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
#define EXCITE_OFFS_PCI_IO 0x1fff8000
#define EXCITE_SIZE_PCI_IO (8 << 10)
#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
#define EXCITE_OFFS_TITAN 0x1fff0000
#define EXCITE_SIZE_TITAN (32 << 10)
#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
#define EXCITE_SIZE_PCI_MEM (64 << 10)
#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
#define EXCITE_OFFS_FPGA 0x1ffdc000
#define EXCITE_SIZE_FPGA (16 << 10)
#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
#define EXCITE_OFFS_NAND 0x1ffd8000
#define EXCITE_SIZE_NAND (16 << 10)
#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
#define EXCITE_OFFS_BOOTROM 0x1f000000
#define EXCITE_SIZE_BOOTROM (8 << 20)
#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
/* FPGA address offsets */
#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
#endif /* __EXCITE_H__ */
include/asm-mips/mach-excite/excite_nandflash.h 0 → 100644
View file @ 35189fad
#ifndef __EXCITE_NANDFLASH_H__
#define __EXCITE_NANDFLASH_H__
/* Resource names */
#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
#endif /* __EXCITE_NANDFLASH_H__ */
include/asm-mips/mach-excite/rm9k_eth.h 0 → 100644
View file @ 35189fad
#if !defined(__RM9K_ETH_H__)
#define __RM9K_ETH_H__
#define RM9K_GE_NAME "rm9k_ge"
/* Resource names */
#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
#endif /* !defined(__RM9K_ETH_H__) */
include/asm-mips/mach-excite/rm9k_wdt.h 0 → 100644
View file @ 35189fad
#ifndef __RM9K_WDT_H__
#define __RM9K_WDT_H__
/* Device name */
#define WDT_NAME "wdt_gpi"
/* Resource names */
#define WDT_RESOURCE_REGS "excite_watchdog_regs"
#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
#endif /* __RM9K_WDT_H__ */
include/asm-mips/mach-excite/rm9k_xicap.h 0 → 100644
View file @ 35189fad
#ifndef __EXCITE_XICAP_H__
#define __EXCITE_XICAP_H__
/* Resource names */
#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
#define XICAP_RESOURCE_XDMA "xicap_xdma"
#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
#define XICAP_RESOURCE_IRQ "xicap_irq"
#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
#endif /* __EXCITE_XICAP_H__ */
include/asm-mips/rm9k-ocd.h 0 → 100644
View file @ 35189fad
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#if !defined(_ASM_RM9K_OCD_H)
#define _ASM_RM9K_OCD_H
#include <linux/types.h>
#include <linux/spinlock.h>
#include <asm/io.h>
extern volatile void __iomem * const ocd_base;
extern volatile void __iomem * const titan_base;
#define ocd_addr(__x__) (ocd_base + (__x__))
#define titan_addr(__x__) (titan_base + (__x__))
#define scram_addr(__x__) (scram_base + (__x__))
/* OCD register access */
#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
#define ocd_writel(__val__, __offs__) \
__raw_writel((__val__), ocd_addr(__offs__))
#define ocd_writew(__val__, __offs__) \
__raw_writew((__val__), ocd_addr(__offs__))
#define ocd_writeb(__val__, __offs__) \
__raw_writeb((__val__), ocd_addr(__offs__))
/* TITAN register access - 32 bit-wide only */
#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
#define titan_writel(__val__, __offs__) \
__raw_writel((__val__), titan_addr(__offs__))
/* Protect access to shared TITAN registers */
extern spinlock_t titan_lock;
extern int titan_irqflags;
#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
#endif /* !defined(_ASM_RM9K_OCD_H) */
include/asm-mips/war.h
View file @ 35189fad
......@@ -172,7 +172,8 @@
* On the RM9000 there is a problem which makes the CreateDirtyExclusive
* cache operation unusable on SMP systems.
*/
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
defined(CONFIG_BASLER_EXCITE)
#define RM9000_CDEX_SMP_WAR 1
#endif
......@@ -182,7 +183,7 @@
* being fetched may case spurious exceptions.
*/
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
defined(CONFIG_PMC_YOSEMITE)
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#endif
......
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