Commit 2f351741 authored by Bryan Wu's avatar Bryan Wu Committed by Linus Torvalds

Blackfin serial driver: this driver enable SPORTs on Blackfin emulate UART

Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
Cc: Alan Cox <alan@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 4e68852d
...@@ -1355,4 +1355,47 @@ config SERIAL_SC26XX_CONSOLE ...@@ -1355,4 +1355,47 @@ config SERIAL_SC26XX_CONSOLE
help help
Support for Console on SC2681/SC2692 serial ports. Support for Console on SC2681/SC2692 serial ports.
config SERIAL_BFIN_SPORT
tristate "Blackfin SPORT emulate UART (EXPERIMENTAL)"
depends on BFIN && EXPERIMENTAL
select SERIAL_CORE
help
Enble support SPORT emulate UART on Blackfin series.
To compile this driver as a module, choose M here: the
module will be called bfin_sport_uart.
choice
prompt "Baud rate for Blackfin SPORT UART"
depends on SERIAL_BFIN_SPORT
default SERIAL_SPORT_BAUD_RATE_57600
help
Choose a baud rate for the SPORT UART, other uart settings are
8 bit, 1 stop bit, no parity, no flow control.
config SERIAL_SPORT_BAUD_RATE_115200
bool "115200"
config SERIAL_SPORT_BAUD_RATE_57600
bool "57600"
config SERIAL_SPORT_BAUD_RATE_38400
bool "38400"
config SERIAL_SPORT_BAUD_RATE_19200
bool "19200"
config SERIAL_SPORT_BAUD_RATE_9600
bool "9600"
endchoice
config SPORT_BAUD_RATE
int
depends on SERIAL_BFIN_SPORT
default 115200 if (SERIAL_SPORT_BAUD_RATE_115200)
default 57600 if (SERIAL_SPORT_BAUD_RATE_57600)
default 38400 if (SERIAL_SPORT_BAUD_RATE_38400)
default 19200 if (SERIAL_SPORT_BAUD_RATE_19200)
default 9600 if (SERIAL_SPORT_BAUD_RATE_9600)
endmenu endmenu
...@@ -27,6 +27,7 @@ obj-$(CONFIG_SERIAL_PXA) += pxa.o ...@@ -27,6 +27,7 @@ obj-$(CONFIG_SERIAL_PXA) += pxa.o
obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o
obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
......
This diff is collapsed.
/*
* File: linux/drivers/serial/bfin_sport_uart.h
*
* Based on: include/asm-blackfin/mach-533/bfin_serial_5xx.h
* Author: Roy Huang <roy.huang>analog.com>
*
* Created: Nov 22, 2006
* Copyright: (C) Analog Device Inc.
* Description: this driver enable SPORTs on Blackfin emulate UART.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
#define OFFSET_TX 0x10 /* Transmit Data Register */
#define OFFSET_RX 0x18 /* Receive Data Register */
#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
#define OFFSET_STAT 0x30 /* Status Register */
#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
#define SPORT_GET_RX32(sport) bfin_read32(((sport)->port.membase + OFFSET_RX))
#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
...@@ -149,13 +149,15 @@ ...@@ -149,13 +149,15 @@
/* Freescale ColdFire */ /* Freescale ColdFire */
#define PORT_MCF 78 #define PORT_MCF 78
#define PORT_SC26XX 79 /* Blackfin SPORT */
#define PORT_BFIN_SPORT 79
/* MN10300 on-chip UART numbers */ /* MN10300 on-chip UART numbers */
#define PORT_MN10300 80 #define PORT_MN10300 80
#define PORT_MN10300_CTS 81 #define PORT_MN10300_CTS 81
#define PORT_SC26XX 82
#ifdef __KERNEL__ #ifdef __KERNEL__
#include <linux/compiler.h> #include <linux/compiler.h>
......
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