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Commit 2acb802b authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc 

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
  powerpc: Remove use of CONFIG_PPC_MERGE
  powerpc: Force printing of 'total_memory' to unsigned long long
  powerpc: Fix compiler warning in arch/powerpc/mm/mem.c
  powerpc: Move include files to arch/powerpc/include/asm
parents d8f4b819 9c4cb825
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Showing with 22 additions and 400 deletions
Documentation/powerpc/booting-without-of.txt
View file @ 2acb802b
......@@ -278,7 +278,7 @@ it with special cases.
a 64-bit platform.
d) request and get assigned a platform number (see PLATFORM_*
constants in include/asm-powerpc/processor.h
constants in arch/powerpc/include/asm/processor.h
32-bit embedded kernels:
......@@ -340,7 +340,7 @@ the block to RAM before passing it to the kernel.
---------
The kernel is entered with r3 pointing to an area of memory that is
roughly described in include/asm-powerpc/prom.h by the structure
roughly described in arch/powerpc/include/asm/prom.h by the structure
boot_param_header:
struct boot_param_header {
......
Documentation/powerpc/eeh-pci-error-recovery.txt
View file @ 2acb802b
......@@ -133,7 +133,7 @@ error. Given an arbitrary address, the routine
pci_get_device_by_addr() will find the pci device associated
with that address (if any).
The default include/asm-powerpc/io.h macros readb(), inb(), insb(),
The default arch/powerpc/include/asm/io.h macros readb(), inb(), insb(),
etc. include a check to see if the i/o read returned all-0xff's.
If so, these make a call to eeh_dn_check_failure(), which in turn
asks the firmware if the all-ff's value is the sign of a true EEH
......
arch/powerpc/Kconfig.debug
View file @ 2acb802b
......@@ -97,7 +97,7 @@ config IRQSTACKS
config VIRQ_DEBUG
bool "Expose hardware/virtual IRQ mapping via debugfs"
depends on DEBUG_FS && PPC_MERGE
depends on DEBUG_FS
help
This option will show the mapping relationship between hardware irq
numbers and virtual irq numbers. The mapping is exposed via debugfs
......
arch/powerpc/boot/io.h
View file @ 2acb802b
......@@ -6,7 +6,7 @@
/*
* Low-level I/O routines.
*
* Copied from <file:include/asm-powerpc/io.h> (which has no copyright)
* Copied from <file:arch/powerpc/include/asm/io.h> (which has no copyright)
*/
static inline int in_8(const volatile unsigned char *addr)
{
......
include/asm-powerpc/dcr.h → arch/powerpc/include/asm/dcr.h
View file @ 2acb802b
......@@ -65,17 +65,13 @@ typedef dcr_host_mmio_t dcr_host_t;
#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
/*
* On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
* base from the device-tree
* additional helpers to read the DCR * base from the device-tree
*/
#ifdef CONFIG_PPC_MERGE
struct device_node;
extern unsigned int dcr_resource_start(struct device_node *np,
unsigned int index);
extern unsigned int dcr_resource_len(struct device_node *np,
unsigned int index);
#endif /* CONFIG_PPC_MERGE */
#endif /* CONFIG_PPC_DCR */
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
......
include/asm-powerpc/i8259.h → arch/powerpc/include/asm/i8259.h
View file @ 2acb802b
......@@ -4,14 +4,9 @@
#include <linux/irq.h>
#ifdef CONFIG_PPC_MERGE
extern void i8259_init(struct device_node *node, unsigned long intack_addr);
extern unsigned int i8259_irq(void);
extern struct irq_host *i8259_get_host(void);
#else
extern void i8259_init(unsigned long intack_addr, int offset);
extern int i8259_irq(void);
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_I8259_H */
include/asm-powerpc/immap_qe.h → arch/powerpc/include/asm/immap_qe.h
View file @ 2acb802b
/*
* include/asm-powerpc/immap_qe.h
*
* QUICC Engine (QE) Internal Memory Map.
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
......
include/asm-powerpc/ipic.h → arch/powerpc/include/asm/ipic.h
View file @ 2acb802b
/*
* include/asm-powerpc/ipic.h
*
* IPIC external definitions and structure.
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
......@@ -79,15 +77,8 @@ extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
extern u32 ipic_get_mcp_status(void);
extern void ipic_clear_mcp_status(u32 mask);
#ifdef CONFIG_PPC_MERGE
extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
extern unsigned int ipic_get_irq(void);
#else
extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
unsigned int irq_offset,
unsigned char *senses, unsigned int senses_count);
extern int ipic_get_irq(void);
#endif
#endif /* __ASM_IPIC_H__ */
#endif /* __KERNEL__ */
include/asm-powerpc/irq.h → arch/powerpc/include/asm/irq.h
View file @ 2acb802b
......@@ -25,8 +25,6 @@
extern atomic_t ppc_n_lost_interrupts;
#ifdef CONFIG_PPC_MERGE
/* This number is used when no interrupt has been assigned */
#define NO_IRQ (0)
......@@ -326,292 +324,6 @@ static __inline__ int irq_canonicalize(int irq)
return irq;
}
#else /* CONFIG_PPC_MERGE */
/* This number is used when no interrupt has been assigned */
#define NO_IRQ (-1)
#define NO_IRQ_IGNORE (-2)
/*
* These constants are used for passing information about interrupt
* signal polarity and level/edge sensing to the low-level PIC chip
* drivers.
*/
#define IRQ_SENSE_MASK 0x1
#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
#define IRQ_POLARITY_MASK 0x2
#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
#if defined(CONFIG_40x)
#include <asm/ibm4xx.h>
#ifndef NR_BOARD_IRQS
#define NR_BOARD_IRQS 0
#endif
#ifndef UIC_WIDTH /* Number of interrupts per device */
#define UIC_WIDTH 32
#endif
#ifndef NR_UICS /* number of UIC devices */
#define NR_UICS 1
#endif
#if defined (CONFIG_403)
/*
* The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
* 32 possible interrupts, a majority of which are not implemented on
* all cores. There are six configurable, external interrupt pins and
* there are eight internal interrupts for the on-chip serial port
* (SPU), DMA controller, and JTAG controller.
*
*/
#define NR_AIC_IRQS 32
#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
#elif !defined (CONFIG_403)
/*
* The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
* possible interrupts as well. There are seven, configurable external
* interrupt pins and there are 17 internal interrupts for the on-chip
* serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
*
*/
#define NR_UIC_IRQS UIC_WIDTH
#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
#endif
#elif defined(CONFIG_44x)
#include <asm/ibm44x.h>
#define NR_UIC_IRQS 32
#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
#elif defined(CONFIG_8xx)
/* Now include the board configuration specific associations.
*/
#include <asm/mpc8xx.h>
/* The MPC8xx cores have 16 possible interrupts. There are eight
* possible level sensitive interrupts assigned and generated internally
* from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
* There are eight external interrupts (IRQs) that can be configured
* as either level or edge sensitive.
*
* On some implementations, there is also the possibility of an 8259
* through the PCI and PCI-ISA bridges.
*
* We are "flattening" the interrupt vectors of the cascaded CPM
* and 8259 interrupt controllers so that we can uniquely identify
* any interrupt source with a single integer.
*/
#define NR_SIU_INTS 16
#define NR_CPM_INTS 32
#ifndef NR_8259_INTS
#define NR_8259_INTS 0
#endif
#define SIU_IRQ_OFFSET 0
#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
/* These values must be zero-based and map 1:1 with the SIU configuration.
* They are used throughout the 8xx I/O subsystem to generate
* interrupt masks, flags, and other control patterns. This is why the
* current kernel assumption of the 8259 as the base controller is such
* a pain in the butt.
*/
#define SIU_IRQ0 (0) /* Highest priority */
#define SIU_LEVEL0 (1)
#define SIU_IRQ1 (2)
#define SIU_LEVEL1 (3)
#define SIU_IRQ2 (4)
#define SIU_LEVEL2 (5)
#define SIU_IRQ3 (6)
#define SIU_LEVEL3 (7)
#define SIU_IRQ4 (8)
#define SIU_LEVEL4 (9)
#define SIU_IRQ5 (10)
#define SIU_LEVEL5 (11)
#define SIU_IRQ6 (12)
#define SIU_LEVEL6 (13)
#define SIU_IRQ7 (14)
#define SIU_LEVEL7 (15)
#define MPC8xx_INT_FEC1 SIU_LEVEL1
#define MPC8xx_INT_FEC2 SIU_LEVEL3
#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
/* The internal interrupts we can configure as we see fit.
* My personal preference is CPM at level 2, which puts it above the
* MBX PCI/ISA/IDE interrupts.
*/
#ifndef PIT_INTERRUPT
#define PIT_INTERRUPT SIU_LEVEL0
#endif
#ifndef CPM_INTERRUPT
#define CPM_INTERRUPT SIU_LEVEL2
#endif
#ifndef PCMCIA_INTERRUPT
#define PCMCIA_INTERRUPT SIU_LEVEL6
#endif
#ifndef DEC_INTERRUPT
#define DEC_INTERRUPT SIU_LEVEL7
#endif
/* Some internal interrupt registers use an 8-bit mask for the interrupt
* level instead of a number.
*/
#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
#else /* CONFIG_40x + CONFIG_8xx */
/*
* this is the # irq's for all ppc arch's (pmac/chrp/prep)
* so it is the max of them all
*/
#define NR_IRQS 256
#define __DO_IRQ_CANON 1
#ifndef CONFIG_8260
#define NUM_8259_INTERRUPTS 16
#else /* CONFIG_8260 */
/* The 8260 has an internal interrupt controller with a maximum of
* 64 IRQs. We will use NR_IRQs from above since it is large enough.
* Don't be confused by the 8260 documentation where they list an
* "interrupt number" and "interrupt vector". We are only interested
* in the interrupt vector. There are "reserved" holes where the
* vector number increases, but the interrupt number in the table does not.
* (Document errata updates have fixed this...make sure you have up to
* date processor documentation -- Dan).
*/
#ifndef CPM_IRQ_OFFSET
#define CPM_IRQ_OFFSET 0
#endif
#define NR_CPM_INTS 64
#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
#define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
#endif /* CONFIG_8260 */
#endif /* Whatever way too big #ifdef */
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
/* pedantic: these are long because they are used with set_bit --RR */
extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
/*
* Because many systems have two overlapping names spaces for
* interrupts (ISA and XICS for example), and the ISA interrupts
* have historically not been easy to renumber, we allow ISA
* interrupts to take values 0 - 15, and shift up the remaining
* interrupts by 0x10.
*/
#define NUM_ISA_INTERRUPTS 0x10
extern int __irq_offset_value;
static inline int irq_offset_up(int irq)
{
return(irq + __irq_offset_value);
}
static inline int irq_offset_down(int irq)
{
return(irq - __irq_offset_value);
}
static inline int irq_offset_value(void)
{
return __irq_offset_value;
}
#ifdef __DO_IRQ_CANON
extern int ppc_do_canonicalize_irqs;
#else
#define ppc_do_canonicalize_irqs 0
#endif
static __inline__ int irq_canonicalize(int irq)
{
if (ppc_do_canonicalize_irqs && irq == 2)
irq = 9;
return irq;
}
#endif /* CONFIG_PPC_MERGE */
extern int distribute_irqs;
struct irqaction;
......
include/asm-powerpc/irqflags.h → arch/powerpc/include/asm/irqflags.h
View file @ 2acb802b
/*
* include/asm-powerpc/irqflags.h
*
* IRQ flags handling
*/
#ifndef _ASM_IRQFLAGS_H
......@@ -10,7 +8,7 @@
/*
* Get definitions for raw_local_save_flags(x), etc.
*/
#include <asm-powerpc/hw_irq.h>
#include <asm/hw_irq.h>
#else
#ifdef CONFIG_TRACE_IRQFLAGS
......
include/asm-powerpc/kgdb.h → arch/powerpc/include/asm/kgdb.h
View file @ 2acb802b
/*
* include/asm-powerpc/kgdb.h
*
* The PowerPC (32/64) specific defines / externs for KGDB. Based on
* the previous 32bit and 64bit specific files, which had the following
* copyrights:
......
include/asm-powerpc/paca.h → arch/powerpc/include/asm/paca.h
View file @ 2acb802b
/*
* include/asm-powerpc/paca.h
*
* This control block defines the PACA which defines the processor
* specific data for each logical processor on the system.
* There are some pointers defined that are utilized by PLIC.
......
include/asm-powerpc/pgtable-ppc64.h → arch/powerpc/include/asm/pgtable-ppc64.h
View file @ 2acb802b
......@@ -100,7 +100,7 @@
#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
/* __pgprot defined in asm-powerpc/page.h */
/* __pgprot defined in arch/powerpc/incliude/asm/page.h */
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
......
include/asm-powerpc/qe_ic.h → arch/powerpc/include/asm/qe_ic.h
View file @ 2acb802b
/*
* include/asm-powerpc/qe_ic.h
*
* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
*
* Authors: Shlomi Gridish <gridish@freescale.com>
......
include/asm-powerpc/rwsem.h → arch/powerpc/include/asm/rwsem.h
View file @ 2acb802b
......@@ -8,8 +8,8 @@
#ifdef __KERNEL__
/*
* include/asm-powerpc/rwsem.h: R/W semaphores for PPC using the stuff
* in lib/rwsem.c. Adapted largely from include/asm-i386/rwsem.h
* R/W semaphores for PPC using the stuff in lib/rwsem.c.
* Adapted largely from include/asm-i386/rwsem.h
* by Paul Mackerras <paulus@samba.org>.
*/
......
include/asm-powerpc/ucc_fast.h → arch/powerpc/include/asm/ucc_fast.h
View file @ 2acb802b
/*
* include/asm-powerpc/ucc_fast.h
*
* Internal header file for UCC FAST unit routines.
*
* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
......
include/asm-powerpc/uic.h → arch/powerpc/include/asm/uic.h
View file @ 2acb802b
/*
* include/asm-powerpc/uic.h
*
* IBM PPC4xx UIC external definitions and structure.
*
* Maintainer: David Gibson <dwg@au1.ibm.com>
......
arch/powerpc/kernel/Makefile
View file @ 2acb802b
......@@ -59,8 +59,6 @@ obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o
obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
obj-$(CONFIG_44x) += cpu_setup_44x.o
ifeq ($(CONFIG_PPC_MERGE),y)
extra-$(CONFIG_PPC_STD_MMU) := head_32.o
extra-$(CONFIG_PPC64) := head_64.o
extra-$(CONFIG_40x) := head_40x.o
......@@ -100,12 +98,6 @@ ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
obj-y += iomap.o
endif
else
# stuff used from here for ARCH=ppc
smpobj-$(CONFIG_SMP) += smp.o
endif
obj-$(CONFIG_PPC64) += $(obj64-y)
extra-$(CONFIG_PPC_FPU) += fpu.o
......@@ -121,9 +113,6 @@ PHONY += systbl_chk
systbl_chk: $(src)/systbl_chk.sh $(obj)/systbl_chk.i
$(call cmd,systbl_chk)
ifeq ($(CONFIG_PPC_MERGE),y)
$(obj)/built-in.o: prom_init_check
quiet_cmd_prom_init_check = CALL $<
......@@ -133,7 +122,4 @@ PHONY += prom_init_check
prom_init_check: $(src)/prom_init_check.sh $(obj)/prom_init.o
$(call cmd,prom_init_check)
endif
clean-files := vmlinux.lds
arch/powerpc/kernel/cpu_setup_44x.S
View file @ 2acb802b
......@@ -39,12 +39,6 @@ _GLOBAL(__setup_cpu_440gx)
_GLOBAL(__setup_cpu_440spe)
b __fixup_440A_mcheck
/* Temporary fixup for arch/ppc until we kill the whole thing */
#ifndef CONFIG_PPC_MERGE
_GLOBAL(__fixup_440A_mcheck)
blr
#endif
/* enable APU between CPU and FPU */
_GLOBAL(__init_fpu_44x)
mfspr r3,SPRN_CCR0
......
arch/powerpc/kernel/irq.c
View file @ 2acb802b
......@@ -77,22 +77,12 @@ static int ppc_spurious_interrupts;
EXPORT_SYMBOL(__irq_offset_value);
atomic_t ppc_n_lost_interrupts;
#ifndef CONFIG_PPC_MERGE
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
#endif
#ifdef CONFIG_TAU_INT
extern int tau_initialized;
extern int tau_interrupts(int);
#endif
#endif /* CONFIG_PPC32 */
#if defined(CONFIG_SMP) && !defined(CONFIG_PPC_MERGE)
extern atomic_t ipi_recv;
extern atomic_t ipi_sent;
#endif
#ifdef CONFIG_PPC64
EXPORT_SYMBOL(irq_desc);
......@@ -216,21 +206,14 @@ int show_interrupts(struct seq_file *p, void *v)
skip:
spin_unlock_irqrestore(&desc->lock, flags);
} else if (i == NR_IRQS) {
#ifdef CONFIG_PPC32
#ifdef CONFIG_TAU_INT
#if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
if (tau_initialized){
seq_puts(p, "TAU: ");
for_each_online_cpu(j)
seq_printf(p, "%10u ", tau_interrupts(j));
seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n");
}
#endif
#if defined(CONFIG_SMP) && !defined(CONFIG_PPC_MERGE)
/* should this be per processor send/receive? */
seq_printf(p, "IPI (recv/sent): %10u/%u\n",
atomic_read(&ipi_recv), atomic_read(&ipi_sent));
#endif
#endif /* CONFIG_PPC32 */
#endif /* CONFIG_PPC32 && CONFIG_TAU_INT*/
seq_printf(p, "BAD: %10u\n", ppc_spurious_interrupts);
}
return 0;
......@@ -454,8 +437,6 @@ void do_softirq(void)
* IRQ controller and virtual interrupts
*/
#ifdef CONFIG_PPC_MERGE
static LIST_HEAD(irq_hosts);
static DEFINE_SPINLOCK(irq_big_lock);
static DEFINE_PER_CPU(unsigned int, irq_radix_reader);
......@@ -1114,8 +1095,6 @@ static int __init irq_debugfs_init(void)
__initcall(irq_debugfs_init);
#endif /* CONFIG_VIRQ_DEBUG */
#endif /* CONFIG_PPC_MERGE */
#ifdef CONFIG_PPC64
static int __init setup_noirqdistrib(char *str)
{
......
arch/powerpc/kernel/process.c
View file @ 2acb802b
......@@ -276,10 +276,8 @@ int set_dabr(unsigned long dabr)
{
__get_cpu_var(current_dabr) = dabr;
#ifdef CONFIG_PPC_MERGE /* XXX for now */
if (ppc_md.set_dabr)
return ppc_md.set_dabr(dabr);
#endif
/* XXX should we have a CPU_FTR_HAS_DABR ? */
#if defined(CONFIG_PPC64) || defined(CONFIG_6xx)
......
arch/powerpc/kernel/vdso.c
View file @ 2acb802b
......@@ -788,9 +788,7 @@ static int __init vdso_init(void)
return 0;
}
#ifdef CONFIG_PPC_MERGE
arch_initcall(vdso_init);
#endif
int in_gate_area_no_task(unsigned long addr)
{
......
arch/powerpc/lib/Makefile
View file @ 2acb802b
......@@ -6,12 +6,10 @@ ifeq ($(CONFIG_PPC64),y)
EXTRA_CFLAGS += -mno-minimal-toc
endif
ifeq ($(CONFIG_PPC_MERGE),y)
obj-y := string.o alloc.o \
checksum_$(CONFIG_WORD_SIZE).o
obj-$(CONFIG_PPC32) += div64.o copy_32.o crtsavres.o
obj-$(CONFIG_HAS_IOMEM) += devres.o
endif
obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
memcpy_64.o usercopy_64.o mem_64.o string.o
......
arch/powerpc/mm/mem.c
View file @ 2acb802b
......@@ -311,7 +311,7 @@ void __init paging_init(void)
#endif /* CONFIG_HIGHMEM */
printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%lx\n",
(u64)top_of_ram, total_ram);
(unsigned long long)top_of_ram, total_ram);
printk(KERN_DEBUG "Memory hole size: %ldMB\n",
(long int)((top_of_ram - total_ram) >> 20));
memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
......
arch/powerpc/mm/ppc_mmu_32.c
View file @ 2acb802b
......@@ -236,8 +236,8 @@ void __init MMU_init_hw(void)
Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);
printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n",
total_memory >> 20, Hash_size >> 10, Hash);
printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
(unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);
/*
......
arch/powerpc/mm/tlb_64.c
View file @ 2acb802b
......@@ -34,7 +34,7 @@
DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
/* This is declared as we are using the more or less generic
* include/asm-powerpc/tlb.h file -- tgall
* arch/powerpc/include/asm/tlb.h file -- tgall
*/
DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
......
arch/powerpc/platforms/52xx/Makefile
View file @ 2acb802b
#
# Makefile for 52xx based boards
#
ifeq ($(CONFIG_PPC_MERGE),y)
obj-y += mpc52xx_pic.o mpc52xx_common.o
obj-$(CONFIG_PCI) += mpc52xx_pci.o
endif
obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o
obj-$(CONFIG_PPC_EFIKA) += efika.o
......@@ -15,4 +13,4 @@ ifeq ($(CONFIG_PPC_LITE5200),y)
obj-$(CONFIG_PM) += lite5200_sleep.o lite5200_pm.o
endif
obj-$(CONFIG_PPC_MPC5200_GPIO) += mpc52xx_gpio.o
\ No newline at end of file
obj-$(CONFIG_PPC_MPC5200_GPIO) += mpc52xx_gpio.o
arch/powerpc/platforms/86xx/mpc86xx_smp.c
View file @ 2acb802b
......@@ -19,7 +19,7 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/pci-bridge.h>
#include <asm-powerpc/mpic.h>
#include <asm/mpic.h>
#include <asm/mpc86xx.h>
#include <asm/cacheflush.h>
......
arch/powerpc/platforms/Makefile
View file @ 2acb802b
obj-$(CONFIG_FSL_ULI1575) += fsl_uli1575.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_PMAC) += powermac/
else
ifeq ($(CONFIG_PPC64),y)
obj-$(CONFIG_PPC_PMAC) += powermac/
endif
endif
obj-$(CONFIG_PPC_CHRP) += chrp/
obj-$(CONFIG_40x) += 40x/
obj-$(CONFIG_44x) += 44x/
......
arch/powerpc/platforms/powermac/Makefile
View file @ 2acb802b
......@@ -7,7 +7,7 @@ endif
obj-y += pic.o setup.o time.o feature.o pci.o \
sleep.o low_i2c.o cache.o pfunc_core.o \
pfunc_base.o
pfunc_base.o udbg_scc.o udbg_adb.o
obj-$(CONFIG_PMAC_BACKLIGHT) += backlight.o
obj-$(CONFIG_CPU_FREQ_PMAC) += cpufreq_32.o
obj-$(CONFIG_CPU_FREQ_PMAC64) += cpufreq_64.o
......@@ -19,4 +19,3 @@ obj-$(CONFIG_NVRAM:m=y) += nvram.o
obj-$(CONFIG_PPC64) += nvram.o
obj-$(CONFIG_PPC32) += bootx_init.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_PPC_MERGE) += udbg_scc.o udbg_adb.o
arch/powerpc/sysdev/Makefile
View file @ 2acb802b
......@@ -25,7 +25,6 @@ obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
obj-$(CONFIG_AXON_RAM) += axonram.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
......@@ -36,7 +35,6 @@ obj-$(CONFIG_OF_RTC) += of_rtc.o
ifeq ($(CONFIG_PCI),y)
obj-$(CONFIG_4xx) += ppc4xx_pci.o
endif
endif
# Temporary hack until we have migrated to asm-powerpc
ifeq ($(ARCH),powerpc)
......
drivers/char/hvc_console.h
View file @ 2acb802b
......@@ -6,7 +6,7 @@
* Ryan S. Arnold <rsa@us.ibm.com>
*
* hvc_console header information:
* moved here from include/asm-powerpc/hvconsole.h
* moved here from arch/powerpc/include/asm/hvconsole.h
* and drivers/char/hvc_console.c
*
* This program is free software; you can redistribute it and/or modify
......
drivers/char/hvcs.c
View file @ 2acb802b
......@@ -114,7 +114,7 @@
* the hvcs_final_close() function in order to get it out of the spinlock.
* Rearranged hvcs_close(). Cleaned up some printks and did some housekeeping
* on the changelog. Removed local CLC_LENGTH and used HVCS_CLC_LENGTH from
* include/asm-powerpc/hvcserver.h
* arch/powerepc/include/asm/hvcserver.h
*
* 1.3.2 -> 1.3.3 Replaced yield() in hvcs_close() with tty_wait_until_sent() to
* prevent possible lockup with realtime scheduling as similarily pointed out by
......
drivers/infiniband/hw/ehca/ehca_reqs.c
View file @ 2acb802b
......@@ -42,7 +42,7 @@
*/
#include <asm-powerpc/system.h>
#include <asm/system.h>
#include "ehca_classes.h"
#include "ehca_tools.h"
#include "ehca_qes.h"
......
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