Commit 2882b0c6 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle

MIPS: Alchemy: get rid of allow_au1k_wait

Eliminate the 'allow_au1k_wait' variable.  MIPS kernel installs the
Alchemy-specific wait code before timer initialization;  if the C0
timer must be used for timekeeping the wait function is set to NULL
which means no wait implementation is available.

As a sideeffect, the 'wait instruction available' output in
/proc/cpuinfo now correctly indicates whether 'wait' is usable.

Run-tested on DB1200.
Signed-off-by: default avatarManuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9d24bafb
...@@ -36,14 +36,13 @@ ...@@ -36,14 +36,13 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <asm/processor.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
/* 32kHz clock enabled and detected */ /* 32kHz clock enabled and detected */
#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
extern int allow_au1k_wait; /* default off for CP0 Counter */
static cycle_t au1x_counter1_read(struct clocksource *cs) static cycle_t au1x_counter1_read(struct clocksource *cs)
{ {
return au_readl(SYS_RTCREAD); return au_readl(SYS_RTCREAD);
...@@ -153,13 +152,17 @@ void __init plat_time_init(void) ...@@ -153,13 +152,17 @@ void __init plat_time_init(void)
printk(KERN_INFO "Alchemy clocksource installed\n"); printk(KERN_INFO "Alchemy clocksource installed\n");
/* can now use 'wait' */
allow_au1k_wait = 1;
return; return;
cntr_err: cntr_err:
/* counters unusable, use C0 counter */ /*
* MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
* function is called. Because the Alchemy counters are unusable
* the C0 timekeeping code is installed and use of the 'wait'
* instruction must be prohibited, which is done most easily by
* assigning NULL to cpu_wait.
*/
cpu_wait = NULL;
r4k_clockevent_init(); r4k_clockevent_init();
init_r4k_clocksource(); init_r4k_clocksource();
allow_au1k_wait = 0;
} }
...@@ -91,16 +91,13 @@ static void rm7k_wait_irqoff(void) ...@@ -91,16 +91,13 @@ static void rm7k_wait_irqoff(void)
local_irq_enable(); local_irq_enable();
} }
/* The Au1xxx wait is available only if using 32khz counter or /*
* external timer source, but specifically not CP0 Counter. */ * The Au1xxx wait is available only if using 32khz counter or
int allow_au1k_wait; * external timer source, but specifically not CP0 Counter.
* alchemy/common/time.c may override cpu_wait!
*/
static void au1k_wait(void) static void au1k_wait(void)
{ {
if (!allow_au1k_wait)
return;
/* using the wait instruction makes CP0 counter unusable */
__asm__(" .set mips3 \n" __asm__(" .set mips3 \n"
" cache 0x14, 0(%0) \n" " cache 0x14, 0(%0) \n"
" cache 0x14, 32(%0) \n" " cache 0x14, 32(%0) \n"
......
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