[8139too]: tab-align enums and structs; remove dead code

* (main change) tab-align hardware register value enums, and hw struct

* MMIO_FLUSH_AUDIT_COMPLETE has been defined to 1 for a while.  Remove
  the code activated when it is set to zero.
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

drivers/net/8139too.c

@@ -388,7 +388,6 @@ enum rx_mode_bits {
 
 /* Bits in TxConfig. */
 enum tx_config_bits {
-
         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
         TxIFGShift	= 24,
         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
@@ -397,10 +396,10 @@ enum tx_config_bits {
         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
 
 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */
-	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */
+	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */
 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */
-	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */
-	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */
+	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */
+	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */
 
 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */
 };
@@ -441,7 +440,7 @@ enum Config5Bits {
 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */
 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */
 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */
-	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
+	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */
 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */
 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */
@@ -576,22 +575,30 @@ struct rtl8139_private {
 	struct napi_struct	napi;
 	struct net_device	*dev;
 	struct net_device_stats	stats;
+
 	unsigned char		*rx_ring;
-	unsigned int cur_rx;	/* Index into the Rx buffer of next Rx pkt. */
+	unsigned int		cur_rx;	/* RX buf index of next pkt */
+	dma_addr_t		rx_ring_dma;
+
 	unsigned int		tx_flag;
 	unsigned long		cur_tx;
 	unsigned long		dirty_tx;
 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */
 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */
-	dma_addr_t rx_ring_dma;
 	dma_addr_t		tx_bufs_dma;
+
 	signed char		phys[4];	/* MII device addresses. */
-	char twistie, twist_row, twist_col;	/* Twister tune state. */
+
+				/* Twister tune state. */
+	char			twistie, twist_row, twist_col;
+
 	unsigned int		watchdog_fired : 1;
 	unsigned int		default_port : 4; /* Last dev->if_port value. */
 	unsigned int		have_thread : 1;
+
 	spinlock_t		lock;
 	spinlock_t		rx_lock;
+
 	chip_t			chipset;
 	u32			rx_config;
 	struct rtl_extra_stats	xstats;
@@ -648,24 +655,11 @@ static const struct ethtool_ops rtl8139_ethtool_ops;
 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
 
-
-#define MMIO_FLUSH_AUDIT_COMPLETE 1
-#if MMIO_FLUSH_AUDIT_COMPLETE
-
 /* write MMIO register */
 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))
 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))
 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))
 
-#else
-
-/* write MMIO register, then flush */
-#define RTL_W8		RTL_W8_F
-#define RTL_W16		RTL_W16_F
-#define RTL_W32		RTL_W32_F
-
-#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
-
 /* read MMIO register */
 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))
 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))