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Commit 154502e1 authored by Paul Mundt's avatar Paul Mundt
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sh: clkfwk: Convert SH-Mobile CPUs to use CLK_ENABLE_ON_INIT. 

Kill off all of the clk_always_enabled leftovers and use the new flag
directly.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 4ff29ff8
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Showing with 183 additions and 225 deletions
arch/sh/include/asm/clock.h
View file @ 154502e1
......@@ -52,22 +52,6 @@ void clk_recalc_rate(struct clk *);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
static inline int clk_always_enable(const char *id)
{
struct clk *clk;
int ret;
clk = clk_get(NULL, id);
if (IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_enable(clk);
if (ret)
clk_put(clk);
return ret;
}
/* the exported API, in addition to clk_set_rate */
/**
* clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
......
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
View file @ 154502e1
......@@ -646,207 +646,208 @@ static struct clk_ops sh7722_mstpcr_clk_ops = {
.recalc = followparent_recalc,
};
#define MSTPCR(_name, _parent, regnr, bitnr) \
#define MSTPCR(_name, _parent, regnr, bitnr, _flags) \
{ \
.name = _name, \
.flags = _flags, \
.arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
.ops = (void *)_parent, \
}
static struct clk sh7722_mstpcr_clocks[] = {
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
MSTPCR("uram0", "umem_clk", 0, 28),
MSTPCR("xymem0", "bus_clk", 0, 26),
MSTPCR("tmu0", "peripheral_clk", 0, 15),
MSTPCR("cmt0", "r_clk", 0, 14),
MSTPCR("rwdt0", "r_clk", 0, 13),
MSTPCR("flctl0", "peripheral_clk", 0, 10),
MSTPCR("scif0", "peripheral_clk", 0, 7),
MSTPCR("scif1", "peripheral_clk", 0, 6),
MSTPCR("scif2", "peripheral_clk", 0, 5),
MSTPCR("i2c0", "peripheral_clk", 1, 9),
MSTPCR("rtc0", "r_clk", 1, 8),
MSTPCR("sdhi0", "peripheral_clk", 2, 18),
MSTPCR("keysc0", "r_clk", 2, 14),
MSTPCR("usbf0", "peripheral_clk", 2, 11),
MSTPCR("2dg0", "bus_clk", 2, 9),
MSTPCR("siu0", "bus_clk", 2, 8),
MSTPCR("vou0", "bus_clk", 2, 5),
MSTPCR("jpu0", "bus_clk", 2, 6),
MSTPCR("beu0", "bus_clk", 2, 4),
MSTPCR("ceu0", "bus_clk", 2, 3),
MSTPCR("veu0", "bus_clk", 2, 2),
MSTPCR("vpu0", "bus_clk", 2, 1),
MSTPCR("lcdc0", "bus_clk", 2, 0),
MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
MSTPCR("cmt0", "r_clk", 0, 14, 0),
MSTPCR("rwdt0", "r_clk", 0, 13, 0),
MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
MSTPCR("scif1", "peripheral_clk", 0, 6, 0),
MSTPCR("scif2", "peripheral_clk", 0, 5, 0),
MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
MSTPCR("rtc0", "r_clk", 1, 8, 0),
MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0),
MSTPCR("keysc0", "r_clk", 2, 14, 0),
MSTPCR("usbf0", "peripheral_clk", 2, 11, 0),
MSTPCR("2dg0", "bus_clk", 2, 9, 0),
MSTPCR("siu0", "bus_clk", 2, 8, 0),
MSTPCR("vou0", "bus_clk", 2, 5, 0),
MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
MSTPCR("beu0", "bus_clk", 2, 4, 0),
MSTPCR("ceu0", "bus_clk", 2, 3, 0),
MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7723)
/* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
MSTPCR("tlb0", "cpu_clk", 0, 31),
MSTPCR("ic0", "cpu_clk", 0, 30),
MSTPCR("oc0", "cpu_clk", 0, 29),
MSTPCR("l2c0", "sh_clk", 0, 28),
MSTPCR("ilmem0", "cpu_clk", 0, 27),
MSTPCR("fpu0", "cpu_clk", 0, 24),
MSTPCR("intc0", "cpu_clk", 0, 22),
MSTPCR("dmac0", "bus_clk", 0, 21),
MSTPCR("sh0", "sh_clk", 0, 20),
MSTPCR("hudi0", "peripheral_clk", 0, 19),
MSTPCR("ubc0", "cpu_clk", 0, 17),
MSTPCR("tmu0", "peripheral_clk", 0, 15),
MSTPCR("cmt0", "r_clk", 0, 14),
MSTPCR("rwdt0", "r_clk", 0, 13),
MSTPCR("dmac1", "bus_clk", 0, 12),
MSTPCR("tmu1", "peripheral_clk", 0, 11),
MSTPCR("flctl0", "peripheral_clk", 0, 10),
MSTPCR("scif0", "peripheral_clk", 0, 9),
MSTPCR("scif1", "peripheral_clk", 0, 8),
MSTPCR("scif2", "peripheral_clk", 0, 7),
MSTPCR("scif3", "bus_clk", 0, 6),
MSTPCR("scif4", "bus_clk", 0, 5),
MSTPCR("scif5", "bus_clk", 0, 4),
MSTPCR("msiof0", "bus_clk", 0, 2),
MSTPCR("msiof1", "bus_clk", 0, 1),
MSTPCR("meram0", "sh_clk", 0, 0),
MSTPCR("i2c0", "peripheral_clk", 1, 9),
MSTPCR("rtc0", "r_clk", 1, 8),
MSTPCR("atapi0", "sh_clk", 2, 28),
MSTPCR("adc0", "peripheral_clk", 2, 28),
MSTPCR("tpu0", "bus_clk", 2, 25),
MSTPCR("irda0", "peripheral_clk", 2, 24),
MSTPCR("tsif0", "bus_clk", 2, 22),
MSTPCR("icb0", "bus_clk", 2, 21),
MSTPCR("sdhi0", "bus_clk", 2, 18),
MSTPCR("sdhi1", "bus_clk", 2, 17),
MSTPCR("keysc0", "r_clk", 2, 14),
MSTPCR("usb0", "bus_clk", 2, 11),
MSTPCR("2dg0", "bus_clk", 2, 10),
MSTPCR("siu0", "bus_clk", 2, 8),
MSTPCR("veu1", "bus_clk", 2, 6),
MSTPCR("vou0", "bus_clk", 2, 5),
MSTPCR("beu0", "bus_clk", 2, 4),
MSTPCR("ceu0", "bus_clk", 2, 3),
MSTPCR("veu0", "bus_clk", 2, 2),
MSTPCR("vpu0", "bus_clk", 2, 1),
MSTPCR("lcdc0", "bus_clk", 2, 0),
MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
MSTPCR("ic0", "cpu_clk", 0, 30, 0),
MSTPCR("oc0", "cpu_clk", 0, 29, 0),
MSTPCR("l2c0", "sh_clk", 0, 28, 0),
MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
MSTPCR("intc0", "cpu_clk", 0, 22, 0),
MSTPCR("dmac0", "bus_clk", 0, 21, 0),
MSTPCR("sh0", "sh_clk", 0, 20, 0),
MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
MSTPCR("cmt0", "r_clk", 0, 14, 0),
MSTPCR("rwdt0", "r_clk", 0, 13, 0),
MSTPCR("dmac1", "bus_clk", 0, 12, 0),
MSTPCR("tmu1", "peripheral_clk", 0, 11, 0),
MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
MSTPCR("scif3", "bus_clk", 0, 6, 0),
MSTPCR("scif4", "bus_clk", 0, 5, 0),
MSTPCR("scif5", "bus_clk", 0, 4, 0),
MSTPCR("msiof0", "bus_clk", 0, 2, 0),
MSTPCR("msiof1", "bus_clk", 0, 1, 0),
MSTPCR("meram0", "sh_clk", 0, 0, CLK_ENABLE_ON_INIT),
MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
MSTPCR("rtc0", "r_clk", 1, 8, 0),
MSTPCR("atapi0", "sh_clk", 2, 28, 0),
MSTPCR("adc0", "peripheral_clk", 2, 28, 0),
MSTPCR("tpu0", "bus_clk", 2, 25, 0),
MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
MSTPCR("tsif0", "bus_clk", 2, 22, 0),
MSTPCR("icb0", "bus_clk", 2, 21, 0),
MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
MSTPCR("keysc0", "r_clk", 2, 14, 0),
MSTPCR("usb0", "bus_clk", 2, 11, 0),
MSTPCR("2dg0", "bus_clk", 2, 10, 0),
MSTPCR("siu0", "bus_clk", 2, 8, 0),
MSTPCR("veu1", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
MSTPCR("vou0", "bus_clk", 2, 5, 0),
MSTPCR("beu0", "bus_clk", 2, 4, 0),
MSTPCR("ceu0", "bus_clk", 2, 3, 0),
MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7724)
/* See Datasheet : Overview -> Block Diagram */
MSTPCR("tlb0", "cpu_clk", 0, 31),
MSTPCR("ic0", "cpu_clk", 0, 30),
MSTPCR("oc0", "cpu_clk", 0, 29),
MSTPCR("rs0", "bus_clk", 0, 28),
MSTPCR("ilmem0", "cpu_clk", 0, 27),
MSTPCR("l2c0", "sh_clk", 0, 26),
MSTPCR("fpu0", "cpu_clk", 0, 24),
MSTPCR("intc0", "peripheral_clk", 0, 22),
MSTPCR("dmac0", "bus_clk", 0, 21),
MSTPCR("sh0", "sh_clk", 0, 20),
MSTPCR("hudi0", "peripheral_clk", 0, 19),
MSTPCR("ubc0", "cpu_clk", 0, 17),
MSTPCR("tmu0", "peripheral_clk", 0, 15),
MSTPCR("cmt0", "r_clk", 0, 14),
MSTPCR("rwdt0", "r_clk", 0, 13),
MSTPCR("dmac1", "bus_clk", 0, 12),
MSTPCR("tmu1", "peripheral_clk", 0, 10),
MSTPCR("scif0", "peripheral_clk", 0, 9),
MSTPCR("scif1", "peripheral_clk", 0, 8),
MSTPCR("scif2", "peripheral_clk", 0, 7),
MSTPCR("scif3", "bus_clk", 0, 6),
MSTPCR("scif4", "bus_clk", 0, 5),
MSTPCR("scif5", "bus_clk", 0, 4),
MSTPCR("msiof0", "bus_clk", 0, 2),
MSTPCR("msiof1", "bus_clk", 0, 1),
MSTPCR("keysc0", "r_clk", 1, 12),
MSTPCR("rtc0", "r_clk", 1, 11),
MSTPCR("i2c0", "peripheral_clk", 1, 9),
MSTPCR("i2c1", "peripheral_clk", 1, 8),
MSTPCR("mmc0", "bus_clk", 2, 29),
MSTPCR("eth0", "bus_clk", 2, 28),
MSTPCR("atapi0", "bus_clk", 2, 26),
MSTPCR("tpu0", "bus_clk", 2, 25),
MSTPCR("irda0", "peripheral_clk", 2, 24),
MSTPCR("tsif0", "bus_clk", 2, 22),
MSTPCR("usb1", "bus_clk", 2, 21),
MSTPCR("usb0", "bus_clk", 2, 20),
MSTPCR("2dg0", "bus_clk", 2, 19),
MSTPCR("sdhi0", "bus_clk", 2, 18),
MSTPCR("sdhi1", "bus_clk", 2, 17),
MSTPCR("veu1", "bus_clk", 2, 15),
MSTPCR("ceu1", "bus_clk", 2, 13),
MSTPCR("beu1", "bus_clk", 2, 12),
MSTPCR("2ddmac0", "sh_clk", 2, 10),
MSTPCR("spu0", "bus_clk", 2, 9),
MSTPCR("jpu0", "bus_clk", 2, 6),
MSTPCR("vou0", "bus_clk", 2, 5),
MSTPCR("beu0", "bus_clk", 2, 4),
MSTPCR("ceu0", "bus_clk", 2, 3),
MSTPCR("veu0", "bus_clk", 2, 2),
MSTPCR("vpu0", "bus_clk", 2, 1),
MSTPCR("lcdc0", "bus_clk", 2, 0),
MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
MSTPCR("ic0", "cpu_clk", 0, 30, 0),
MSTPCR("oc0", "cpu_clk", 0, 29, 0),
MSTPCR("rs0", "bus_clk", 0, 28, 0),
MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
MSTPCR("l2c0", "sh_clk", 0, 26, 0),
MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
MSTPCR("dmac0", "bus_clk", 0, 21, 0),
MSTPCR("sh0", "sh_clk", 0, 20, 0),
MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
MSTPCR("cmt0", "r_clk", 0, 14, 0),
MSTPCR("rwdt0", "r_clk", 0, 13, 0),
MSTPCR("dmac1", "bus_clk", 0, 12, 0),
MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
MSTPCR("scif3", "bus_clk", 0, 6, 0),
MSTPCR("scif4", "bus_clk", 0, 5, 0),
MSTPCR("scif5", "bus_clk", 0, 4, 0),
MSTPCR("msiof0", "bus_clk", 0, 2, 0),
MSTPCR("msiof1", "bus_clk", 0, 1, 0),
MSTPCR("keysc0", "r_clk", 1, 12, 0),
MSTPCR("rtc0", "r_clk", 1, 11, 0),
MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
MSTPCR("mmc0", "bus_clk", 2, 29, 0),
MSTPCR("eth0", "bus_clk", 2, 28, 0),
MSTPCR("atapi0", "bus_clk", 2, 26, 0),
MSTPCR("tpu0", "bus_clk", 2, 25, 0),
MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
MSTPCR("tsif0", "bus_clk", 2, 22, 0),
MSTPCR("usb1", "bus_clk", 2, 21, 0),
MSTPCR("usb0", "bus_clk", 2, 20, 0),
MSTPCR("2dg0", "bus_clk", 2, 19, 0),
MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT),
MSTPCR("ceu1", "bus_clk", 2, 13, 0),
MSTPCR("beu1", "bus_clk", 2, 12, 0),
MSTPCR("2ddmac0", "sh_clk", 2, 10, 0),
MSTPCR("spu0", "bus_clk", 2, 9, 0),
MSTPCR("jpu0", "bus_clk", 2, 6, 0),
MSTPCR("vou0", "bus_clk", 2, 5, 0),
MSTPCR("beu0", "bus_clk", 2, 4, 0),
MSTPCR("ceu0", "bus_clk", 2, 3, 0),
MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7343)
MSTPCR("uram0", "umem_clk", 0, 28),
MSTPCR("xymem0", "bus_clk", 0, 26),
MSTPCR("tmu0", "peripheral_clk", 0, 15),
MSTPCR("cmt0", "r_clk", 0, 14),
MSTPCR("rwdt0", "r_clk", 0, 13),
MSTPCR("scif0", "peripheral_clk", 0, 7),
MSTPCR("scif1", "peripheral_clk", 0, 6),
MSTPCR("scif2", "peripheral_clk", 0, 5),
MSTPCR("scif3", "peripheral_clk", 0, 4),
MSTPCR("i2c0", "peripheral_clk", 1, 9),
MSTPCR("i2c1", "peripheral_clk", 1, 8),
MSTPCR("sdhi0", "peripheral_clk", 2, 18),
MSTPCR("keysc0", "r_clk", 2, 14),
MSTPCR("usbf0", "peripheral_clk", 2, 11),
MSTPCR("siu0", "bus_clk", 2, 8),
MSTPCR("jpu0", "bus_clk", 2, 6),
MSTPCR("vou0", "bus_clk", 2, 5),
MSTPCR("beu0", "bus_clk", 2, 4),
MSTPCR("ceu0", "bus_clk", 2, 3),
MSTPCR("veu0", "bus_clk", 2, 2),
MSTPCR("vpu0", "bus_clk", 2, 1),
MSTPCR("lcdc0", "bus_clk", 2, 0),
MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
MSTPCR("cmt0", "r_clk", 0, 14, 0),
MSTPCR("rwdt0", "r_clk", 0, 13, 0),
MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
MSTPCR("scif1", "peripheral_clk", 0, 6, 0),
MSTPCR("scif2", "peripheral_clk", 0, 5, 0),
MSTPCR("scif3", "peripheral_clk", 0, 4, 0),
MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0),
MSTPCR("keysc0", "r_clk", 2, 14, 0),
MSTPCR("usbf0", "peripheral_clk", 2, 11, 0),
MSTPCR("siu0", "bus_clk", 2, 8, 0),
MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
MSTPCR("vou0", "bus_clk", 2, 5, 0),
MSTPCR("beu0", "bus_clk", 2, 4, 0),
MSTPCR("ceu0", "bus_clk", 2, 3, 0),
MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7366)
/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
MSTPCR("tlb0", "cpu_clk", 0, 31),
MSTPCR("ic0", "cpu_clk", 0, 30),
MSTPCR("oc0", "cpu_clk", 0, 29),
MSTPCR("rsmem0", "sh_clk", 0, 28),
MSTPCR("xymem0", "cpu_clk", 0, 26),
MSTPCR("intc30", "peripheral_clk", 0, 23),
MSTPCR("intc0", "peripheral_clk", 0, 22),
MSTPCR("dmac0", "bus_clk", 0, 21),
MSTPCR("sh0", "sh_clk", 0, 20),
MSTPCR("hudi0", "peripheral_clk", 0, 19),
MSTPCR("ubc0", "cpu_clk", 0, 17),
MSTPCR("tmu0", "peripheral_clk", 0, 15),
MSTPCR("cmt0", "r_clk", 0, 14),
MSTPCR("rwdt0", "r_clk", 0, 13),
MSTPCR("flctl0", "peripheral_clk", 0, 10),
MSTPCR("scif0", "peripheral_clk", 0, 7),
MSTPCR("scif1", "bus_clk", 0, 6),
MSTPCR("scif2", "bus_clk", 0, 5),
MSTPCR("msiof0", "peripheral_clk", 0, 2),
MSTPCR("sbr0", "peripheral_clk", 0, 1),
MSTPCR("i2c0", "peripheral_clk", 1, 9),
MSTPCR("icb0", "bus_clk", 2, 27),
MSTPCR("meram0", "sh_clk", 2, 26),
MSTPCR("dacc0", "peripheral_clk", 2, 24),
MSTPCR("dacy0", "peripheral_clk", 2, 23),
MSTPCR("tsif0", "bus_clk", 2, 22),
MSTPCR("sdhi0", "bus_clk", 2, 18),
MSTPCR("mmcif0", "bus_clk", 2, 17),
MSTPCR("usb0", "bus_clk", 2, 11),
MSTPCR("siu0", "bus_clk", 2, 8),
MSTPCR("veu1", "bus_clk", 2, 7),
MSTPCR("vou0", "bus_clk", 2, 5),
MSTPCR("beu0", "bus_clk", 2, 4),
MSTPCR("ceu0", "bus_clk", 2, 3),
MSTPCR("veu0", "bus_clk", 2, 2),
MSTPCR("vpu0", "bus_clk", 2, 1),
MSTPCR("lcdc0", "bus_clk", 2, 0),
MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
MSTPCR("ic0", "cpu_clk", 0, 30, 0),
MSTPCR("oc0", "cpu_clk", 0, 29, 0),
MSTPCR("rsmem0", "sh_clk", 0, 28, CLK_ENABLE_ON_INIT),
MSTPCR("xymem0", "cpu_clk", 0, 26, CLK_ENABLE_ON_INIT),
MSTPCR("intc30", "peripheral_clk", 0, 23, 0),
MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
MSTPCR("dmac0", "bus_clk", 0, 21, 0),
MSTPCR("sh0", "sh_clk", 0, 20, 0),
MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
MSTPCR("cmt0", "r_clk", 0, 14, 0),
MSTPCR("rwdt0", "r_clk", 0, 13, 0),
MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
MSTPCR("scif1", "bus_clk", 0, 6, 0),
MSTPCR("scif2", "bus_clk", 0, 5, 0),
MSTPCR("msiof0", "peripheral_clk", 0, 2, 0),
MSTPCR("sbr0", "peripheral_clk", 0, 1, 0),
MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
MSTPCR("icb0", "bus_clk", 2, 27, 0),
MSTPCR("meram0", "sh_clk", 2, 26, 0),
MSTPCR("dacc0", "peripheral_clk", 2, 24, 0),
MSTPCR("dacy0", "peripheral_clk", 2, 23, 0),
MSTPCR("tsif0", "bus_clk", 2, 22, 0),
MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
MSTPCR("mmcif0", "bus_clk", 2, 17, 0),
MSTPCR("usb0", "bus_clk", 2, 11, 0),
MSTPCR("siu0", "bus_clk", 2, 8, 0),
MSTPCR("veu1", "bus_clk", 2, 7, CLK_ENABLE_ON_INIT),
MSTPCR("vou0", "bus_clk", 2, 5, 0),
MSTPCR("beu0", "bus_clk", 2, 4, 0),
MSTPCR("ceu0", "bus_clk", 2, 3, 0),
MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
};
......
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
View file @ 154502e1
......@@ -223,12 +223,6 @@ static struct platform_device *sh7343_devices[] __initdata = {
static int __init sh7343_devices_setup(void)
{
clk_always_enable("uram0"); /* URAM */
clk_always_enable("xymem0"); /* XYMEM */
clk_always_enable("veu0"); /* VEU */
clk_always_enable("vpu0"); /* VPU */
clk_always_enable("jpu0"); /* JPU */
platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
......
arch/sh/kernel/cpu/sh4a/setup-sh7366.c
View file @ 154502e1
......@@ -212,12 +212,6 @@ static struct platform_device *sh7366_devices[] __initdata = {
static int __init sh7366_devices_setup(void)
{
clk_always_enable("rsmem0"); /* RSMEM */
clk_always_enable("xymem0"); /* XYMEM */
clk_always_enable("veu1"); /* VEU-2 */
clk_always_enable("veu0"); /* VEU-1 */
clk_always_enable("vpu0"); /* VPU */
platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
......
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
View file @ 154502e1
......@@ -352,12 +352,6 @@ static struct platform_device *sh7722_devices[] __initdata = {
static int __init sh7722_devices_setup(void)
{
clk_always_enable("uram0"); /* URAM */
clk_always_enable("xymem0"); /* XYMEM */
clk_always_enable("veu0"); /* VEU */
clk_always_enable("vpu0"); /* VPU */
clk_always_enable("jpu0"); /* JPU */
platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
......
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
View file @ 154502e1
......@@ -460,11 +460,6 @@ static struct platform_device *sh7723_devices[] __initdata = {
static int __init sh7723_devices_setup(void)
{
clk_always_enable("meram0"); /* MERAM */
clk_always_enable("veu1"); /* VEU2H1 */
clk_always_enable("veu0"); /* VEU2H0 */
clk_always_enable("vpu0"); /* VPU */
platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
......
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
View file @ 154502e1
......@@ -281,10 +281,6 @@ static struct platform_device *sh7724_devices[] __initdata = {
static int __init sh7724_devices_setup(void)
{
clk_always_enable("vpu0"); /* VPU */
clk_always_enable("veu1"); /* VEU3F1 */
clk_always_enable("veu0"); /* VEU3F0 */
platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
......
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