SYSLINK: procmgr - adjust memory map for SDC

This patch programs all the required memory regions for Ducati
as TLBs to provide a sw solution for the hw bug in SDC. A total
of 49MB of physical memory is mapped, and the physical address is
assumed to begin at 0x88000000.
Signed-off-by: Suman Anna <s-anna@ti.com>

arch/arm/plat-omap/include/syslink/ducatienabler.h

@@ -74,7 +74,7 @@
 
 
 
-
+#if 0  /* Original definitions for OMAP4430. */
 /* Define the various Ducati Memory Regions. */
 /* The first 4K page of BOOTVECS is programmed as a TLB entry. The remaining */
 /* three pages are not used and are mapped to minimize number of PTEs */
@@ -101,6 +101,64 @@
 
 #define DUCATI_SW_DMM_ADDR			0x80000000
 #define DUCATI_SW_DMM_LEN			0x400000
+#endif
+
+/* OMAP4430 SDC definitions */
+#define L4_PERIPHERAL_L4CFG			0x4A000000
+#define DUCATI_PERIPHERAL_L4CFG			0xAA000000
+
+#define L4_PERIPHERAL_L4PER			0x48000000
+#define DUCATI_PERIPHERAL_L4PER			0xA8000000
+
+#define L3_IVAHD_CONFIG				0x5A000000
+#define DUCATI_IVAHD_CONFIG			0xBA000000
+
+#define L3_IVAHD_SL2				0x5B000000
+#define DUCATI_IVAHD_SL2			0xBB000000
+
+#define L3_TILER_MODE0_1_ADDR			0x60000000
+#define DUCATI_TILER_MODE0_1_ADDR		0x60000000
+#define DUCATI_TILER_MODE0_1_LEN		0x10000000
+
+#define L3_TILER_MODE3_ADDR			0x78000000
+#define DUCATI_TILER_MODE3_ADDR			0x78000000
+#define DUCATI_TILER_MODE3_LEN			0x8000000
+
+#define DUCATI_BOOTVECS_UNUSED_ADDR		0x1000
+#define DUCATI_BOOTVECS_UNUSED_LEN		0x3000
+
+#define DUCATI_MEM_CODE_SYSM3_ADDR		0x4000
+#define DUCATI_MEM_CODE_SYSM3_LEN		0x1FC000
+
+#define DUCATI_MEM_CODE_APPM3_ADDR		0x800000
+#define DUCATI_MEM_CODE_APPM3_LEN		0x200000
+
+#define DUCATI_MEM_CONST_SYSM3_ADDR		0x80000000
+#define DUCATI_MEM_CONST_SYSM3_LEN		0x100000
+
+#define DUCATI_MEM_CONST_APPM3_ADDR		0x80100000
+#define DUCATI_MEM_CONST_APPM3_LEN		0x100000
+
+#define DUCATI_MEM_HEAP_SYSM3_ADDR		0x80200000
+#define DUCATI_MEM_HEAP_SYSM3_LEN		0x100000
+
+#define DUCATI_MEM_HEAP_APPM3_ADDR		0x80300000
+#define DUCATI_MEM_HEAP_APPM3_LEN		0x1000000
+
+#define DUCATI_MEM_MPU_DUCATI_SHMEM_ADDR	0x81300000
+#define DUCATI_MEM_MPU_DUCATI_SHMEM_LEN		0xC00000
+
+#define DUCATI_MEM_IPC_SHMEM_ADDR		0x81F00000
+#define DUCATI_MEM_IPC_SHMEM_LEN		0x100000
+
+#define DUCATI_MEM_IPC_HEAP0_ADDR		0xA0000000
+#define DUCATI_MEM_IPC_HEAP0_LEN		0x55000
+
+#define DUCATI_MEM_IPC_HEAP1_ADDR		0xA0055000
+#define DUCATI_MEM_IPC_HEAP1_LEN		0x55000
+
+#define DUCATI_MEM_IPC_HEAP2_ADDR		0xA00AA000
+#define DUCATI_MEM_IPC_HEAP2_LEN		0x56000
 
 
 /* Types of mapping attributes */
@@ -145,6 +203,7 @@ struct memory_entry {
 	u32 ul_size;
 };
 
+#if 0 /* Original definitions for OMAP4430. */
 static const struct mmu_entry l4_map[] = {
 	/*  Mailbox 4KB*/
 	{L4_PERIPHERAL_MBOX, DUCATI_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB},
@@ -188,6 +247,37 @@ static const struct  memory_entry l3_memory_regions[] = {
 	/*  DMM*/
 	{DUCATI_SW_DMM_ADDR, DUCATI_SW_DMM_LEN},
 };
+#endif
+
+/* OMAP4430 SDC definitions */
+static const struct mmu_entry l4_map[] = {
+	/* TILER 8-bit and 16-bit modes */
+	{L3_TILER_MODE0_1_ADDR, DUCATI_TILER_MODE0_1_ADDR,
+		(HW_PAGE_SIZE_16MB * 16)},
+	/* TILER: Pages-mode */
+	{L3_TILER_MODE3_ADDR, DUCATI_TILER_MODE3_ADDR,
+		(HW_PAGE_SIZE_16MB * 8)},
+	/*  L4_CFG: Covers all modules in L4_CFG 16MB*/
+	{L4_PERIPHERAL_L4CFG, DUCATI_PERIPHERAL_L4CFG, HW_PAGE_SIZE_16MB},
+	/*  L4_PER: Covers all modules in L4_PER 16MB*/
+	{L4_PERIPHERAL_L4PER, DUCATI_PERIPHERAL_L4PER, HW_PAGE_SIZE_16MB},
+	/* IVA_HD Config: Covers all modules in IVA_HD Config space 16MB */
+	{L3_IVAHD_CONFIG, DUCATI_IVAHD_CONFIG, HW_PAGE_SIZE_16MB},
+	/* IVA_HD SL2: Covers all memory in IVA_HD SL2 space 16MB */
+	{L3_IVAHD_SL2, DUCATI_IVAHD_SL2, HW_PAGE_SIZE_16MB},
+};
+
+static const struct  memory_entry l3_memory_regions[] = {
+	/*  MEM_INTVECS_SYSM3, MEM_INTVECS_APPM3, MEM_CODE_SYSM3,
+		MEM_CODE_APPM3 */
+	{0, PAGE_SIZE_16MB},
+	/*  MEM_CONST_SYSM3, MEM_CONST_APPM3, MEM_HEAP_SYSM3, MEM_HEAP_APPM3,
+		MEM_MPU_DUCATI_SHMEM, MEM_IPC_SHMEM */
+	{DUCATI_MEM_CONST_SYSM3_ADDR, (PAGE_SIZE_16MB * 2)},
+	/*  MEM_IPC_HEAP0, MEM_IPC_HEAP1, MEM_IPC_HEAP2 */
+	{DUCATI_MEM_IPC_HEAP0_ADDR, PAGE_SIZE_1MB},
+};
+
 
 void dbg_print_ptes(bool ashow_inv_entries, bool ashow_repeat_entries);
 int ducati_setup(void);

drivers/dsp/syslink/procmgr/proc4430/ducatienabler.c

@@ -75,7 +75,8 @@
  * during the make menuconfig.
  *
  */
-#define DUCATI_BASEIMAGE_PHYSICAL_ADDRESS	0x87200000
+/* #define DUCATI_BASEIMAGE_PHYSICAL_ADDRESS	0x87200000 */
+#define DUCATI_BASEIMAGE_PHYSICAL_ADDRESS	0x88000000
 
 #define phys_to_page(phys)      pfn_to_page((phys) >> PAGE_SHIFT)
 
@@ -1028,8 +1029,10 @@ int  ducati_mmu_init(u32 a_phy_addr)
 	u32 i = 0;
 	u32 map_attrs;
 	u32 num_l3_mem_entries = 0;
+#if 0
 	u32 tiler_mapbeg = 0;
 	u32 tiler_totalsize = 0;
+#endif
 
 	num_l4_entries = (sizeof(l4_map) / sizeof(struct mmu_entry));
 	num_l3_mem_entries = sizeof(l3_memory_regions) /
@@ -1053,8 +1056,18 @@ int  ducati_mmu_init(u32 a_phy_addr)
 				l3_memory_regions[i].ul_virt_addr,
 				l3_memory_regions[i].ul_size, phys_addr);
 
+#if 0
+		/* OMAP4430 original code */
 		if (l3_memory_regions[i].ul_virt_addr == DUCATI_SHARED_IPC_ADDR)
 			shm_phys_addr = phys_addr;
+		*/
+#endif
+		/* OMAP4430 SDC code */
+		/* Adjust below logic if using cacheable shared memory */
+		if (l3_memory_regions[i].ul_virt_addr == \
+			DUCATI_MEM_IPC_HEAP0_ADDR) {
+			shm_phys_addr = phys_addr;
+		}
 
 		ret_val = add_dsp_mmu_entry(&phys_addr,
 			(u32 *)(&(l3_memory_regions[i].ul_virt_addr)),
@@ -1064,6 +1077,8 @@ int  ducati_mmu_init(u32 a_phy_addr)
 			goto error_exit;
 	}
 
+#if 0
+	/* OMAP4430 original code */
 	tiler_mapbeg = L3_TILER_VIEW0_ADDR;
 	tiler_totalsize = DUCATIVA_TILER_VIEW0_LEN;
 	phys_addr = L3_TILER_VIEW0_ADDR;
@@ -1074,6 +1089,7 @@ int  ducati_mmu_init(u32 a_phy_addr)
 	ret_val = add_entry_ext(&phys_addr, &tiler_mapbeg, tiler_totalsize);
 	if (WARN_ON(ret_val < 0))
 		goto error_exit;
+#endif
 
 	map_attrs = 0x00000000;
 	map_attrs |= DSP_MAPLITTLEENDIAN;
@@ -1291,7 +1307,8 @@ EXPORT_SYMBOL(ducati_destroy);
  */
 u32 get_ducati_virt_mem()
 {
-	shm_virt_addr = (u32)ioremap(shm_phys_addr, DUCATI_SHARED_IPC_LEN);
+	/*shm_virt_addr = (u32)ioremap(shm_phys_addr, DUCATI_SHARED_IPC_LEN);*/
+	shm_virt_addr = (u32)ioremap(shm_phys_addr, DUCATI_MEM_IPC_SHMEM_LEN);
 	return shm_virt_addr;
 }
 EXPORT_SYMBOL(get_ducati_virt_mem);