OMAP3 clock/SRAM: fix CORE DPLL M2 divider mask

3430ES2+ CORE DPLL M2 divider can divide by 1 to 31, unlike ES1, which
was more limited.  The SRAM code currently only supports dividing by 1
or 2, but we should mask off the full range of bits to guard against
the event that the previous contents of CM_CLKSEL_PLL1 included an M2
divider > 2.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

arch/arm/mach-omap2/sram34xx.S

@@ -173,7 +173,7 @@ omap3_sdrc_dlla_status:
 omap3_sdrc_dlla_ctrl:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 core_m2_mask_val:
-	.word 0xE7FFFFFF
+	.word 0x07FFFFFF
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
 	.word	. - omap3_sram_configure_core_dpll