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linux-davinci-2.6.23
Commit fe38ea56 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
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[ARM] 3246/1: S3C24XX - retab clock list in arch/arm/mach-s3c2410/clock.c 

Patch from Ben Dooks

Properly tabulate the clock table in arch/arm/mach-s3c2410/clock.c
and put the requisite commas on the end of the structs.

Fix the comment about clock enable and disable in the setup code
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 9d4ae727
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Showing with 103 additions and 103 deletions
arch/arm/mach-s3c2410/clock.c
View file @ fe38ea56
...@@ -253,100 +253,101 @@ struct clk s3c24xx_uclk = { ...@@ -253,100 +253,101 @@ struct clk s3c24xx_uclk = {
/* clock definitions */ /* clock definitions */
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ .name = "nand", {
.id = -1, .name = "nand",
.parent = &clk_h, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_h,
.ctrlbit = S3C2410_CLKCON_NAND .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_NAND,
{ .name = "lcd", }, {
.id = -1, .name = "lcd",
.parent = &clk_h, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_h,
.ctrlbit = S3C2410_CLKCON_LCDC .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_LCDC,
{ .name = "usb-host", }, {
.id = -1, .name = "usb-host",
.parent = &clk_h, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_h,
.ctrlbit = S3C2410_CLKCON_USBH .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_USBH,
{ .name = "usb-device", }, {
.id = -1, .name = "usb-device",
.parent = &clk_h, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_h,
.ctrlbit = S3C2410_CLKCON_USBD .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_USBD,
{ .name = "timers", }, {
.id = -1, .name = "timers",
.parent = &clk_p, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_PWMT .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_PWMT,
{ .name = "sdi", }, {
.id = -1, .name = "sdi",
.parent = &clk_p, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_SDI .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_SDI,
{ .name = "uart", }, {
.id = 0, .name = "uart",
.parent = &clk_p, .id = 0,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_UART0 .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_UART0,
{ .name = "uart", }, {
.id = 1, .name = "uart",
.parent = &clk_p, .id = 1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_UART1 .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_UART1,
{ .name = "uart", }, {
.id = 2, .name = "uart",
.parent = &clk_p, .id = 2,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_UART2 .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_UART2,
{ .name = "gpio", }, {
.id = -1, .name = "gpio",
.parent = &clk_p, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_GPIO .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_GPIO,
{ .name = "rtc", }, {
.id = -1, .name = "rtc",
.parent = &clk_p, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_RTC .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_RTC,
{ .name = "adc", }, {
.id = -1, .name = "adc",
.parent = &clk_p, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_ADC .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_ADC,
{ .name = "i2c", }, {
.id = -1, .name = "i2c",
.parent = &clk_p, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_IIC .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_IIC,
{ .name = "iis", }, {
.id = -1, .name = "iis",
.parent = &clk_p, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_IIS .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_IIS,
{ .name = "spi", }, {
.id = -1, .name = "spi",
.parent = &clk_p, .id = -1,
.enable = s3c24xx_clkcon_enable, .parent = &clk_p,
.ctrlbit = S3C2410_CLKCON_SPI .enable = s3c24xx_clkcon_enable,
}, .ctrlbit = S3C2410_CLKCON_SPI,
{ .name = "watchdog", }, {
.id = -1, .name = "watchdog",
.parent = &clk_p, .id = -1,
.ctrlbit = 0 .parent = &clk_p,
.ctrlbit = 0,
} }
}; };
...@@ -390,16 +391,15 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, ...@@ -390,16 +391,15 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
clk_p.rate = pclk; clk_p.rate = pclk;
clk_f.rate = fclk; clk_f.rate = fclk;
/* it looks like just setting the register here is not good /* We must be careful disabling the clocks we are not intending to
* enough, and causes the odd hang at initial boot time, so * be using at boot time, as subsytems such as the LCD which do
* do all of them indivdually. * their own DMA requests to the bus can cause the system to lockup
* if they where in the middle of requesting bus access.
* *
* I think disabling the LCD clock if the LCD is active is * Disabling the LCD clock if the LCD is active is very dangerous,
* very dangerous, and therefore the bootloader should be * and therefore the bootloader should be careful to not enable
* careful to not enable the LCD clock if it is not needed. * the LCD clock if it is not needed.
* */
* and of course, this looks neater
*/
s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0); s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0); s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
......
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