Commit d44a65f7 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Jeff Garzik

pata_hpt37x: actually clock HPT374 with 50 MHz DPLL (take 2)

The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask
including mode 5 used to check for the necessity of 66 MHz clocking -- this
caused 66 MHz clock to be used for HPT374 chip that does not tolerate it.
While fixing this, also remove PLL mode from the TODO list -- I don't think
it's still a relevant item.
Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent be456b77
...@@ -8,12 +8,10 @@ ...@@ -8,12 +8,10 @@
* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
* Portions Copyright (C) 2001 Sun Microsystems, Inc. * Portions Copyright (C) 2001 Sun Microsystems, Inc.
* Portions Copyright (C) 2003 Red Hat Inc * Portions Copyright (C) 2003 Red Hat Inc
* Portions Copyright (C) 2005-2006 MontaVista Software, Inc. * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
* *
* TODO * TODO
* PLL mode * Look into engine reset on timeout errors. Should not be required.
* Look into engine reset on timeout errors. Should not be
* required.
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
...@@ -26,7 +24,7 @@ ...@@ -26,7 +24,7 @@
#include <linux/libata.h> #include <linux/libata.h>
#define DRV_NAME "pata_hpt37x" #define DRV_NAME "pata_hpt37x"
#define DRV_VERSION "0.6.7" #define DRV_VERSION "0.6.8"
struct hpt_clock { struct hpt_clock {
u8 xfer_speed; u8 xfer_speed;
...@@ -1092,9 +1090,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) ...@@ -1092,9 +1090,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
int dpll, adjust; int dpll, adjust;
/* Compute DPLL */ /* Compute DPLL */
dpll = 2; dpll = (port->udma_mask & 0xC0) ? 3 : 2;
if (port->udma_mask & 0xE0)
dpll = 3;
f_low = (MHz[clock_slot] * 48) / MHz[dpll]; f_low = (MHz[clock_slot] * 48) / MHz[dpll];
f_high = f_low + 2; f_high = f_low + 2;
......
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