[ARM] 3381/1: ixp2000: fix slowport write timing control register fields

Patch from Lennert Buytenhek

The original version of the chip docs had the PW and SU fields in
the slowport write timing control register accidentally reversed.
This is mentioned in the errata (documentation change #4) and fixed
in newer docs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

include/asm-arm/arch-ixp2000/ixp2000-regs.h

@@ -353,8 +353,8 @@
  * Masks and shifts for various fields in the WTC and RTC registers.
  */
 #define	SLOWPORT_WRTC_MASK_HD		0x0003
-#define	SLOWPORT_WRTC_MASK_SU		0x003c
-#define	SLOWPORT_WRTC_MASK_PW		0x03c0
+#define	SLOWPORT_WRTC_MASK_PW		0x003c
+#define	SLOWPORT_WRTC_MASK_SU		0x03c0
 
 #define	SLOWPORT_WRTC_SHIFT_HD		0x00
 #define	SLOWPORT_WRTC_SHIFT_SU		0x02