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linux-davinci-2.6.23
Commit 9df40802 authored by Kevin Hilman's avatar Kevin Hilman
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Merge ../../omap/pristine

parents 779219ca 15fd6635
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Showing with 106 additions and 693 deletions
Makefile
View file @ 9df40802
......@@ -11,7 +11,7 @@ NAME=Crazed Snow-Weasel
# expect to learn how to build the kernel reading this file.
# Add custom flags here to avoid conflict with updates
EXTRAVERSION := $(EXTRAVERSION)-omap2
EXTRAVERSION := $(EXTRAVERSION)-omap1
# Do not print "Entering directory ..."
MAKEFLAGS += --no-print-directory
......
arch/arm/mach-omap1/board-ams-delta.c
View file @ 9df40802
......@@ -91,6 +91,15 @@ static struct omap_board_config_kernel ams_delta_config[] = {
{ OMAP_TAG_USB, &ams_delta_usb_config },
};
static struct platform_device ams_delta_led_device = {
.name = "ams-delta-led",
.id = -1
};
static struct platform_device *ams_delta_devices[] __initdata = {
&ams_delta_led_device,
};
static void __init ams_delta_init(void)
{
iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
......@@ -101,6 +110,8 @@ static void __init ams_delta_init(void)
/* Clear latch2 (NAND, LCD, modem enable) */
ams_delta_latch2_write(~0, 0);
platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
}
static void __init ams_delta_map_io(void)
......
arch/arm/mach-omap2/board-h4.c
View file @ 9df40802
......@@ -156,6 +156,7 @@ static struct platform_device h4_smc91x_device = {
/* Select between the IrDA and aGPS module
*/
#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
static int h4_select_irda(struct device *dev, int state)
{
unsigned char expa;
......@@ -212,6 +213,10 @@ static int h4_transceiver_mode(struct device *dev, int mode)
return 0;
}
#else
static int h4_select_irda(struct device *dev, int state) { return 0; }
static int h4_transceiver_mode(struct device *dev, int mode) { return 0; }
#endif
static struct omap_irda_config h4_irda_data = {
.transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
......
arch/arm/mach-omap2/clock.c
View file @ 9df40802
......@@ -103,7 +103,7 @@ static void omap2_clk_fixed_enable(struct clk *clk)
else if (clk == &apll54_ck)
cval = (1 << 6);
while (!CM_IDLEST_CKGEN & cval) { /* Wait for lock */
while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
++i;
udelay(1);
if (i == 100000)
......
arch/arm/plat-omap/dma.c
View file @ 9df40802
......@@ -1461,11 +1461,13 @@ EXPORT_SYMBOL(omap_request_dma);
EXPORT_SYMBOL(omap_free_dma);
EXPORT_SYMBOL(omap_start_dma);
EXPORT_SYMBOL(omap_stop_dma);
EXPORT_SYMBOL(omap_set_dma_callback);
EXPORT_SYMBOL(omap_enable_dma_irq);
EXPORT_SYMBOL(omap_disable_dma_irq);
EXPORT_SYMBOL(omap_set_dma_transfer_params);
EXPORT_SYMBOL(omap_set_dma_color_mode);
EXPORT_SYMBOL(omap_set_dma_write_mode);
EXPORT_SYMBOL(omap_set_dma_src_params);
EXPORT_SYMBOL(omap_set_dma_src_index);
......
arch/arm/plat-omap/dmtimer.c
View file @ 9df40802
......@@ -79,6 +79,9 @@ struct omap_dm_timer {
#ifdef CONFIG_ARCH_OMAP1
#define omap_dm_clk_enable(x)
#define omap_dm_clk_disable(x)
static struct omap_dm_timer dm_timers[] = {
{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
......@@ -92,6 +95,9 @@ static struct omap_dm_timer dm_timers[] = {
#elif defined(CONFIG_ARCH_OMAP2)
#define omap_dm_clk_enable(x) clk_enable(x)
#define omap_dm_clk_disable(x) clk_disable(x)
static struct omap_dm_timer dm_timers[] = {
{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
{ .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
......@@ -168,11 +174,15 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
#ifdef CONFIG_ARCH_OMAP2
clk_enable(timer->iclk);
clk_enable(timer->fclk);
#endif
omap_dm_clk_enable(timer->fclk);
omap_dm_clk_enable(timer->iclk);
omap_dm_timer_reset(timer);
/* Leave iclk enabled for GPT1 as it is needed for the
* system timer to work properly. */
if (timer != &dm_timers[0])
omap_dm_clk_disable(timer->iclk);
}
struct omap_dm_timer *omap_dm_timer_request(void)
......@@ -223,11 +233,14 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
void omap_dm_timer_free(struct omap_dm_timer *timer)
{
omap_dm_clk_enable(timer->iclk);
omap_dm_timer_reset(timer);
#ifdef CONFIG_ARCH_OMAP2
clk_disable(timer->iclk);
clk_disable(timer->fclk);
#endif
omap_dm_clk_disable(timer->iclk);
if (timer == &dm_timers[0])
omap_dm_clk_disable(timer->iclk);
omap_dm_clk_disable(timer->fclk);
WARN_ON(!timer->reserved);
timer->reserved = 0;
}
......@@ -276,7 +289,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
{
return timer->fclk;
return timer->fclk;
}
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
......@@ -288,29 +301,35 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
void omap_dm_timer_trigger(struct omap_dm_timer *timer)
{
omap_dm_clk_enable(timer->iclk);
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
omap_dm_clk_disable(timer->iclk);
}
void omap_dm_timer_start(struct omap_dm_timer *timer)
{
u32 l;
omap_dm_clk_enable(timer->iclk);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (!(l & OMAP_TIMER_CTRL_ST)) {
l |= OMAP_TIMER_CTRL_ST;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
omap_dm_clk_disable(timer->iclk);
}
void omap_dm_timer_stop(struct omap_dm_timer *timer)
{
u32 l;
omap_dm_clk_enable(timer->iclk);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (l & OMAP_TIMER_CTRL_ST) {
l &= ~0x1;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}
omap_dm_clk_disable(timer->iclk);
}
#ifdef CONFIG_ARCH_OMAP1
......@@ -348,6 +367,7 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
{
u32 l;
omap_dm_clk_enable(timer->iclk);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (autoreload)
l |= OMAP_TIMER_CTRL_AR;
......@@ -356,6 +376,7 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
omap_dm_clk_disable(timer->iclk);
}
void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
......@@ -363,6 +384,7 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
{
u32 l;
omap_dm_clk_enable(timer->iclk);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
if (enable)
l |= OMAP_TIMER_CTRL_CE;
......@@ -370,6 +392,7 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
l &= ~OMAP_TIMER_CTRL_CE;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
omap_dm_clk_disable(timer->iclk);
}
......@@ -378,6 +401,7 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
{
u32 l;
omap_dm_clk_enable(timer->iclk);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
OMAP_TIMER_CTRL_PT | (0x03 << 10));
......@@ -387,12 +411,14 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
l |= OMAP_TIMER_CTRL_PT;
l |= trigger << 10;
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
omap_dm_clk_disable(timer->iclk);
}
void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
{
u32 l;
omap_dm_clk_enable(timer->iclk);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
if (prescaler >= 0x00 && prescaler <= 0x07) {
......@@ -400,32 +426,51 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
l |= prescaler << 2;
}
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
omap_dm_clk_disable(timer->iclk);
}
void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
unsigned int value)
{
omap_dm_clk_enable(timer->iclk);
omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
omap_dm_clk_disable(timer->iclk);
}
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
{
return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
unsigned int l;
omap_dm_clk_enable(timer->iclk);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
omap_dm_clk_disable(timer->iclk);
return l;
}
void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
{
omap_dm_clk_enable(timer->iclk);
omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
omap_dm_clk_disable(timer->iclk);
}
unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
{
return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
unsigned int l;
omap_dm_clk_enable(timer->iclk);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
omap_dm_clk_disable(timer->iclk);
return l;
}
void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
{
return omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
omap_dm_clk_enable(timer->iclk);
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
omap_dm_clk_disable(timer->iclk);
}
int omap_dm_timers_active(void)
......@@ -436,9 +481,13 @@ int omap_dm_timers_active(void)
struct omap_dm_timer *timer;
timer = &dm_timers[i];
omap_dm_clk_enable(timer->iclk);
if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
OMAP_TIMER_CTRL_ST)
OMAP_TIMER_CTRL_ST) {
omap_dm_clk_disable(timer->iclk);
return 1;
}
omap_dm_clk_disable(timer->iclk);
}
return 0;
}
......
arch/arm/plat-omap/dsp/dsp_common.c
View file @ 9df40802
......@@ -59,7 +59,6 @@ struct cpustat {
void (*mem_rel_cb)(void);
};
struct cpustat cpustat = {
.lock = __MUTEX_INITIALIZER(cpustat.lock),
.stat = CPUSTAT_RESET,
.icrmask = 0xffff,
};
......@@ -243,6 +242,8 @@ static int init_done;
static int __init omap_dsp_init(void)
{
mutex_init(&cpustat.lock);
dspmem_size = 0;
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
......@@ -544,4 +545,6 @@ EXPORT_SYMBOL(dsp_register_mem_cb);
EXPORT_SYMBOL(dsp_unregister_mem_cb);
EXPORT_SYMBOL(__cpu_flush_kern_tlb_range);
EXPORT_SYMBOL(cpu_architecture);
EXPORT_SYMBOL(pmd_clear_bad);
#endif
arch/arm/plat-omap/gpio.c
View file @ 9df40802
......@@ -216,7 +216,7 @@ static inline int gpio_valid(int gpio)
return -1;
#ifndef CONFIG_ARCH_OMAP24XX
if (OMAP_GPIO_IS_MPUIO(gpio)) {
if (gpio >= MAX_GPIO_LINES + 16)
if (gpio >= OMAP_MAX_GPIO_LINES + 16)
return -1;
return 0;
}
......@@ -985,7 +985,7 @@ static int __init _omap_gpio_init(void)
else
clk_enable(gpio_ick);
gpio_fck = clk_get(NULL, "gpios_fck");
if (IS_ERR(gpio_ick))
if (IS_ERR(gpio_fck))
printk("Could not get gpios_fck\n");
else
clk_enable(gpio_fck);
......
arch/arm/plat-omap/pm.c deleted 100644 → 0
View file @ 779219ca
/*
* linux/arch/arm/plat-omap/pm.c
*
* OMAP Power Management Routines
*
* Original code for the SA11x0:
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
*
* Modified for the PXA250 by Nicolas Pitre:
* Copyright (c) 2002 Monta Vista Software, Inc.
*
* Modified for the OMAP1510 by David Singleton:
* Copyright (c) 2002 Monta Vista Software, Inc.
*
* Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/pm.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/pm.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/arch/irqs.h>
#include <asm/arch/tc.h>
#include <asm/arch/pm.h>
#include <asm/arch/mux.h>
#include <asm/arch/tps65010.h>
#include <asm/arch/dsp_common.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
static void (*omap_sram_idle)(void) = NULL;
static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
/*
* Let's power down on idle, but only if we are really
* idle, because once we start down the path of
* going idle we continue to do idle even if we get
* a clock tick interrupt . .
*/
void omap_pm_idle(void)
{
unsigned int mask32 = 0;
/*
* If the DSP is being used let's just idle the CPU, the overhead
* to wake up from Big Sleep is big, milliseconds versus micro
* seconds for wait for interrupt.
*/
local_irq_disable();
local_fiq_disable();
if (need_resched()) {
local_fiq_enable();
local_irq_enable();
return;
}
mask32 = omap_readl(ARM_SYSST);
/*
* Prevent the ULPD from entering low power state by setting
* POWER_CTRL_REG:4 = 0
*/
omap_writew(omap_readw(ULPD_POWER_CTRL) &
~ULPD_DEEP_SLEEP_TRANSITION_EN, ULPD_POWER_CTRL);
/*
* Since an interrupt may set up a timer, we don't want to
* reprogram the hardware timer with interrupts enabled.
* Re-enable interrupts only after returning from idle.
*/
timer_dyn_reprogram();
if ((mask32 & DSP_IDLE) == 0) {
__asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
} else
omap_sram_idle();
local_fiq_enable();
local_irq_enable();
}
/*
* Configuration of the wakeup event is board specific. For the
* moment we put it into this helper function. Later it may move
* to board specific files.
*/
static void omap_pm_wakeup_setup(void)
{
u32 level1_wake = 0;
u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
/*
* Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
* and the L2 wakeup interrupts: keypad and UART2. Note that the
* drivers must still separately call omap_set_gpio_wakeup() to
* wake up to a GPIO interrupt.
*/
if (cpu_is_omap730())
level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_730_IH2_IRQ);
else if (cpu_is_omap1510())
level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
omap_writel(~level1_wake, OMAP_IH1_MIR);
if (cpu_is_omap730()) {
omap_writel(~level2_wake, OMAP_IH2_0_MIR);
omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), OMAP_IH2_1_MIR);
} else if (cpu_is_omap1510()) {
level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
omap_writel(~level2_wake, OMAP_IH2_MIR);
} else if (cpu_is_omap16xx()) {
level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
omap_writel(~level2_wake, OMAP_IH2_0_MIR);
/* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
omap_writel(~0x0, OMAP_IH2_2_MIR);
omap_writel(~0x0, OMAP_IH2_3_MIR);
}
/* New IRQ agreement, recalculate in cascade order */
omap_writel(1, OMAP_IH2_CONTROL);
omap_writel(1, OMAP_IH1_CONTROL);
}
void omap_pm_suspend(void)
{
unsigned long arg0 = 0, arg1 = 0;
printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
omap_serial_wake_trigger(1);
if (machine_is_omap_osk()) {
/* Stop LED1 (D9) blink */
tps65010_set_led(LED1, OFF);
}
omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
/*
* Step 1: turn off interrupts (FIXME: NOTE: already disabled)
*/
local_irq_disable();
local_fiq_disable();
/*
* Step 2: save registers
*
* The omap is a strange/beautiful device. The caches, memory
* and register state are preserved across power saves.
* We have to save and restore very little register state to
* idle the omap.
*
* Save interrupt, MPUI, ARM and UPLD control registers.
*/
if (cpu_is_omap730()) {
MPUI730_SAVE(OMAP_IH1_MIR);
MPUI730_SAVE(OMAP_IH2_0_MIR);
MPUI730_SAVE(OMAP_IH2_1_MIR);
MPUI730_SAVE(MPUI_CTRL);
MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI730_SAVE(MPUI_DSP_API_CONFIG);
MPUI730_SAVE(EMIFS_CONFIG);
MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
} else if (cpu_is_omap1510()) {
MPUI1510_SAVE(OMAP_IH1_MIR);
MPUI1510_SAVE(OMAP_IH2_MIR);
MPUI1510_SAVE(MPUI_CTRL);
MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
MPUI1510_SAVE(EMIFS_CONFIG);
MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
} else if (cpu_is_omap16xx()) {
MPUI1610_SAVE(OMAP_IH1_MIR);
MPUI1610_SAVE(OMAP_IH2_0_MIR);
MPUI1610_SAVE(OMAP_IH2_1_MIR);
MPUI1610_SAVE(OMAP_IH2_2_MIR);
MPUI1610_SAVE(OMAP_IH2_3_MIR);
MPUI1610_SAVE(MPUI_CTRL);
MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
MPUI1610_SAVE(EMIFS_CONFIG);
MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
}
ARM_SAVE(ARM_CKCTL);
ARM_SAVE(ARM_IDLECT1);
ARM_SAVE(ARM_IDLECT2);
if (!(cpu_is_omap1510()))
ARM_SAVE(ARM_IDLECT3);
ARM_SAVE(ARM_EWUPCT);
ARM_SAVE(ARM_RSTCT1);
ARM_SAVE(ARM_RSTCT2);
ARM_SAVE(ARM_SYSST);
ULPD_SAVE(ULPD_CLOCK_CTRL);
ULPD_SAVE(ULPD_STATUS_REQ);
/* (Step 3 removed - we now allow deep sleep by default) */
/*
* Step 4: OMAP DSP Shutdown
*/
/*
* Step 5: Wakeup Event Setup
*/
omap_pm_wakeup_setup();
/*
* Step 6: ARM and Traffic controller shutdown
*/
/* disable ARM watchdog */
omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
/*
* Step 6b: ARM and Traffic controller shutdown
*
* Step 6 continues here. Prepare jump to power management
* assembly code in internal SRAM.
*
* Since the omap_cpu_suspend routine has been copied to
* SRAM, we'll do an indirect procedure call to it and pass the
* contents of arm_idlect1 and arm_idlect2 so it can restore
* them when it wakes up and it will return.
*/
arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
/*
* Step 6c: ARM and Traffic controller shutdown
*
* Jump to assembly code. The processor will stay there
* until wake up.
*/
omap_sram_suspend(arg0, arg1);
/*
* If we are here, processor is woken up!
*/
/*
* Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
*/
if (!(cpu_is_omap1510()))
ARM_RESTORE(ARM_IDLECT3);
ARM_RESTORE(ARM_CKCTL);
ARM_RESTORE(ARM_EWUPCT);
ARM_RESTORE(ARM_RSTCT1);
ARM_RESTORE(ARM_RSTCT2);
ARM_RESTORE(ARM_SYSST);
ULPD_RESTORE(ULPD_CLOCK_CTRL);
ULPD_RESTORE(ULPD_STATUS_REQ);
if (cpu_is_omap730()) {
MPUI730_RESTORE(EMIFS_CONFIG);
MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
MPUI730_RESTORE(OMAP_IH1_MIR);
MPUI730_RESTORE(OMAP_IH2_0_MIR);
MPUI730_RESTORE(OMAP_IH2_1_MIR);
} else if (cpu_is_omap1510()) {
MPUI1510_RESTORE(MPUI_CTRL);
MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
MPUI1510_RESTORE(EMIFS_CONFIG);
MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
MPUI1510_RESTORE(OMAP_IH1_MIR);
MPUI1510_RESTORE(OMAP_IH2_MIR);
} else if (cpu_is_omap16xx()) {
MPUI1610_RESTORE(MPUI_CTRL);
MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
MPUI1610_RESTORE(EMIFS_CONFIG);
MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
MPUI1610_RESTORE(OMAP_IH1_MIR);
MPUI1610_RESTORE(OMAP_IH2_0_MIR);
MPUI1610_RESTORE(OMAP_IH2_1_MIR);
MPUI1610_RESTORE(OMAP_IH2_2_MIR);
MPUI1610_RESTORE(OMAP_IH2_3_MIR);
}
omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
/*
* Reenable interrupts
*/
local_irq_enable();
local_fiq_enable();
omap_serial_wake_trigger(0);
printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
if (machine_is_omap_osk()) {
/* Let LED1 (D9) blink again */
tps65010_set_led(LED1, BLINK);
}
}
#if defined(DEBUG) && defined(CONFIG_PROC_FS)
static int g_read_completed;
/*
* Read system PM registers for debugging
*/
static int omap_pm_read_proc(
char *page_buffer,
char **my_first_byte,
off_t virtual_start,
int length,
int *eof,
void *data)
{
int my_buffer_offset = 0;
char * const my_base = page_buffer;
ARM_SAVE(ARM_CKCTL);
ARM_SAVE(ARM_IDLECT1);
ARM_SAVE(ARM_IDLECT2);
if (!(cpu_is_omap1510()))
ARM_SAVE(ARM_IDLECT3);
ARM_SAVE(ARM_EWUPCT);
ARM_SAVE(ARM_RSTCT1);
ARM_SAVE(ARM_RSTCT2);
ARM_SAVE(ARM_SYSST);
ULPD_SAVE(ULPD_IT_STATUS);
ULPD_SAVE(ULPD_CLOCK_CTRL);
ULPD_SAVE(ULPD_SOFT_REQ);
ULPD_SAVE(ULPD_STATUS_REQ);
ULPD_SAVE(ULPD_DPLL_CTRL);
ULPD_SAVE(ULPD_POWER_CTRL);
if (cpu_is_omap730()) {
MPUI730_SAVE(MPUI_CTRL);
MPUI730_SAVE(MPUI_DSP_STATUS);
MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI730_SAVE(MPUI_DSP_API_CONFIG);
MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
MPUI730_SAVE(EMIFS_CONFIG);
} else if (cpu_is_omap1510()) {
MPUI1510_SAVE(MPUI_CTRL);
MPUI1510_SAVE(MPUI_DSP_STATUS);
MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
MPUI1510_SAVE(EMIFS_CONFIG);
} else if (cpu_is_omap16xx()) {
MPUI1610_SAVE(MPUI_CTRL);
MPUI1610_SAVE(MPUI_DSP_STATUS);
MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
MPUI1610_SAVE(EMIFS_CONFIG);
}
if (virtual_start == 0) {
g_read_completed = 0;
my_buffer_offset += sprintf(my_base + my_buffer_offset,
"ARM_CKCTL_REG: 0x%-8x \n"
"ARM_IDLECT1_REG: 0x%-8x \n"
"ARM_IDLECT2_REG: 0x%-8x \n"
"ARM_IDLECT3_REG: 0x%-8x \n"
"ARM_EWUPCT_REG: 0x%-8x \n"
"ARM_RSTCT1_REG: 0x%-8x \n"
"ARM_RSTCT2_REG: 0x%-8x \n"
"ARM_SYSST_REG: 0x%-8x \n"
"ULPD_IT_STATUS_REG: 0x%-4x \n"
"ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
"ULPD_SOFT_REQ_REG: 0x%-4x \n"
"ULPD_DPLL_CTRL_REG: 0x%-4x \n"
"ULPD_STATUS_REQ_REG: 0x%-4x \n"
"ULPD_POWER_CTRL_REG: 0x%-4x \n",
ARM_SHOW(ARM_CKCTL),
ARM_SHOW(ARM_IDLECT1),
ARM_SHOW(ARM_IDLECT2),
ARM_SHOW(ARM_IDLECT3),
ARM_SHOW(ARM_EWUPCT),
ARM_SHOW(ARM_RSTCT1),
ARM_SHOW(ARM_RSTCT2),
ARM_SHOW(ARM_SYSST),
ULPD_SHOW(ULPD_IT_STATUS),
ULPD_SHOW(ULPD_CLOCK_CTRL),
ULPD_SHOW(ULPD_SOFT_REQ),
ULPD_SHOW(ULPD_DPLL_CTRL),
ULPD_SHOW(ULPD_STATUS_REQ),
ULPD_SHOW(ULPD_POWER_CTRL));
if (cpu_is_omap730()) {
my_buffer_offset += sprintf(my_base + my_buffer_offset,
"MPUI730_CTRL_REG 0x%-8x \n"
"MPUI730_DSP_STATUS_REG: 0x%-8x \n"
"MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
"MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
"MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
"MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
MPUI730_SHOW(MPUI_CTRL),
MPUI730_SHOW(MPUI_DSP_STATUS),
MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
MPUI730_SHOW(MPUI_DSP_API_CONFIG),
MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
MPUI730_SHOW(EMIFS_CONFIG));
} else if (cpu_is_omap1510()) {
my_buffer_offset += sprintf(my_base + my_buffer_offset,
"MPUI1510_CTRL_REG 0x%-8x \n"
"MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
"MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
"MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
"MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
"MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
MPUI1510_SHOW(MPUI_CTRL),
MPUI1510_SHOW(MPUI_DSP_STATUS),
MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
MPUI1510_SHOW(EMIFS_CONFIG));
} else if (cpu_is_omap16xx()) {
my_buffer_offset += sprintf(my_base + my_buffer_offset,
"MPUI1610_CTRL_REG 0x%-8x \n"
"MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
"MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
"MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
"MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
"MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
MPUI1610_SHOW(MPUI_CTRL),
MPUI1610_SHOW(MPUI_DSP_STATUS),
MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
MPUI1610_SHOW(EMIFS_CONFIG));
}
g_read_completed++;
} else if (g_read_completed >= 1) {
*eof = 1;
return 0;
}
g_read_completed++;
*my_first_byte = page_buffer;
return my_buffer_offset;
}
static void omap_pm_init_proc(void)
{
struct proc_dir_entry *entry;
entry = create_proc_read_entry("driver/omap_pm",
S_IWUSR | S_IRUGO, NULL,
omap_pm_read_proc, NULL);
}
#endif /* DEBUG && CONFIG_PROC_FS */
/*
* omap_pm_prepare - Do preliminary suspend work.
* @state: suspend state we're entering.
*
*/
//#include <asm/hardware.h>
static int omap_pm_prepare(suspend_state_t state)
{
int error = 0;
switch (state)
{
case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM:
break;
case PM_SUSPEND_DISK:
return -ENOTSUPP;
default:
return -EINVAL;
}
return error;
}
/*
* omap_pm_enter - Actually enter a sleep state.
* @state: State we're entering.
*
*/
static int omap_pm_enter(suspend_state_t state)
{
switch (state)
{
case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM:
omap_pm_suspend();
break;
case PM_SUSPEND_DISK:
return -ENOTSUPP;
default:
return -EINVAL;
}
return 0;
}
/**
* omap_pm_finish - Finish up suspend sequence.
* @state: State we're coming out of.
*
* This is called after we wake back up (or if entering the sleep state
* failed).
*/
static int omap_pm_finish(suspend_state_t state)
{
return 0;
}
static irqreturn_t omap_wakeup_interrupt(int irq, void * dev,
struct pt_regs * regs)
{
return IRQ_HANDLED;
}
static struct irqaction omap_wakeup_irq = {
.name = "peripheral wakeup",
.flags = IRQF_DISABLED,
.handler = omap_wakeup_interrupt
};
static struct pm_ops omap_pm_ops ={
.pm_disk_mode = 0,
.prepare = omap_pm_prepare,
.enter = omap_pm_enter,
.finish = omap_pm_finish,
};
static int __init omap_pm_init(void)
{
printk("Power Management for TI OMAP.\n");
/*
* We copy the assembler sleep/wakeup routines to SRAM.
* These routines need to be in SRAM as that's the only
* memory the MPU can see when it wakes up.
*/
if (cpu_is_omap730()) {
omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
omap730_idle_loop_suspend_sz);
omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
omap730_cpu_suspend_sz);
} else if (cpu_is_omap1510()) {
omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
omap1510_idle_loop_suspend_sz);
omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
omap1510_cpu_suspend_sz);
} else if (cpu_is_omap16xx()) {
omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
omap1610_idle_loop_suspend_sz);
omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
omap1610_cpu_suspend_sz);
}
if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
return -ENODEV;
}
pm_idle = omap_pm_idle;
if (cpu_is_omap730())
setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
else if (cpu_is_omap16xx())
setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
#if 0
/* --- BEGIN BOARD-DEPENDENT CODE --- */
/* Sleepx mask direction */
omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
/* Unmask sleepx signal */
omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
/* --- END BOARD-DEPENDENT CODE --- */
#endif
/* Program new power ramp-up time
* (0 for most boards since we don't lower voltage when in deep sleep)
*/
omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
/* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
/* Configure IDLECT3 */
if (cpu_is_omap730())
omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
else if (cpu_is_omap16xx())
omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
pm_set_ops(&omap_pm_ops);
#if defined(DEBUG) && defined(CONFIG_PROC_FS)
omap_pm_init_proc();
#endif
if (cpu_is_omap16xx()) {
/* configure LOW_PWR pin */
omap_cfg_reg(T20_1610_LOW_PWR);
}
return 0;
}
__initcall(omap_pm_init);
drivers/leds/leds-omap-pwm.c
View file @ 9df40802
......@@ -69,7 +69,7 @@ static void omap_pwm_led_power_on(struct omap_pwm_led *led)
led->powered = 1;
/* Select clock */
omap_dm_timer_set_source(led->intensity_timer, OMAP_TIMER_SRC_SYS_CLK);
omap_dm_timer_set_source(led->intensity_timer, OMAP_TIMER_SRC_32_KHZ);
/* Turn voltage on */
if (led->pdata->set_power != NULL)
......
include/asm-arm/arch-omap/board-ams-delta.h
View file @ 9df40802
......@@ -50,9 +50,20 @@
#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
#define AMS_DELTA_GPIO_PIN_CONFIG 11
#define AMS_DELTA_GPIO_PIN_NAND_RB 12
#ifndef __ASSEMBLY__
......
include/asm-arm/arch-omap/dma.h
View file @ 9df40802
......@@ -344,13 +344,13 @@ struct omap_dma_channel_params {
int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
int src_amode; /* constant , post increment, indexed , double indexed */
int src_start; /* source address : physical */
unsigned long src_start; /* source address : physical */
int src_ei; /* source element index */
int src_fi; /* source frame index */
int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
int dst_amode; /* constant , post increment, indexed , double indexed */
int dst_start; /* source address : physical */
unsigned long dst_start; /* source address : physical */
int dst_ei; /* source element index */
int dst_fi; /* source frame index */
......
sound/oss/omap-audio-aic23.c
View file @ 9df40802
......@@ -244,7 +244,6 @@ static audio_state_t aic23_state = {
.hw_remove = __exit_p(omap_aic23_remove),
.hw_suspend = omap_aic23_suspend,
.hw_resume = omap_aic23_resume,
.mutex = __MUTEX_INITIALIZER(aic23_state.mutex),
};
/* This will be defined in the audio.h */
......@@ -673,6 +672,8 @@ static int __init audio_aic23_init(void)
if (machine_is_omap_h2() || machine_is_omap_h3())
return -ENODEV;
mutex_init(&aic23_state.mutex);
if (machine_is_omap_osk()) {
/* Set MCLK to be clock input for AIC23 */
aic23_mclk = clk_get(0, "mclk");
......
sound/oss/omap-audio-tsc2101.c
View file @ 9df40802
......@@ -326,7 +326,6 @@ static audio_state_t tsc2101_state = {
.hw_remove = omap_tsc2101_remove,
.hw_suspend = omap_tsc2101_suspend,
.hw_resume = omap_tsc2101_resume,
.mutex = __MUTEX_INITIALIZER(tsc2101_state.mutex),
};
/* This will be defined in the Audio.h */
......@@ -1031,6 +1030,8 @@ static int __init audio_tsc2101_init(void)
if (machine_is_omap_osk() || machine_is_omap_innovator())
return -ENODEV;
mutex_init(&tsc2101_state.mutex);
/* register the codec with the audio driver */
if ((err = audio_register_codec(&tsc2101_state))) {
printk(KERN_ERR
......
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