Commit 470ea7eb authored by Stephen Hemminger's avatar Stephen Hemminger Committed by Jeff Garzik

[PATCH] sky2: 88E803X transmit lockup

The reason sky2 driver was locking up on transmit on the Yukon-FE chipset
is that it was misconfiguring the internal RAM buffer so the transmitter
and receiver were sharing the same space.

The code assumed there was 16K of RAM on Yukon-FE (taken from vendor driver
sk98lin which is even more f*cked up on this). Then it assigned based on that.
The giveaway was that the registers would only hold 9bits so both RX/TX
had 0..1ff for space. It is a wonder it worked at all!

This patch addresses this, and fixes an easily reproducible hang on Transmit.
Only the Yukon-FE chip is Marvell 88E803X (10/100 only) are affected.
Signed-off-by: default avatarStephen Hemminger <shemminger@osdl.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 7347b03d
...@@ -699,16 +699,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) ...@@ -699,16 +699,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
} }
/* Assign Ram Buffer allocation. /* Assign Ram Buffer allocation in units of 64bit (8 bytes) */
* start and end are in units of 4k bytes static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
* ram registers are in units of 64bit words
*/
static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
{ {
u32 start, end; pr_debug(PFX "q %d %#x %#x\n", q, start, end);
start = startk * 4096/8;
end = (endk * 4096/8) - 1;
sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
sky2_write32(hw, RB_ADDR(q, RB_START), start); sky2_write32(hw, RB_ADDR(q, RB_START), start);
...@@ -717,7 +711,7 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) ...@@ -717,7 +711,7 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
sky2_write32(hw, RB_ADDR(q, RB_RP), start); sky2_write32(hw, RB_ADDR(q, RB_RP), start);
if (q == Q_R1 || q == Q_R2) { if (q == Q_R1 || q == Q_R2) {
u32 space = (endk - startk) * 4096/8; u32 space = end - start + 1;
u32 tp = space - space/4; u32 tp = space - space/4;
/* On receive queue's set the thresholds /* On receive queue's set the thresholds
...@@ -1199,19 +1193,16 @@ static int sky2_up(struct net_device *dev) ...@@ -1199,19 +1193,16 @@ static int sky2_up(struct net_device *dev)
sky2_mac_init(hw, port); sky2_mac_init(hw, port);
/* Determine available ram buffer space (in 4K blocks). /* Determine available ram buffer space in qwords. */
* Note: not sure about the FE setting below yet ramsize = sky2_read8(hw, B2_E_0) * 4096/8;
*/
if (hw->chip_id == CHIP_ID_YUKON_FE)
ramsize = 4;
else
ramsize = sky2_read8(hw, B2_E_0);
/* Give transmitter one third (rounded up) */ if (ramsize > 6*1024/8)
rxspace = ramsize - (ramsize + 2) / 3; rxspace = ramsize - (ramsize + 2) / 3;
else
rxspace = ramsize / 2;
sky2_ramset(hw, rxqaddr[port], 0, rxspace); sky2_ramset(hw, rxqaddr[port], 0, rxspace-1);
sky2_ramset(hw, txqaddr[port], rxspace, ramsize); sky2_ramset(hw, txqaddr[port], rxspace, ramsize-1);
/* Make sure SyncQ is disabled */ /* Make sure SyncQ is disabled */
sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
......
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