ARM: DaVinci: IRQ cleanup

- Remove now obsolete #include <linux/config.h>
- Remove unnecessary header files.
- Update as per genirq patches.
- Use davinci_read/write[bwl] functions as necessary
  and re-write/cleanup the code.
Signed-off-by: Komal Shah <komal_shah802003@yahoo.com>
Signed-off-by: Kevin Hilman <khilman@mvista.com>

arch/arm/mach-davinci/irq.c

 /*
  * linux/arch/arm/mach-davinci/irq.c
  *
- * TI DaVinci INTC config file
+ * Interrupt handler for DaVinci boards.
  *
  * Copyright (C) 2006 Texas Instruments.
  *
@@ -21,111 +21,121 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  * ----------------------------------------------------------------------------
- *
  */
-
-#include <linux/config.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/module.h>
-#include <linux/sched.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
+#include <linux/irq.h>
 
 #include <asm/hardware.h>
-#include <asm/irq.h>
 #include <asm/io.h>
-
 #include <asm/mach/irq.h>
-#include <asm/arch/irq.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/memory.h>
-#include <asm/arch/hardware.h>
-
 
+#define IRQ_BIT(irq)  ((irq) & 0x1f)
 
-#define INTC_NUM_INTS_ONE_REGISTER  32
-
-#define INTC_CLEAR_INTERRUPTS       0xFFFFFFFF
 #define INTC_IDT_BASE		DAVINCI_IRAM_VIRT
-#define INTC_DISABLE_WHEN_CLEARED_MODE   0x4
-#define INTC_IRQ_ENTRY_RAW				0x2
-#define INTC_FIQ_ENTRY_RAW				0x1
 #define INTC_VECT_OFFSET	0x100
 
-static volatile intc_registers *pintc
-		= (intc_registers *) IO_ADDRESS(DAVINCI_ARM_INTC_BASE);
-
+#define FIQ_REG0_OFFSET		0x0000
+#define FIQ_REG1_OFFSET		0x0004
+#define IRQ_REG0_OFFSET		0x0008
+#define IRQ_REG1_OFFSET		0x000C
+#define IRQ_ENT_REG0_OFFSET	0x0018
+#define IRQ_ENT_REG1_OFFSET	0x001C
+#define IRQ_INCTL_REG_OFFSET	0x0020
+#define IRQ_EABASE_REG_OFFSET	0x0024
 
 static void __init davinci_intcinit(void);
 
+static inline unsigned int davinci_irq_readl(int offset)
+{
+	return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
+}
+
+static inline void davinci_irq_writel(unsigned long value, int offset)
+{
+	davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
+}
+
 /* Disable interrupt */
-static void davinci_xdisable_int(unsigned int intno)
+static void davinci_mask_irq(unsigned int irq)
 {
 	unsigned int mask;
+	u32 l;
+
+	mask = 1 << IRQ_BIT(irq);
 
-	if (intno < INTC_NUM_INTS_ONE_REGISTER) {
-		mask = 1 << intno;
-		pintc->eint0 &= ~mask;
-	} else if (intno < DAVINCI_N_AINTC_IRQ) {
-		mask = 1 << (intno - INTC_NUM_INTS_ONE_REGISTER);
-		pintc->eint1 &= ~mask;
+	if (irq > 31) {
+		l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
+		l &= ~mask;
+		davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
+	} else {
+		l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
+		l &= ~mask;
+		davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
 	}
 }
 
 /* Enable interrupt */
-static void davinci_xenable_int(unsigned int intno)
+static void davinci_unmask_irq(unsigned int irq)
 {
 	unsigned int mask;
-	if (intno < INTC_NUM_INTS_ONE_REGISTER) {
-		mask = 1 << intno;
-		pintc->eint0 |= mask;
-	} else if (intno < DAVINCI_N_AINTC_IRQ) {
-		mask = 1 << (intno - INTC_NUM_INTS_ONE_REGISTER);
-		pintc->eint1 |= mask;
+	u32 l;
+
+	mask = 1 << IRQ_BIT(irq);
+
+	if (irq > 31) {
+		l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
+		l |= mask;
+		davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
+	} else {
+		l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
+		l |= mask;
+		davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
 	}
 }
 
 /* EOI interrupt */
-static void davinci_xeoi_pic(unsigned int intno)
+static void davinci_ack_irq(unsigned int irq)
 {
 	unsigned int mask;
-	if (intno < INTC_NUM_INTS_ONE_REGISTER) {
-		mask = 1 << intno;
-		pintc->irq0 = mask;
-	} else if (intno < DAVINCI_N_AINTC_IRQ) {
-		mask = 1 << (intno - INTC_NUM_INTS_ONE_REGISTER);
-		pintc->irq1 = mask;
-	}
+
+	mask = 1 << IRQ_BIT(irq);
+
+	if (irq > 31)
+		davinci_irq_writel(mask, IRQ_REG1_OFFSET);
+	else
+		davinci_irq_writel(mask, IRQ_REG0_OFFSET);
 }
 
-static struct irq_chip irqchip_0 = {
+static struct irq_chip davinci_irq_chip_0 = {
 	.name	= "AINTC",
-	.ack = davinci_xeoi_pic,
-	.mask = davinci_xdisable_int,
-	.unmask = davinci_xenable_int,
+	.ack	= davinci_ack_irq,
+	.mask	= davinci_mask_irq,
+	.unmask = davinci_unmask_irq,
 };
 
 void __init davinci_irq_init(void)
 {
 	int i;
-	unsigned int *ptr = (unsigned int *)INTC_IDT_BASE;
+	unsigned int *idtbase = (unsigned int *)INTC_IDT_BASE;
+	unsigned int *eabase;
 
 	davinci_intcinit();
 
-	/* set up irq vectors */
-	ptr += INTC_VECT_OFFSET / (sizeof(*ptr));
-	for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
-		if (i == 0) {
-			*ptr = 0xFFFFFFFF;
-		} else {
-			*ptr = i - 1;
-		}
-		ptr++;
+	eabase = idtbase +  INTC_VECT_OFFSET / sizeof(*idtbase);
+
+	*eabase = ~0x0;
+	eabase++;
+
+	for (i = 1; i < NR_IRQS; i++) {
+		*eabase = i - 1;
+		eabase++;
 	}
 
-	/* Program the irqchip structures for ARM INTC */
-	for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
-		set_irq_chip(i, &irqchip_0);
+	/* Proggam the irqchip structures for ARM INTC */
+	for (i = 0; i < NR_IRQS; i++) {
+		set_irq_chip(i, &davinci_irq_chip_0);
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                 if (i != IRQ_TINT1_TINT34)
                         set_irq_handler(i, do_edge_IRQ);
@@ -137,23 +147,25 @@ void __init davinci_irq_init(void)
 /* ARM Interrupt Controller Initialize */
 static void __init davinci_intcinit(void)
 {
-	/* Clear all interrupt requests - write 1 to clear the interrupt */
-	pintc->fiq0 = pintc->irq0 = INTC_CLEAR_INTERRUPTS;
-	pintc->fiq1 = pintc->irq1 = INTC_CLEAR_INTERRUPTS;
+	/* Clear all interrupt requests */
+	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
+	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
+	davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
+	davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 
 	/* Disable all interrupts */
-	pintc->eint0 = pintc->eint1 = 0;
+	davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
+	davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
 
 	/* Interrupts disabled immediately. IRQ entry reflects all interrupts */
-	pintc->inctl = 0;
-
-	/* Set vector table base address
-	 * last two bits are zero which means 4 byte entry */
-	pintc->eabase = (unsigned int)INTC_VECT_OFFSET;
+	davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
 
-	/* Clear all interrupt requests - write 1 to clear the interrupt */
-	pintc->fiq0 = pintc->irq0 = INTC_CLEAR_INTERRUPTS;
-	pintc->fiq1 = pintc->irq1 = INTC_CLEAR_INTERRUPTS;
+	/* Set vector table base address - 4 byte entry */
+	davinci_irq_writel(INTC_VECT_OFFSET, IRQ_EABASE_REG_OFFSET);
 
-	return;
+	/* Clear all interrupt requests */
+	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
+	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
+	davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
+	davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 }

include/asm-arm/arch-davinci/irq.h

-/*
- *  linux/include/asm-arm/arch-davinci/irq.h
- *
- *  BRIEF MODULE DESCRIPTION
- *      DAVINCI Virtual irq definitions
- *
- *  Copyright (C) 2006 Texas Instruments.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_ARCH_IRQ_H
-#define __ASM_ARCH_IRQ_H
-
-/**************************************************************************
- * Included Files
- **************************************************************************/
-
-/**************************************************************************
- * Global Function Prototypes
- **************************************************************************/
-typedef struct intc_registers_t {
-	unsigned int fiq0;	/* 0x0 */
-	unsigned int fiq1;	/* 0x4 */
-	unsigned int irq0;	/* 0x8 */
-	unsigned int irq1;	/* 0xC */
-	unsigned int fiqentry;	/* 0x10 */
-	unsigned int irqentry;	/* 0x14 */
-	unsigned int eint0;	/* 0x18 */
-	unsigned int eint1;	/* 0x1C */
-	unsigned int inctl;	/* 0x20 */
-	unsigned int eabase;	/* 0x24 */
-	unsigned int resv1;	/* 0x28 */
-	unsigned int resv2;	/* 0x2C */
-	unsigned int intpri0;	/* 0x30 */
-	unsigned int intpri1;	/* 0x34 */
-	unsigned int intpri2;	/* 0x38 */
-	unsigned int intpri3;	/* 0x3C */
-	unsigned int intpri4;	/* 0x30 */
-	unsigned int intpri5;	/* 0x34 */
-	unsigned int intpri6;	/* 0x38 */
-	unsigned int intpri7;	/* 0x3C */
-} intc_registers;
-
-/****************************************************
- * DaVinci Interrupt numbers
- ****************************************************/
-
-#endif				/* __ASM_ARCH_IRQ_H */