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linux-davinci-2.6.23
Commit 315a6998 authored by Anton Blanchard's avatar Anton Blanchard Committed by Linus Torvalds
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[PATCH] ppc64: use c99 initialisers in cputable code 

Use c99 initialisers in the cputable code.
Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 2098eec2
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Showing with 212 additions and 153 deletions
arch/ppc64/kernel/cputable.c
View file @ 315a6998
...@@ -50,137 +50,196 @@ extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec); ...@@ -50,137 +50,196 @@ extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
struct cpu_spec cpu_specs[] = { struct cpu_spec cpu_specs[] = {
{ /* Power3 */ { /* Power3 */
0xffff0000, 0x00400000, "POWER3 (630)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00400000,
CPU_FTR_IABR | CPU_FTR_PMC8, .cpu_name = "POWER3 (630)",
COMMON_USER_PPC64, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
128, 128, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
__setup_cpu_power3, CPU_FTR_PMC8,
COMMON_PPC64_FW .cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power3,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* Power3+ */ { /* Power3+ */
0xffff0000, 0x00410000, "POWER3 (630+)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00410000,
CPU_FTR_IABR | CPU_FTR_PMC8, .cpu_name = "POWER3 (630+)",
COMMON_USER_PPC64, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
128, 128, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
__setup_cpu_power3, CPU_FTR_PMC8,
COMMON_PPC64_FW .cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power3,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* Northstar */ { /* Northstar */
0xffff0000, 0x00330000, "RS64-II (northstar)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00330000,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .cpu_name = "RS64-II (northstar)",
COMMON_USER_PPC64, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
128, 128, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
__setup_cpu_power3, CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_PPC64_FW .cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power3,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* Pulsar */ { /* Pulsar */
0xffff0000, 0x00340000, "RS64-III (pulsar)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00340000,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .cpu_name = "RS64-III (pulsar)",
COMMON_USER_PPC64, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
128, 128, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
__setup_cpu_power3, CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_PPC64_FW .cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power3,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* I-star */ { /* I-star */
0xffff0000, 0x00360000, "RS64-III (icestar)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00360000,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .cpu_name = "RS64-III (icestar)",
COMMON_USER_PPC64, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
128, 128, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
__setup_cpu_power3, CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_PPC64_FW .cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power3,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* S-star */ { /* S-star */
0xffff0000, 0x00370000, "RS64-IV (sstar)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00370000,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .cpu_name = "RS64-IV (sstar)",
COMMON_USER_PPC64, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
128, 128, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
__setup_cpu_power3, CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_PPC64_FW .cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power3,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* Power4 */ { /* Power4 */
0xffff0000, 0x00350000, "POWER4 (gp)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00350000,
.cpu_name = "POWER4 (gp)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA, CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64, .cpu_user_features = COMMON_USER_PPC64,
128, 128, .icache_bsize = 128,
__setup_cpu_power4, .dcache_bsize = 128,
COMMON_PPC64_FW .cpu_setup = __setup_cpu_power4,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* Power4+ */ { /* Power4+ */
0xffff0000, 0x00380000, "POWER4+ (gq)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00380000,
.cpu_name = "POWER4+ (gq)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA, CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64, .cpu_user_features = COMMON_USER_PPC64,
128, 128, .icache_bsize = 128,
__setup_cpu_power4, .dcache_bsize = 128,
COMMON_PPC64_FW .cpu_setup = __setup_cpu_power4,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* PPC970 */ { /* PPC970 */
0xffff0000, 0x00390000, "PPC970", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00390000,
.cpu_name = "PPC970",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP, .cpu_user_features = COMMON_USER_PPC64 |
128, 128, PPC_FEATURE_HAS_ALTIVEC_COMP,
__setup_cpu_ppc970, .icache_bsize = 128,
COMMON_PPC64_FW .dcache_bsize = 128,
.cpu_setup = __setup_cpu_ppc970,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* PPC970FX */ { /* PPC970FX */
0xffff0000, 0x003c0000, "PPC970FX", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x003c0000,
.cpu_name = "PPC970FX",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP, .cpu_user_features = COMMON_USER_PPC64 |
128, 128, PPC_FEATURE_HAS_ALTIVEC_COMP,
__setup_cpu_ppc970, .icache_bsize = 128,
COMMON_PPC64_FW .dcache_bsize = 128,
.cpu_setup = __setup_cpu_ppc970,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* Power5 */ { /* Power5 */
0xffff0000, 0x003a0000, "POWER5 (gr)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x003a0000,
.cpu_name = "POWER5 (gr)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
CPU_FTR_MMCRA_SIHV, CPU_FTR_MMCRA_SIHV,
COMMON_USER_PPC64, .cpu_user_features = COMMON_USER_PPC64,
128, 128, .icache_bsize = 128,
__setup_cpu_power4, .dcache_bsize = 128,
COMMON_PPC64_FW .cpu_setup = __setup_cpu_power4,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* Power5 */ { /* Power5 */
0xffff0000, 0x003b0000, "POWER5 (gs)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x003b0000,
.cpu_name = "POWER5 (gs)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
CPU_FTR_MMCRA_SIHV, CPU_FTR_MMCRA_SIHV,
COMMON_USER_PPC64, .cpu_user_features = COMMON_USER_PPC64,
128, 128, .icache_bsize = 128,
__setup_cpu_power4, .dcache_bsize = 128,
COMMON_PPC64_FW .cpu_setup = __setup_cpu_power4,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* BE DD1.x */ { /* BE DD1.x */
0xffff0000, 0x00700000, "Broadband Engine", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00700000,
.cpu_name = "Broadband Engine",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_SMT, CPU_FTR_SMT,
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP, .cpu_user_features = COMMON_USER_PPC64 |
128, 128, PPC_FEATURE_HAS_ALTIVEC_COMP,
__setup_cpu_be, .icache_bsize = 128,
COMMON_PPC64_FW .dcache_bsize = 128,
.cpu_setup = __setup_cpu_be,
.firmware_features = COMMON_PPC64_FW,
}, },
{ /* default match */ { /* default match */
0x00000000, 0x00000000, "POWER4 (compatible)", .pvr_mask = 0x00000000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00000000,
.cpu_name = "POWER4 (compatible)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2, CPU_FTR_PPCAS_ARCH_V2,
COMMON_USER_PPC64, .cpu_user_features = COMMON_USER_PPC64,
128, 128, .icache_bsize = 128,
__setup_cpu_power4, .dcache_bsize = 128,
COMMON_PPC64_FW .cpu_setup = __setup_cpu_power4,
.firmware_features = COMMON_PPC64_FW,
} }
}; };
......
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