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linux-davinci-2.6.23
Commit 1ffea473 authored by Tony Lindgren's avatar Tony Lindgren
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ARM: OMAP: First version of common DMA support for omap1 and omap2 

This patch modifies omap dma.c to add support for 24xx.
Functionality should be the same as earlier.
parent 61ebdc9b
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Showing with 768 additions and 365 deletions
arch/arm/plat-omap/dma.c
View file @ 1ffea473
...@@ -6,6 +6,8 @@ ...@@ -6,6 +6,8 @@
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
* Graphics DMA and LCD DMA graphics tranformations * Graphics DMA and LCD DMA graphics tranformations
* by Imre Deak <imre.deak@nokia.com> * by Imre Deak <imre.deak@nokia.com>
* OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
* Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
* *
* Support functions for the OMAP internal DMA channels. * Support functions for the OMAP internal DMA channels.
...@@ -31,8 +33,15 @@ ...@@ -31,8 +33,15 @@
#include <asm/arch/tc.h> #include <asm/arch/tc.h>
#define OMAP_DMA_ACTIVE 0x01 #define DEBUG_PRINTS
#undef DEBUG_PRINTS
#ifdef DEBUG_PRINTS
#define debug_printk(x) printk x
#else
#define debug_printk(x)
#endif
#define OMAP_DMA_ACTIVE 0x01
#define OMAP_DMA_CCR_EN (1 << 7) #define OMAP_DMA_CCR_EN (1 << 7)
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
...@@ -55,7 +64,7 @@ static int dma_chan_count; ...@@ -55,7 +64,7 @@ static int dma_chan_count;
static spinlock_t dma_chan_lock; static spinlock_t dma_chan_lock;
static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT]; static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = { const static u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
...@@ -63,6 +72,20 @@ const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = { ...@@ -63,6 +72,20 @@ const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
}; };
#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
__FUNCTION__);
#ifdef CONFIG_ARCH_OMAP15XX
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
int omap_dma_in_1510_mode(void)
{
return enable_1510_mode;
}
#else
#define omap_dma_in_1510_mode() 0
#endif
#ifdef CONFIG_ARCH_OMAP1
static inline int get_gdma_dev(int req) static inline int get_gdma_dev(int req)
{ {
u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
...@@ -82,6 +105,9 @@ static inline void set_gdma_dev(int req, int dev) ...@@ -82,6 +105,9 @@ static inline void set_gdma_dev(int req, int dev)
l |= (dev - 1) << shift; l |= (dev - 1) << shift;
omap_writel(l, reg); omap_writel(l, reg);
} }
#else
#define set_gdma_dev(req, dev) do {} while (0)
#endif
static void clear_lch_regs(int lch) static void clear_lch_regs(int lch)
{ {
...@@ -124,36 +150,59 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, ...@@ -124,36 +150,59 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
int frame_count, int sync_mode, int frame_count, int sync_mode,
int dma_trigger, int src_or_dst_synch) int dma_trigger, int src_or_dst_synch)
{ {
u16 w; OMAP_DMA_CSDP_REG(lch) &= ~0x03;
OMAP_DMA_CSDP_REG(lch) |= data_type;
w = omap_readw(OMAP_DMA_CSDP(lch)); if (cpu_class_is_omap1()) {
w &= ~0x03; OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
w |= data_type; if (sync_mode == OMAP_DMA_SYNC_FRAME)
omap_writew(w, OMAP_DMA_CSDP(lch)); OMAP_DMA_CCR_REG(lch) |= 1 << 5;
OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
if (sync_mode == OMAP_DMA_SYNC_BLOCK)
OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
}
if (cpu_is_omap24xx() && dma_trigger) {
u32 val = OMAP_DMA_CCR_REG(lch);
if (dma_trigger > 63)
val |= 1 << 20;
if (dma_trigger > 31)
val |= 1 << 19;
w = omap_readw(OMAP_DMA_CCR(lch)); val |= (dma_trigger & 0x1f);
w &= ~(1 << 5);
if (sync_mode == OMAP_DMA_SYNC_FRAME)
w |= 1 << 5;
omap_writew(w, OMAP_DMA_CCR(lch));
w = omap_readw(OMAP_DMA_CCR2(lch)); if (sync_mode & OMAP_DMA_SYNC_FRAME)
w &= ~(1 << 2); val |= 1 << 5;
if (sync_mode == OMAP_DMA_SYNC_BLOCK)
w |= 1 << 2;
omap_writew(w, OMAP_DMA_CCR2(lch));
omap_writew(elem_count, OMAP_DMA_CEN(lch)); if (sync_mode & OMAP_DMA_SYNC_BLOCK)
omap_writew(frame_count, OMAP_DMA_CFN(lch)); val |= 1 << 18;
if (src_or_dst_synch)
val |= 1 << 24; /* source synch */
else
val &= ~(1 << 24); /* dest synch */
OMAP_DMA_CCR_REG(lch) = val;
}
OMAP_DMA_CEN_REG(lch) = elem_count;
OMAP_DMA_CFN_REG(lch) = frame_count;
} }
void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
{ {
u16 w; u16 w;
BUG_ON(omap_dma_in_1510_mode()); BUG_ON(omap_dma_in_1510_mode());
w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03; if (cpu_is_omap24xx()) {
REVISIT_24XX();
return;
}
w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
switch (mode) { switch (mode) {
case OMAP_DMA_CONSTANT_FILL: case OMAP_DMA_CONSTANT_FILL:
w |= 0x01; w |= 0x01;
...@@ -166,63 +215,84 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) ...@@ -166,63 +215,84 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
default: default:
BUG(); BUG();
} }
omap_writew(w, OMAP_DMA_CCR2(lch)); OMAP1_DMA_CCR2_REG(lch) = w;
w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f; w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
/* Default is channel type 2D */ /* Default is channel type 2D */
if (mode) { if (mode) {
omap_writew((u16)color, OMAP_DMA_COLOR_L(lch)); OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch)); OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
w |= 1; /* Channel type G */ w |= 1; /* Channel type G */
} }
omap_writew(w, OMAP_DMA_LCH_CTRL(lch)); OMAP1_DMA_LCH_CTRL_REG(lch) = w;
} }
/* Note that src_port is only for omap1 */
void omap_set_dma_src_params(int lch, int src_port, int src_amode, void omap_set_dma_src_params(int lch, int src_port, int src_amode,
unsigned long src_start, unsigned long src_start,
int src_ei, int src_fi) int src_ei, int src_fi)
{ {
u16 w; if (cpu_class_is_omap1()) {
OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
}
OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
w = omap_readw(OMAP_DMA_CSDP(lch)); if (cpu_class_is_omap1()) {
w &= ~(0x1f << 2); OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
w |= src_port << 2; OMAP1_DMA_CSSA_L_REG(lch) = src_start;
omap_writew(w, OMAP_DMA_CSDP(lch)); }
w = omap_readw(OMAP_DMA_CCR(lch)); if (cpu_is_omap24xx())
w &= ~(0x03 << 12); OMAP2_DMA_CSSA_REG(lch) = src_start;
w |= src_amode << 12;
omap_writew(w, OMAP_DMA_CCR(lch)); OMAP_DMA_CSEI_REG(lch) = src_ei;
OMAP_DMA_CSFI_REG(lch) = src_fi;
}
omap_writew(src_start >> 16, OMAP_DMA_CSSA_U(lch)); void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
omap_writew(src_start, OMAP_DMA_CSSA_L(lch)); {
omap_set_dma_transfer_params(lch, params->data_type,
params->elem_count, params->frame_count,
params->sync_mode, params->trigger,
params->src_or_dst_synch);
omap_set_dma_src_params(lch, params->src_port,
params->src_amode, params->src_start,
params->src_ei, params->src_fi);
omap_set_dma_dest_params(lch, params->dst_port,
params->dst_amode, params->dst_start,
params->dst_ei, params->dst_fi);
} }
void omap_set_dma_src_index(int lch, int eidx, int fidx) void omap_set_dma_src_index(int lch, int eidx, int fidx)
{ {
omap_writew(eidx, OMAP_DMA_CSEI(lch)); if (cpu_is_omap24xx()) {
omap_writew(fidx, OMAP_DMA_CSFI(lch)); REVISIT_24XX();
return;
}
OMAP_DMA_CSEI_REG(lch) = eidx;
OMAP_DMA_CSFI_REG(lch) = fidx;
} }
void omap_set_dma_src_data_pack(int lch, int enable) void omap_set_dma_src_data_pack(int lch, int enable)
{ {
u16 w; OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
if (enable)
w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 6); OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
w |= enable ? (1 << 6) : 0;
omap_writew(w, OMAP_DMA_CSDP(lch));
} }
void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{ {
u16 w; OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 7);
switch (burst_mode) { switch (burst_mode) {
case OMAP_DMA_DATA_BURST_DIS: case OMAP_DMA_DATA_BURST_DIS:
break; break;
case OMAP_DMA_DATA_BURST_4: case OMAP_DMA_DATA_BURST_4:
w |= (0x02 << 7); OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7);
break; break;
case OMAP_DMA_DATA_BURST_8: case OMAP_DMA_DATA_BURST_8:
/* not supported by current hardware /* not supported by current hardware
...@@ -232,111 +302,280 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) ...@@ -232,111 +302,280 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
default: default:
BUG(); BUG();
} }
omap_writew(w, OMAP_DMA_CSDP(lch));
} }
/* Note that dest_port is only for OMAP1 */
void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
unsigned long dest_start, unsigned long dest_start,
int dst_ei, int dst_fi) int dst_ei, int dst_fi)
{ {
u16 w; if (cpu_class_is_omap1()) {
OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
}
w = omap_readw(OMAP_DMA_CSDP(lch)); OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
w &= ~(0x1f << 9); OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
w |= dest_port << 9;
omap_writew(w, OMAP_DMA_CSDP(lch));
w = omap_readw(OMAP_DMA_CCR(lch)); if (cpu_class_is_omap1()) {
w &= ~(0x03 << 14); OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
w |= dest_amode << 14; OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
omap_writew(w, OMAP_DMA_CCR(lch)); }
if (cpu_is_omap24xx())
OMAP2_DMA_CDSA_REG(lch) = dest_start;
omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U(lch)); OMAP_DMA_CDEI_REG(lch) = dst_ei;
omap_writew(dest_start, OMAP_DMA_CDSA_L(lch)); OMAP_DMA_CDFI_REG(lch) = dst_fi;
} }
void omap_set_dma_dest_index(int lch, int eidx, int fidx) void omap_set_dma_dest_index(int lch, int eidx, int fidx)
{ {
omap_writew(eidx, OMAP_DMA_CDEI(lch)); if (cpu_is_omap24xx()) {
omap_writew(fidx, OMAP_DMA_CDFI(lch)); REVISIT_24XX();
return;
}
OMAP_DMA_CDEI_REG(lch) = eidx;
OMAP_DMA_CDFI_REG(lch) = fidx;
} }
void omap_set_dma_dest_data_pack(int lch, int enable) void omap_set_dma_dest_data_pack(int lch, int enable)
{ {
u16 w; OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
if (enable)
w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 13); OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
w |= enable ? (1 << 13) : 0;
omap_writew(w, OMAP_DMA_CSDP(lch));
} }
void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{ {
u16 w; OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 14);
switch (burst_mode) { switch (burst_mode) {
case OMAP_DMA_DATA_BURST_DIS: case OMAP_DMA_DATA_BURST_DIS:
break; break;
case OMAP_DMA_DATA_BURST_4: case OMAP_DMA_DATA_BURST_4:
w |= (0x02 << 14); OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14);
break; break;
case OMAP_DMA_DATA_BURST_8: case OMAP_DMA_DATA_BURST_8:
w |= (0x03 << 14); OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14);
break; break;
default: default:
printk(KERN_ERR "Invalid DMA burst mode\n"); printk(KERN_ERR "Invalid DMA burst mode\n");
BUG(); BUG();
return; return;
} }
omap_writew(w, OMAP_DMA_CSDP(lch));
} }
static inline void init_intr(int lch) static inline void omap_enable_channel_irq(int lch)
{ {
u16 w; u32 status;
/* Read CSR to make sure it's cleared. */ /* Read CSR to make sure it's cleared. */
w = omap_readw(OMAP_DMA_CSR(lch)); status = OMAP_DMA_CSR_REG(lch);
/* Enable some nice interrupts. */ /* Enable some nice interrupts. */
omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR(lch)); OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
dma_chan[lch].flags |= OMAP_DMA_ACTIVE; dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
} }
static inline void enable_lnk(int lch) static void omap_disable_channel_irq(int lch)
{ {
u16 w; if (cpu_is_omap24xx())
OMAP_DMA_CICR_REG(lch) = 0;
}
/* Clear the STOP_LNK bits */ void omap_enable_dma_irq(int lch, u16 bits)
w = omap_readw(OMAP_DMA_CLNK_CTRL(lch)); {
w &= ~(1 << 14); dma_chan[lch].enabled_irqs |= bits;
omap_writew(w, OMAP_DMA_CLNK_CTRL(lch)); }
/* And set the ENABLE_LNK bits */ void omap_disable_dma_irq(int lch, u16 bits)
{
dma_chan[lch].enabled_irqs &= ~bits;
}
static inline void enable_lnk(int lch)
{
if (cpu_class_is_omap1())
OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
/* Set the ENABLE_LNK bits */
if (dma_chan[lch].next_lch != -1) if (dma_chan[lch].next_lch != -1)
omap_writew(dma_chan[lch].next_lch | (1 << 15), OMAP_DMA_CLNK_CTRL_REG(lch) =
OMAP_DMA_CLNK_CTRL(lch)); dma_chan[lch].next_lch | (1 << 15);
} }
static inline void disable_lnk(int lch) static inline void disable_lnk(int lch)
{ {
u16 w;
/* Disable interrupts */ /* Disable interrupts */
omap_writew(0, OMAP_DMA_CICR(lch)); if (cpu_class_is_omap1()) {
OMAP_DMA_CICR_REG(lch) = 0;
/* Set the STOP_LNK bit */
OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
}
/* Set the STOP_LNK bit */ if (cpu_is_omap24xx()) {
w = omap_readw(OMAP_DMA_CLNK_CTRL(lch)); omap_disable_channel_irq(lch);
w |= (1 << 14); /* Clear the ENABLE_LNK bit */
w = omap_writew(w, OMAP_DMA_CLNK_CTRL(lch)); OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
}
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
} }
void omap_start_dma(int lch) static inline void omap2_enable_irq_lch(int lch)
{ {
u16 w; u32 val;
if (!cpu_is_omap24xx())
return;
val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
val |= 1 << lch;
omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
}
int omap_request_dma(int dev_id, const char *dev_name,
void (* callback)(int lch, u16 ch_status, void *data),
void *data, int *dma_ch_out)
{
int ch, free_ch = -1;
unsigned long flags;
struct omap_dma_lch *chan;
spin_lock_irqsave(&dma_chan_lock, flags);
for (ch = 0; ch < dma_chan_count; ch++) {
if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
free_ch = ch;
if (dev_id == 0)
break;
}
}
if (free_ch == -1) {
spin_unlock_irqrestore(&dma_chan_lock, flags);
return -EBUSY;
}
chan = dma_chan + free_ch;
chan->dev_id = dev_id;
if (cpu_class_is_omap1())
clear_lch_regs(free_ch);
if (cpu_is_omap24xx())
omap_clear_dma(free_ch);
spin_unlock_irqrestore(&dma_chan_lock, flags);
chan->dev_name = dev_name;
chan->callback = callback;
chan->data = data;
chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
OMAP_DMA_BLOCK_IRQ;
if (cpu_is_omap16xx()) {
/* If the sync device is set, configure it dynamically. */
if (dev_id != 0) {
set_gdma_dev(free_ch + 1, dev_id);
dev_id = free_ch + 1;
}
/* Disable the 1510 compatibility mode and set the sync device
* id. */
OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
} else if (cpu_is_omap730() || cpu_is_omap15xx()) {
OMAP_DMA_CCR_REG(free_ch) = dev_id;
}
if (cpu_is_omap24xx()) {
omap2_enable_irq_lch(free_ch);
omap_enable_channel_irq(free_ch);
/* Clear the CSR register and IRQ status register */
OMAP_DMA_CSR_REG(free_ch) = 0x0;
omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
}
*dma_ch_out = free_ch;
return 0;
}
void omap_free_dma(int lch)
{
unsigned long flags;
spin_lock_irqsave(&dma_chan_lock, flags);
if (dma_chan[lch].dev_id == -1) {
printk("omap_dma: trying to free nonallocated DMA channel %d\n",
lch);
spin_unlock_irqrestore(&dma_chan_lock, flags);
return;
}
dma_chan[lch].dev_id = -1;
dma_chan[lch].next_lch = -1;
dma_chan[lch].callback = NULL;
spin_unlock_irqrestore(&dma_chan_lock, flags);
if (cpu_class_is_omap1()) {
/* Disable all DMA interrupts for the channel. */
OMAP_DMA_CICR_REG(lch) = 0;
/* Make sure the DMA transfer is stopped. */
OMAP_DMA_CCR_REG(lch) = 0;
}
if (cpu_is_omap24xx()) {
u32 val;
/* Disable interrupts */
val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
val &= ~(1 << lch);
omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
/* Clear the CSR register and IRQ status register */
OMAP_DMA_CSR_REG(lch) = 0x0;
val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
val |= 1 << lch;
omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
/* Disable all DMA interrupts for the channel. */
OMAP_DMA_CICR_REG(lch) = 0;
/* Make sure the DMA transfer is stopped. */
OMAP_DMA_CCR_REG(lch) = 0;
omap_clear_dma(lch);
}
}
/*
* Clears any DMA state so the DMA engine is ready to restart with new buffers
* through omap_start_dma(). Any buffers in flight are discarded.
*/
void omap_clear_dma(int lch)
{
unsigned long flags;
local_irq_save(flags);
if (cpu_class_is_omap1()) {
int status;
OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
/* Clear pending interrupts */
status = OMAP_DMA_CSR_REG(lch);
}
if (cpu_is_omap24xx()) {
int i;
u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
for (i = 0; i < 0x44; i += 4)
omap_writel(0, lch_base + i);
}
local_irq_restore(flags);
}
void omap_start_dma(int lch)
{
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
int next_lch, cur_lch; int next_lch, cur_lch;
char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
...@@ -350,31 +589,37 @@ void omap_start_dma(int lch) ...@@ -350,31 +589,37 @@ void omap_start_dma(int lch)
do { do {
next_lch = dma_chan[cur_lch].next_lch; next_lch = dma_chan[cur_lch].next_lch;
/* The loop case: we've been here already */ /* The loop case: we've been here already */
if (dma_chan_link_map[cur_lch]) if (dma_chan_link_map[cur_lch])
break; break;
/* Mark the current channel */ /* Mark the current channel */
dma_chan_link_map[cur_lch] = 1; dma_chan_link_map[cur_lch] = 1;
enable_lnk(cur_lch); enable_lnk(cur_lch);
init_intr(cur_lch); omap_enable_channel_irq(cur_lch);
cur_lch = next_lch; cur_lch = next_lch;
} while (next_lch != -1); } while (next_lch != -1);
} else if (cpu_is_omap24xx()) {
/* Errata: Need to write lch even if not using chaining */
OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
}
omap_enable_channel_irq(lch);
/* Errata: On ES2.0 BUFFERING disable must be set.
* This will always fail on ES1.0 */
if (cpu_is_omap24xx()) {
OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
} }
init_intr(lch); OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
w = omap_readw(OMAP_DMA_CCR(lch));
w |= OMAP_DMA_CCR_EN;
omap_writew(w, OMAP_DMA_CCR(lch));
dma_chan[lch].flags |= OMAP_DMA_ACTIVE; dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
} }
void omap_stop_dma(int lch) void omap_stop_dma(int lch)
{ {
u16 w;
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
int next_lch, cur_lch = lch; int next_lch, cur_lch = lch;
char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
...@@ -395,146 +640,83 @@ void omap_stop_dma(int lch) ...@@ -395,146 +640,83 @@ void omap_stop_dma(int lch)
return; return;
} }
/* Disable all interrupts on the channel */ /* Disable all interrupts on the channel */
omap_writew(0, OMAP_DMA_CICR(lch)); if (cpu_class_is_omap1())
OMAP_DMA_CICR_REG(lch) = 0;
w = omap_readw(OMAP_DMA_CCR(lch)); OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
w &= ~OMAP_DMA_CCR_EN;
omap_writew(w, OMAP_DMA_CCR(lch));
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
} }
void omap_enable_dma_irq(int lch, u16 bits) /*
* Returns current physical source address for the given DMA channel.
* If the channel is running the caller must disable interrupts prior calling
* this function and process the returned value before re-enabling interrupt to
* prevent races with the interrupt handler. Note that in continuous mode there
* is a chance for CSSA_L register overflow inbetween the two reads resulting
* in incorrect return value.
*/
dma_addr_t omap_get_dma_src_pos(int lch)
{ {
dma_chan[lch].enabled_irqs |= bits; dma_addr_t offset;
}
void omap_disable_dma_irq(int lch, u16 bits) if (cpu_class_is_omap1())
{ offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
dma_chan[lch].enabled_irqs &= ~bits; (OMAP1_DMA_CSSA_U_REG(lch) << 16));
}
static int dma_handle_ch(int ch) if (cpu_is_omap24xx())
{ offset = OMAP_DMA_CSAC_REG(lch);
u16 csr;
if (enable_1510_mode && ch >= 6) { return offset;
csr = dma_chan[ch].saved_csr;
dma_chan[ch].saved_csr = 0;
} else
csr = omap_readw(OMAP_DMA_CSR(ch));
if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
dma_chan[ch + 6].saved_csr = csr >> 7;
csr &= 0x7f;
}
if ((csr & 0x3f) == 0)
return 0;
if (unlikely(dma_chan[ch].dev_id == -1)) {
printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n",
ch, csr);
return 0;
}
if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
printk(KERN_WARNING "DMA timeout with device %d\n", dma_chan[ch].dev_id);
if (unlikely(csr & OMAP_DMA_DROP_IRQ))
printk(KERN_WARNING "DMA synchronization event drop occurred with device %d\n",
dma_chan[ch].dev_id);
if (likely(csr & OMAP_DMA_BLOCK_IRQ))
dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
return 1;
} }
static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) /*
* Returns current physical destination address for the given DMA channel.
* If the channel is running the caller must disable interrupts prior calling
* this function and process the returned value before re-enabling interrupt to
* prevent races with the interrupt handler. Note that in continuous mode there
* is a chance for CDSA_L register overflow inbetween the two reads resulting
* in incorrect return value.
*/
dma_addr_t omap_get_dma_dst_pos(int lch)
{ {
int ch = ((int) dev_id) - 1; dma_addr_t offset;
int handled = 0;
for (;;) { if (cpu_class_is_omap1())
int handled_now = 0; offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
(OMAP1_DMA_CDSA_U_REG(lch) << 16));
handled_now += dma_handle_ch(ch); if (cpu_is_omap24xx())
if (enable_1510_mode && dma_chan[ch + 6].saved_csr) offset = OMAP2_DMA_CDSA_REG(lch);
handled_now += dma_handle_ch(ch + 6);
if (!handled_now)
break;
handled += handled_now;
}
return handled ? IRQ_HANDLED : IRQ_NONE; return offset;
} }
int omap_request_dma(int dev_id, const char *dev_name, /*
void (* callback)(int lch, u16 ch_status, void *data), * Returns current source transfer counting for the given DMA channel.
void *data, int *dma_ch_out) * Can be used to monitor the progress of a transfer inside a block.
* It must be called with disabled interrupts.
*/
int omap_get_dma_src_addr_counter(int lch)
{ {
int ch, free_ch = -1; return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
unsigned long flags;
struct omap_dma_lch *chan;
spin_lock_irqsave(&dma_chan_lock, flags);
for (ch = 0; ch < dma_chan_count; ch++) {
if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
free_ch = ch;
if (dev_id == 0)
break;
}
}
if (free_ch == -1) {
spin_unlock_irqrestore(&dma_chan_lock, flags);
return -EBUSY;
}
chan = dma_chan + free_ch;
chan->dev_id = dev_id;
clear_lch_regs(free_ch);
spin_unlock_irqrestore(&dma_chan_lock, flags);
chan->dev_id = dev_id;
chan->dev_name = dev_name;
chan->callback = callback;
chan->data = data;
chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
if (cpu_is_omap16xx()) {
/* If the sync device is set, configure it dynamically. */
if (dev_id != 0) {
set_gdma_dev(free_ch + 1, dev_id);
dev_id = free_ch + 1;
}
/* Disable the 1510 compatibility mode and set the sync device
* id. */
omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR(free_ch));
} else {
omap_writew(dev_id, OMAP_DMA_CCR(free_ch));
}
*dma_ch_out = free_ch;
return 0;
} }
void omap_free_dma(int ch) int omap_dma_running(void)
{ {
unsigned long flags; int lch;
spin_lock_irqsave(&dma_chan_lock, flags); /* Check if LCD DMA is running */
if (dma_chan[ch].dev_id == -1) { if (cpu_is_omap16xx())
printk("omap_dma: trying to free nonallocated DMA channel %d\n", ch); if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
spin_unlock_irqrestore(&dma_chan_lock, flags); return 1;
return;
}
dma_chan[ch].dev_id = -1;
spin_unlock_irqrestore(&dma_chan_lock, flags);
/* Disable all DMA interrupts for the channel. */ for (lch = 0; lch < dma_chan_count; lch++)
omap_writew(0, OMAP_DMA_CICR(ch)); if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
/* Make sure the DMA transfer is stopped. */ return 1;
omap_writew(0, OMAP_DMA_CCR(ch));
}
int omap_dma_in_1510_mode(void) return 0;
{
return enable_1510_mode;
} }
/* /*
...@@ -552,7 +734,8 @@ void omap_dma_link_lch (int lch_head, int lch_queue) ...@@ -552,7 +734,8 @@ void omap_dma_link_lch (int lch_head, int lch_queue)
if ((dma_chan[lch_head].dev_id == -1) || if ((dma_chan[lch_head].dev_id == -1) ||
(dma_chan[lch_queue].dev_id == -1)) { (dma_chan[lch_queue].dev_id == -1)) {
printk(KERN_ERR "omap_dma: trying to link non requested channels\n"); printk(KERN_ERR "omap_dma: trying to link "
"non requested channels\n");
dump_stack(); dump_stack();
} }
...@@ -572,20 +755,145 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue) ...@@ -572,20 +755,145 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
if (dma_chan[lch_head].next_lch != lch_queue || if (dma_chan[lch_head].next_lch != lch_queue ||
dma_chan[lch_head].next_lch == -1) { dma_chan[lch_head].next_lch == -1) {
printk(KERN_ERR "omap_dma: trying to unlink non linked channels\n"); printk(KERN_ERR "omap_dma: trying to unlink "
"non linked channels\n");
dump_stack(); dump_stack();
} }
if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
(dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
printk(KERN_ERR "omap_dma: You need to stop the DMA channels before unlinking\n"); printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
"before unlinking\n");
dump_stack(); dump_stack();
} }
dma_chan[lch_head].next_lch = -1; dma_chan[lch_head].next_lch = -1;
} }
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_ARCH_OMAP1
static int omap1_dma_handle_ch(int ch)
{
u16 csr;
if (enable_1510_mode && ch >= 6) {
csr = dma_chan[ch].saved_csr;
dma_chan[ch].saved_csr = 0;
} else
csr = OMAP_DMA_CSR_REG(ch);
if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
dma_chan[ch + 6].saved_csr = csr >> 7;
csr &= 0x7f;
}
if ((csr & 0x3f) == 0)
return 0;
if (unlikely(dma_chan[ch].dev_id == -1)) {
printk(KERN_WARNING "Spurious interrupt from DMA channel "
"%d (CSR %04x)\n", ch, csr);
return 0;
}
if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
printk(KERN_WARNING "DMA timeout with device %d\n",
dma_chan[ch].dev_id);
if (unlikely(csr & OMAP_DMA_DROP_IRQ))
printk(KERN_WARNING "DMA synchronization event drop occurred "
"with device %d\n", dma_chan[ch].dev_id);
if (likely(csr & OMAP_DMA_BLOCK_IRQ))
dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
return 1;
}
static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id,
struct pt_regs *regs)
{
int ch = ((int) dev_id) - 1;
int handled = 0;
for (;;) {
int handled_now = 0;
handled_now += omap1_dma_handle_ch(ch);
if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
handled_now += omap1_dma_handle_ch(ch + 6);
if (!handled_now)
break;
handled += handled_now;
}
return handled ? IRQ_HANDLED : IRQ_NONE;
}
#else
#define omap1_dma_irq_handler NULL
#endif
#ifdef CONFIG_ARCH_OMAP2
static int omap2_dma_handle_ch(int ch)
{
u32 val = OMAP_DMA_CSR_REG(ch);
if (!val)
return 0;
if (unlikely(dma_chan[ch].dev_id == -1))
return 0;
if (unlikely(val & OMAP_DMA_TOUT_IRQ))
printk(KERN_INFO "DMA timeout with device %d\n",
dma_chan[ch].dev_id);
if (unlikely(val & OMAP_DMA_DROP_IRQ))
printk(KERN_INFO
"DMA synchronization event drop occurred with device "
"%d\n", dma_chan[ch].dev_id);
OMAP_DMA_CSR_REG(ch) = 0x20;
val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
/* ch in this function is from 0-31 while in register it is 1-32 */
val = 1 << (ch);
omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
if (likely(dma_chan[ch].callback != NULL)){
val = OMAP_DMA_CSR_REG(ch);
dma_chan[ch].callback(ch, val, dma_chan[ch].data);
}
return 0;
}
/* STATUS register count is from 1-32 while our is 0-31 */
static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id,
struct pt_regs *regs)
{
u32 val;
int i;
val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
int active = val & (1 << (i - 1));
if (active)
omap2_dma_handle_ch(i - 1);
}
return IRQ_HANDLED;
}
static struct irqaction omap24xx_dma_irq = {
.name = "DMA",
.handler = omap2_dma_irq_handler,
.flags = SA_INTERRUPT
};
#else
static struct irqaction omap24xx_dma_irq;
#endif
/*----------------------------------------------------------------------------*/
static struct lcd_dma_info { static struct lcd_dma_info {
spinlock_t lock; spinlock_t lock;
...@@ -797,7 +1105,7 @@ static void set_b1_regs(void) ...@@ -797,7 +1105,7 @@ static void set_b1_regs(void)
/* Always set the source port as SDRAM for now*/ /* Always set the source port as SDRAM for now*/
w &= ~(0x03 << 6); w &= ~(0x03 << 6);
if (lcd_dma.callback != NULL) if (lcd_dma.callback != NULL)
w |= 1 << 1; /* Block interrupt enable */ w |= 1 << 1; /* Block interrupt enable */
else else
w &= ~(1 << 1); w &= ~(1 << 1);
omap_writew(w, OMAP1610_DMA_LCD_CTRL); omap_writew(w, OMAP1610_DMA_LCD_CTRL);
...@@ -816,7 +1124,8 @@ static void set_b1_regs(void) ...@@ -816,7 +1124,8 @@ static void set_b1_regs(void)
omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
} }
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id,
struct pt_regs *regs)
{ {
u16 w; u16 w;
...@@ -872,7 +1181,8 @@ void omap_free_lcd_dma(void) ...@@ -872,7 +1181,8 @@ void omap_free_lcd_dma(void)
return; return;
} }
if (!enable_1510_mode) if (!enable_1510_mode)
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR); omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
OMAP1610_DMA_LCD_CCR);
lcd_dma.reserved = 0; lcd_dma.reserved = 0;
spin_unlock(&lcd_dma.lock); spin_unlock(&lcd_dma.lock);
} }
...@@ -941,78 +1251,7 @@ void omap_stop_lcd_dma(void) ...@@ -941,78 +1251,7 @@ void omap_stop_lcd_dma(void)
omap_writew(w, OMAP1610_DMA_LCD_CTRL); omap_writew(w, OMAP1610_DMA_LCD_CTRL);
} }
/* /*----------------------------------------------------------------------------*/
* Clears any DMA state so the DMA engine is ready to restart with new buffers
* through omap_start_dma(). Any buffers in flight are discarded.
*/
void omap_clear_dma(int lch)
{
unsigned long flags;
int status;
local_irq_save(flags);
omap_writew(omap_readw(OMAP_DMA_CCR(lch)) & ~OMAP_DMA_CCR_EN,
OMAP_DMA_CCR(lch));
status = omap_readw(OMAP_DMA_CSR(lch)); /* clear pending interrupts */
local_irq_restore(flags);
}
/*
* Returns current physical source address for the given DMA channel.
* If the channel is running the caller must disable interrupts prior calling
* this function and process the returned value before re-enabling interrupt to
* prevent races with the interrupt handler. Note that in continuous mode there
* is a chance for CSSA_L register overflow inbetween the two reads resulting
* in incorrect return value.
*/
dma_addr_t omap_get_dma_src_pos(int lch)
{
return (dma_addr_t) (omap_readw(OMAP_DMA_CSSA_L(lch)) |
(omap_readw(OMAP_DMA_CSSA_U(lch)) << 16));
}
/*
* Returns current physical destination address for the given DMA channel.
* If the channel is running the caller must disable interrupts prior calling
* this function and process the returned value before re-enabling interrupt to
* prevent races with the interrupt handler. Note that in continuous mode there
* is a chance for CDSA_L register overflow inbetween the two reads resulting
* in incorrect return value.
*/
dma_addr_t omap_get_dma_dst_pos(int lch)
{
return (dma_addr_t) (omap_readw(OMAP_DMA_CDSA_L(lch)) |
(omap_readw(OMAP_DMA_CDSA_U(lch)) << 16));
}
/*
* Returns current source transfer counting for the given DMA channel.
* Can be used to monitor the progress of a transfer inside a block.
* It must be called with disabled interrupts.
*/
int omap_get_dma_src_addr_counter(int lch)
{
return (dma_addr_t) omap_readw(OMAP_DMA_CSAC(lch));
}
int omap_dma_running(void)
{
int lch;
/* Check if LCD DMA is running */
if (cpu_is_omap16xx())
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
return 1;
for (lch = 0; lch < dma_chan_count; lch++) {
u16 w;
w = omap_readw(OMAP_DMA_CCR(lch));
if (w & OMAP_DMA_CCR_EN)
return 1;
}
return 0;
}
static int __init omap_init_dma(void) static int __init omap_init_dma(void)
{ {
...@@ -1026,8 +1265,10 @@ static int __init omap_init_dma(void) ...@@ -1026,8 +1265,10 @@ static int __init omap_init_dma(void)
printk(KERN_INFO "OMAP DMA hardware version %d\n", printk(KERN_INFO "OMAP DMA hardware version %d\n",
omap_readw(OMAP_DMA_HW_ID)); omap_readw(OMAP_DMA_HW_ID));
printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
(omap_readw(OMAP_DMA_CAPS_0_U) << 16) | omap_readw(OMAP_DMA_CAPS_0_L), (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
(omap_readw(OMAP_DMA_CAPS_1_U) << 16) | omap_readw(OMAP_DMA_CAPS_1_L), omap_readw(OMAP_DMA_CAPS_0_L),
(omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
omap_readw(OMAP_DMA_CAPS_1_L),
omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3), omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
omap_readw(OMAP_DMA_CAPS_4)); omap_readw(OMAP_DMA_CAPS_4));
if (!enable_1510_mode) { if (!enable_1510_mode) {
...@@ -1040,6 +1281,11 @@ static int __init omap_init_dma(void) ...@@ -1040,6 +1281,11 @@ static int __init omap_init_dma(void)
dma_chan_count = 16; dma_chan_count = 16;
} else } else
dma_chan_count = 9; dma_chan_count = 9;
} else if (cpu_is_omap24xx()) {
u8 revision = omap_readb(OMAP_DMA4_REVISION);
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
revision >> 4, revision & 0xf);
dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
} else { } else {
dma_chan_count = 0; dma_chan_count = 0;
return 0; return 0;
...@@ -1050,46 +1296,57 @@ static int __init omap_init_dma(void) ...@@ -1050,46 +1296,57 @@ static int __init omap_init_dma(void)
spin_lock_init(&dma_chan_lock); spin_lock_init(&dma_chan_lock);
memset(&dma_chan, 0, sizeof(dma_chan)); memset(&dma_chan, 0, sizeof(dma_chan));
/* Disable and clear all DMA channels to avoid spurious IRQ */
for (ch = 0; ch < dma_chan_count; ch++) { for (ch = 0; ch < dma_chan_count; ch++) {
omap_clear_dma(ch); omap_clear_dma(ch);
}
for (ch = 0; ch < dma_chan_count; ch++) {
dma_chan[ch].dev_id = -1; dma_chan[ch].dev_id = -1;
dma_chan[ch].next_lch = -1; dma_chan[ch].next_lch = -1;
if (ch >= 6 && enable_1510_mode) if (ch >= 6 && enable_1510_mode)
continue; continue;
/* request_irq() doesn't like dev_id (ie. ch) being zero, if (cpu_class_is_omap1()) {
* so we have to kludge around this. */ /* request_irq() doesn't like dev_id (ie. ch) being
r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA", * zero, so we have to kludge around this. */
(void *) (ch + 1)); r = request_irq(omap1_dma_irq[ch],
omap1_dma_irq_handler, 0, "DMA",
(void *) (ch + 1));
if (r != 0) {
int i;
printk(KERN_ERR "unable to request IRQ %d "
"for DMA (error %d)\n",
omap1_dma_irq[ch], r);
for (i = 0; i < ch; i++)
free_irq(omap1_dma_irq[i],
(void *) (i + 1));
return r;
}
}
}
if (cpu_is_omap24xx())
setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
/* FIXME: Update LCD DMA to work on 24xx */
if (cpu_class_is_omap1()) {
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0) { if (r != 0) {
int i; int i;
printk(KERN_ERR "unable to request IRQ %d for DMA (error %d)\n", printk(KERN_ERR "unable to request IRQ for LCD DMA "
dma_irq[ch], r); "(error %d)\n", r);
for (i = 0; i < ch; i++) for (i = 0; i < dma_chan_count; i++)
free_irq(dma_irq[i], (void *) (i + 1)); free_irq(omap1_dma_irq[i], (void *) (i + 1));
return r; return r;
} }
} }
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, "LCD DMA", NULL);
if (r != 0) {
int i;
printk(KERN_ERR "unable to request IRQ for LCD DMA (error %d)\n", r);
for (i = 0; i < dma_chan_count; i++)
free_irq(dma_irq[i], (void *) (i + 1));
return r;
}
return 0; return 0;
} }
arch_initcall(omap_init_dma); arch_initcall(omap_init_dma);
EXPORT_SYMBOL(omap_get_dma_src_pos); EXPORT_SYMBOL(omap_get_dma_src_pos);
EXPORT_SYMBOL(omap_get_dma_dst_pos); EXPORT_SYMBOL(omap_get_dma_dst_pos);
EXPORT_SYMBOL(omap_get_dma_src_addr_counter); EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
...@@ -1115,6 +1372,8 @@ EXPORT_SYMBOL(omap_set_dma_dest_index); ...@@ -1115,6 +1372,8 @@ EXPORT_SYMBOL(omap_set_dma_dest_index);
EXPORT_SYMBOL(omap_set_dma_dest_data_pack); EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
EXPORT_SYMBOL(omap_set_dma_params);
EXPORT_SYMBOL(omap_dma_link_lch); EXPORT_SYMBOL(omap_dma_link_lch);
EXPORT_SYMBOL(omap_dma_unlink_lch); EXPORT_SYMBOL(omap_dma_unlink_lch);
......
include/asm-arm/arch-omap/dma.h
View file @ 1ffea473
...@@ -23,8 +23,107 @@ ...@@ -23,8 +23,107 @@
#define MAX_DMA_ADDRESS 0xffffffff #define MAX_DMA_ADDRESS 0xffffffff
/* Hardware registers for omap1 */
#define OMAP_DMA_BASE (0xfffed800)
#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
/* Hardware registers for omap2 */
#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000)
#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00)
#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78)
#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08)
#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c)
#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10)
#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14)
#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18)
#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c)
#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20)
#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24)
#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28)
#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64)
#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
#ifdef CONFIG_ARCH_OMAP1
#define OMAP_LOGICAL_DMA_CH_COUNT 17 #define OMAP_LOGICAL_DMA_CH_COUNT 17
/* Common channel specific registers for omap1 */
#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
#else
#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
/* Common channel specific registers for omap2 */
#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
#endif
/* Channel specific registers only on omap1 */
#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
/* Channel specific registers only on omap2 */
#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
/*----------------------------------------------------------------------------*/
/* DMA channels for omap1 */
#define OMAP_DMA_NO_DEVICE 0 #define OMAP_DMA_NO_DEVICE 0
#define OMAP_DMA_MCSI1_TX 1 #define OMAP_DMA_MCSI1_TX 1
#define OMAP_DMA_MCSI1_RX 2 #define OMAP_DMA_MCSI1_RX 2
...@@ -85,29 +184,72 @@ ...@@ -85,29 +184,72 @@
#define OMAP_DMA_MMC2_RX 55 #define OMAP_DMA_MMC2_RX 55
#define OMAP_DMA_CRYPTO_DES_OUT 56 #define OMAP_DMA_CRYPTO_DES_OUT 56
/* DMA channels for 24xx */
#define OMAP24XX_DMA_NO_DEVICE 0
#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
#define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */
#define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */
#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */
#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
#define OMAP_DMA_BASE (0xfffed800) #define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */
#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) #define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */
#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) #define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) #define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) #define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) #define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) #define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) #define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) #define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) #define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) #define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */
#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) #define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */
#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) #define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */
#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) #define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */
#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) #define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */
#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) #define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */
#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) #define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */
#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */
#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */
#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */
#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */
#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */
#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */
#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */
#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */
#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */
#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */
#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */
#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */
#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */
#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */
#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */
#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */
#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */
#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */
#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */
#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */
#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */
#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */
#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */
#define OMAP24XX_DMA_MS 63 /* SDMA_62 */
/*----------------------------------------------------------------------------*/
/* Hardware registers for LCD DMA */
#define OMAP1510_DMA_LCD_BASE (0xfffedb00) #define OMAP1510_DMA_LCD_BASE (0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
...@@ -116,7 +258,7 @@ ...@@ -116,7 +258,7 @@
#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
#define OMAP1610_DMA_LCD_BASE (0xfffee300) #define OMAP1610_DMA_LCD_BASE (0xfffee300)
#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) #define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
...@@ -134,30 +276,6 @@ ...@@ -134,30 +276,6 @@
#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
/* Every LCh has its own set of the registers below */
#define OMAP_DMA_CSDP(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
#define OMAP_DMA_CCR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
#define OMAP_DMA_CICR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
#define OMAP_DMA_CSR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
#define OMAP_DMA_CSSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
#define OMAP_DMA_CSSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
#define OMAP_DMA_CDSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
#define OMAP_DMA_CDSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
#define OMAP_DMA_CEN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
#define OMAP_DMA_CFN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
#define OMAP_DMA_CSFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
#define OMAP_DMA_CSEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
#define OMAP_DMA_CSAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
#define OMAP_DMA_CDAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
#define OMAP_DMA_CDEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
#define OMAP_DMA_CDFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
#define OMAP_DMA_COLOR_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
#define OMAP_DMA_COLOR_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
#define OMAP_DMA_CCR2(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
#define OMAP_DMA_CLNK_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
#define OMAP_DMA_LCH_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
#define OMAP_DMA_TOUT_IRQ (1 << 0) #define OMAP_DMA_TOUT_IRQ (1 << 0)
#define OMAP_DMA_DROP_IRQ (1 << 1) #define OMAP_DMA_DROP_IRQ (1 << 1)
#define OMAP_DMA_HALF_IRQ (1 << 2) #define OMAP_DMA_HALF_IRQ (1 << 2)
...@@ -194,6 +312,7 @@ enum { ...@@ -194,6 +312,7 @@ enum {
OMAP_LCD_DMA_B2_BOTTOM OMAP_LCD_DMA_B2_BOTTOM
}; };
/* REVISIT: Check if BURST_4 is really 1 (or 2) */
enum omap_dma_burst_mode { enum omap_dma_burst_mode {
OMAP_DMA_DATA_BURST_DIS = 0, OMAP_DMA_DATA_BURST_DIS = 0,
OMAP_DMA_DATA_BURST_4, OMAP_DMA_DATA_BURST_4,
...@@ -206,6 +325,31 @@ enum omap_dma_color_mode { ...@@ -206,6 +325,31 @@ enum omap_dma_color_mode {
OMAP_DMA_TRANSPARENT_COPY OMAP_DMA_TRANSPARENT_COPY
}; };
struct omap_dma_channel_params {
int data_type; /* data type 8,16,32 */
int elem_count; /* number of elements in a frame */
int frame_count; /* number of frames in a element */
int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
int src_amode; /* constant , post increment, indexed , double indexed */
int src_start; /* source address : physical */
int src_ei; /* source element index */
int src_fi; /* source frame index */
int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
int dst_amode; /* constant , post increment, indexed , double indexed */
int dst_start; /* source address : physical */
int dst_ei; /* source element index */
int dst_fi; /* source frame index */
int trigger; /* trigger attached if the channel is synchronized */
int sync_mode; /* sycn on element, frame , block or packet */
int src_or_dst_synch; /* source synch(1) or destination synch(0) */
int ie; /* interrupt enabled */
};
extern void omap_set_dma_priority(int dst_port, int priority); extern void omap_set_dma_priority(int dst_port, int priority);
extern int omap_request_dma(int dev_id, const char *dev_name, extern int omap_request_dma(int dev_id, const char *dev_name,
void (* callback)(int lch, u16 ch_status, void *data), void (* callback)(int lch, u16 ch_status, void *data),
...@@ -238,6 +382,9 @@ extern void omap_set_dma_dest_data_pack(int lch, int enable); ...@@ -238,6 +382,9 @@ extern void omap_set_dma_dest_data_pack(int lch, int enable);
extern void omap_set_dma_dest_burst_mode(int lch, extern void omap_set_dma_dest_burst_mode(int lch,
enum omap_dma_burst_mode burst_mode); enum omap_dma_burst_mode burst_mode);
extern void omap_set_dma_params(int lch,
struct omap_dma_channel_params * params);
extern void omap_dma_link_lch (int lch_head, int lch_queue); extern void omap_dma_link_lch (int lch_head, int lch_queue);
extern void omap_dma_unlink_lch (int lch_head, int lch_queue); extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
...@@ -247,9 +394,6 @@ extern int omap_get_dma_src_addr_counter(int lch); ...@@ -247,9 +394,6 @@ extern int omap_get_dma_src_addr_counter(int lch);
extern void omap_clear_dma(int lch); extern void omap_clear_dma(int lch);
extern int omap_dma_running(void); extern int omap_dma_running(void);
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
extern int omap_dma_in_1510_mode(void);
/* LCD DMA functions */ /* LCD DMA functions */
extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
void *data); void *data);
......
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