Commit 11d1b1d5 authored by Tony Lindgren's avatar Tony Lindgren

ARM: OMAP: Fix DMA register access to use _REG access

DMA register access changed to use REG16 adn REG32 macros when 24xx DMA
support was added
parent 64fec5f5
...@@ -174,10 +174,10 @@ omap16xx_cam_link_open(struct omap16xxcam *data) ...@@ -174,10 +174,10 @@ omap16xx_cam_link_open(struct omap16xxcam *data)
return ret; return ret;
} }
data->next_dmach = data->dma_channel_number1; data->next_dmach = data->dma_channel_number1;
omap_writew(data->dma_channel_number2, OMAP_DMA_CLNK_CTRL_REG(data->dma_channel_number1) =
OMAP_DMA_CLNK_CTRL(data->dma_channel_number1)); data->dma_channel_number2;
omap_writew(data->dma_channel_number1, OMAP_DMA_CLNK_CTRL_REG(data->dma_channel_number2) =
OMAP_DMA_CLNK_CTRL(data->dma_channel_number2)); data->dma_channel_number1;
return 0; return 0;
} }
...@@ -222,7 +222,7 @@ omap16xx_cam_dma_link_callback(int lch, unsigned short ch_status, void *data) ...@@ -222,7 +222,7 @@ omap16xx_cam_dma_link_callback(int lch, unsigned short ch_status, void *data)
while (cam->free_dmach < 2) while (cam->free_dmach < 2)
{ {
if ((omap_readw(OMAP_DMA_CCR(lch)) & (1 << 7) )) if (OMAP_DMA_CCR_REG(lch) & (1 << 7))
break; break;
count = (lch == cam->dma_channel_number2) ? 1 : 0; count = (lch == cam->dma_channel_number2) ? 1 : 0;
...@@ -342,9 +342,7 @@ omap16xxcam_start_dma(struct sgdma_state *sgdma, ...@@ -342,9 +342,7 @@ omap16xxcam_start_dma(struct sgdma_state *sgdma,
OMAP_DMA_SYNC_FRAME, OMAP_DMA_SYNC_FRAME,
0, 0); 0, 0);
OMAP_DMA_CLNK_CTRL_REG(dmach) &= ~( 1<< 15);
omap_writew(omap_readw(OMAP_DMA_CLNK_CTRL(dmach)) & ~(1<<15),
OMAP_DMA_CLNK_CTRL(dmach));
prev_dmach = (dmach == data->dma_channel_number2) ? prev_dmach = (dmach == data->dma_channel_number2) ?
data->dma_channel_number1 : data->dma_channel_number2; data->dma_channel_number1 : data->dma_channel_number2;
...@@ -353,11 +351,8 @@ omap16xxcam_start_dma(struct sgdma_state *sgdma, ...@@ -353,11 +351,8 @@ omap16xxcam_start_dma(struct sgdma_state *sgdma,
data->new = 0; data->new = 0;
omap16xx_cam_waitfor_syncedge(data, EN_V_UP); omap16xx_cam_waitfor_syncedge(data, EN_V_UP);
} else { } else {
if (omap_readw(OMAP_DMA_CCR(prev_dmach)) & (1 << 7)) { if (OMAP_DMA_CCR_REG(prev_dmach) & (1 << 7))
omap_writew((omap_readw(OMAP_DMA_CLNK_CTRL(prev_dmach)) | OMAP_DMA_CLNK_CTRL_REG(prev_dmach) |= (1 << 15);
(1 << 15)),
OMAP_DMA_CLNK_CTRL(prev_dmach));
}
else { else {
/* no transfer is in progress */ /* no transfer is in progress */
omap_start_dma(dmach); omap_start_dma(dmach);
......
...@@ -404,8 +404,8 @@ omap1610_irda_irq(int irq, void *dev_id, struct pt_regs *hw_regs) ...@@ -404,8 +404,8 @@ omap1610_irda_irq(int irq, void *dev_id, struct pt_regs *hw_regs)
skb_reserve(skb, 1); skb_reserve(skb, 1);
w = omap_readw(OMAP_DMA_CDAC(si->rx_dma_channel)); w = OMAP_DMA_CDAC_REG(si->rx_dma_channel);
w -= omap_readw(OMAP_DMA_CDSA_L(si->rx_dma_channel)); w -= OMAP_DMA_CDSA_L_REG(si->rx_dma_channel);
if (si->speed != 4000000) { if (si->speed != 4000000) {
memcpy(skb_put(skb, w - 2), si->rx_buf_dma_virt, w - 2); /* Copy DMA buffer to skb */ memcpy(skb_put(skb, w - 2), si->rx_buf_dma_virt, w - 2); /* Copy DMA buffer to skb */
......
...@@ -544,9 +544,9 @@ static inline dma_addr_t dma_csac(unsigned lch) ...@@ -544,9 +544,9 @@ static inline dma_addr_t dma_csac(unsigned lch)
/* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
* read before the DMA controller finished disabling the channel. * read before the DMA controller finished disabling the channel.
*/ */
csac = omap_readw(OMAP_DMA_CSAC(lch)); csac = OMAP_DMA_CSAC_REG(lch);
if (csac == 0) if (csac == 0)
csac = omap_readw(OMAP_DMA_CSAC(lch)); csac = OMAP_DMA_CSAC_REG(lch);
return csac; return csac;
} }
...@@ -557,9 +557,9 @@ static inline dma_addr_t dma_cdac(unsigned lch) ...@@ -557,9 +557,9 @@ static inline dma_addr_t dma_cdac(unsigned lch)
/* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
* read before the DMA controller finished disabling the channel. * read before the DMA controller finished disabling the channel.
*/ */
cdac = omap_readw(OMAP_DMA_CDAC(lch)); cdac = OMAP_DMA_CDAC_REG(lch);
if (cdac == 0) if (cdac == 0)
cdac = omap_readw(OMAP_DMA_CDAC(lch)); cdac = OMAP_DMA_CDAC_REG(lch);
return cdac; return cdac;
} }
...@@ -584,7 +584,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) ...@@ -584,7 +584,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
} }
#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \ #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
? omap_readw(OMAP_DMA_CSAC(x)) /* really: CPC */ \ ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
: dma_cdac(x)) : dma_cdac(x))
static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
...@@ -854,7 +854,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) ...@@ -854,7 +854,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
/* channel type P: hw synch (fifo) */ /* channel type P: hw synch (fifo) */
if (!cpu_is_omap15xx()) if (!cpu_is_omap15xx())
omap_writew(2, OMAP_DMA_LCH_CTRL(ep->lch)); OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
} }
just_restart: just_restart:
...@@ -901,7 +901,7 @@ static void dma_channel_release(struct omap_ep *ep) ...@@ -901,7 +901,7 @@ static void dma_channel_release(struct omap_ep *ep)
else else
req = NULL; req = NULL;
active = ((1 << 7) & omap_readl(OMAP_DMA_CCR(ep->lch))) != 0; active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
DBG("%s release %s %cxdma%d %p\n", ep->ep.name, DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
active ? "active" : "idle", active ? "active" : "idle",
......
...@@ -428,8 +428,7 @@ static void sound_dma_irq_handler(int sound_curr_lch, u16 ch_status, ...@@ -428,8 +428,7 @@ static void sound_dma_irq_handler(int sound_curr_lch, u16 ch_status,
sound_curr_lch, ch_status, dma_status, data); sound_curr_lch, ch_status, dma_status, data);
if (dma_status & (DCSR_ERROR)) { if (dma_status & (DCSR_ERROR)) {
omap_writew(omap_readw(OMAP_DMA_CCR(sound_curr_lch)) & OMAP_DMA_CCR_REG(sound_curr_lch) &= ~DCCR_EN;
~DCCR_EN, OMAP_DMA_CCR(sound_curr_lch));
ERR("DCSR_ERROR!\n"); ERR("DCSR_ERROR!\n");
FN_OUT(-1); FN_OUT(-1);
return; return;
......
...@@ -847,8 +847,7 @@ static void sound_dma_irq_handler(int sound_curr_lch, u16 ch_status, void *data) ...@@ -847,8 +847,7 @@ static void sound_dma_irq_handler(int sound_curr_lch, u16 ch_status, void *data)
ch_status, dma_status, data); ch_status, dma_status, data);
if (dma_status & (DCSR_ERROR)) { if (dma_status & (DCSR_ERROR)) {
omap_writew(omap_readw(OMAP_DMA_CCR(sound_curr_lch)) & ~DCCR_EN, OMAP_DMA_CCR_REG(sound_curr_lch) &= ~DCCR_EN;
OMAP_DMA_CCR(sound_curr_lch));
ERR("DCSR_ERROR!\n"); ERR("DCSR_ERROR!\n");
FN_OUT(-1); FN_OUT(-1);
return; return;
......
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