add neuros ir blaster driver

arch/arm/configs/ntosd_644xA_defconfig

@@ -830,6 +830,7 @@ CONFIG_HWMON=y
 # CONFIG_HWMON_DEBUG_CHIP is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+CONFIG_NEUROS_IR_BLASTER=m
 
 #
 # Multifunction device drivers

drivers/input/misc/neuros_ir.c

@@ -39,6 +39,7 @@
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/irq.h>
+#include <linux/interrupt.h>
 
 #include <asm/arch/hardware.h>
 
@@ -55,9 +56,6 @@
     #define dbg(fmt, arg...)
 #endif
 
-#define GPIO01_DIR	__REG(0x01C67010)
-#define GPIO01_RIS_INT	__REG(0x01C67024)
-
 #define USE_WORKQUEUE 1
 #define READ_ONLY_ONE_KEY 1
 #define IR_RETRY_COUNT 3
@@ -190,8 +188,10 @@ static void irrtc_do_wq(struct work_struct *work)
 
 	if (is_learning == 1)
 	{
-		//disable_irq(IRQ_TIMER1);
-		//outw( inw( IO_GIO_IRQPORT) & (~GIO3), IO_GIO_IRQPORT); // gio 3 external IRQ disable;
+		disable_irq(IRQ_TINT1_TINT34);
+        TIMER1_TCR &= ~(3<<22); //disable timer1 34
+        CLR_GPIO01_RIS_INT |= (1<<7); // gpio 7 rising edge IRQ disable
+        CLR_GPIO01_FAL_INT |= (1<<7); // gpio 7 falling edge IRQ disable
 		lock_data_protect();
 		set_osd_key(1);
         set_is_learning(0);
@@ -233,10 +233,7 @@ static irqreturn_t handle_irrtc_irqs(int irq, void * dev_id)
 static void irqs_irrtc_init( void )
 {
     GPIO01_DIR |= 0x04;  //gio 2 direction input
-    GPIO01_RIS_INT |= 0x04; // gio 2 rising edge IRQ enable
-    //outw( inw( IO_GIO_DIR0 ) | 0x0001, IO_GIO_DIR0 );  //gio 0 direction input
-    //outw( inw( IO_GIO_INV0 ) | 0x0001, IO_GIO_INV0 );  //gio 0 inv
-    //outw( inw( IO_GIO_IRQPORT) | 0x0001, IO_GIO_IRQPORT);  // gio 0 external IRQ enable
+    SET_GPIO01_RIS_INT |= 0x04; // gio 2 rising edge IRQ enable
     request_irq(IRQ_GPIO2, handle_irrtc_irqs, 0, "irrtc", &device); 
 }
 

drivers/misc/Kconfig

@@ -202,5 +202,18 @@ config THINKPAD_ACPI_BAY
 
 	  If you are not sure, say Y here.
 	  
+config NEUROS_IR_BLASTER
+	tristate "Neuros IR blaster driver"
+	depends on ARCH_DAVINCI
+	---help---
+	  This option enables the Neuros IR blaster driver.
+
+	  TODO: This needs a better description.
+
+	  To compile this driver as a module (recommended), choose M here: the
+	  module will be called neuros_ir_blaster.
+
+	  If unsure and targeting the Neuros OSD, say M.
+
 
 endif # MISC_DEVICES

drivers/misc/Makefile

@@ -15,3 +15,4 @@ obj-$(CONFIG_SGI_IOC4)		+= ioc4.o
 obj-$(CONFIG_SONY_LAPTOP)	+= sony-laptop.o
 obj-$(CONFIG_THINKPAD_ACPI)	+= thinkpad_acpi.o
 obj-$(CONFIG_EEPROM_93CX6)	+= eeprom_93cx6.o
+obj-$(CONFIG_NEUROS_IR_BLASTER)	+= neuros_ir_blaster.o

include/linux/neuros_ir.h

@@ -41,5 +41,24 @@
 #define TEST_KEY 0x3f
 #define UP_KEY 0x00
 
+#define GPIO01_DIR	__REG(0x01C67010)
+#define SET_GPIO01_IN_DATA	__REG(0x01C67020)
+#define SET_GPIO01_RIS_INT	__REG(0x01C67024)
+#define CLR_GPIO01_RIS_INT	__REG(0x01C67028)
+#define SET_GPIO01_FAL_INT	__REG(0x01C6702C)
+#define CLR_GPIO01_FAL_INT	__REG(0x01C67030)
+#define GPIO23_DIR	__REG(0x01C67038)
+#define GPIO23_OUT_DATA	__REG(0x01C6703C)
+#define GPIO23_SET_DATA	__REG(0x01C67040)
+#define GPIO23_CLR_DATA	__REG(0x01C67044)
+#define PINMUX1 __REG(0x01C40004)
+#define PWM0_CFG	__REG(0x01C22008)
+#define PWM0_PER    __REG(0x01C22014)
+#define PWM0_PH1D    __REG(0x01C22018)
+#define TIMER1_TIM34    __REG(0x01C21414)
+#define TIMER1_PRD34    __REG(0x01C2141C)
+#define TIMER1_TCR    __REG(0x01C21820)
+#define TIMER1_TGCR    __REG(0x01C21824)
+
 #endif /* NEUROS_IR__H */
 

include/linux/neuros_ir_blaster.h

@@ -32,8 +32,6 @@
     #include <stdint.h>
 #endif
 
-#define BLASTER_THROUGH_ARM
-#define GIO3 0x0008
 #define KEY_MASK 0xff
 #define NEUROS_IR_BLASTER_MAJOR 111
 #define NEUROS_IR_BLASTER_IOC_MAGIC 'b'
@@ -53,7 +51,6 @@
 #define CAPTRUE_PRECISION3 17 /*averaged off x% difference.*/
 #define the_same3(x,y) the_same(x,y,CAPTRUE_PRECISION3)
 
-#ifdef BLASTER_THROUGH_ARM
 #define BLS_START 0
 #define BLS_COMPLETE 1
 #define BLS_ERROR -1
@@ -72,47 +69,6 @@ struct blaster_data_type {
     uint32_t bits[BLASTER_MAX_CHANGE];  	/*each bit length*/
 };
 
-#else
-
-// I2C command definitions.
-#define cmdBLASTER_SEND         0x18
-/* RRB registers definitions. */
-#define regCMND                 0     // command register.
-#define regBLASTER_DBITS        (0x80+24)  // used to put blaster data(part7)
-#define regBLASTER_MBITS        0x80  // used to put blaster data(part6)
-#define regFLASH_DATA           0x06  // used to put blaster data(part5)
-#define regBLASTER_BIT2         (regBLASTER_DATA+6)  // used to put blaster data(part4)
-#define regBLASTER_BIT1         (regBLASTER_DATA+4)  // used to put blaster data(part3)
-#define regBLASTER_BIT0         (regBLASTER_DATA+2)  // used to put blaster data(part2)
-#define regBLASTER_DATA         0x1C  // used to put blaster data(part1)
-
-#define BLASTER_MAX_CHANGE	(8*24)  /* maximum edge changes. */
-#define BLASTER_MAX_SBITS       8       /*special edge number min is 6*/
-#define BLASTER_MAX_BITS	(8*24)  /*maximum edge changes, use for uncompacted data structure*/
-#define END_COUNT               8       /*number of edges for end bit. */
-#define BITS_COUNT_START        7       /*bits count start. */
-#define END_FLAG_START          6       /*end flag mask. */
-#define BITS_COUNT_MASK         (0xFF<<BITS_COUNT_START)  /*bits count mask. */
-#define END_FLAG_MASK           (1<<END_FLAG_START)       /*end flag mask. */
-#define MAX_REPEAT_TIMES        7       /*bits count start. */
-#define BITS_TIMES_MASK         0xFFF8  /*bits times mask. */
-#define FIRST_LEVEL_BIT_START   15      /*bits count start. */
-#define FIRST_LEVEL_BIT_MASK    (1<<FIRST_LEVEL_BIT_START)    /*end flag mask. */
-
-struct blaster_data_type {
-    uint16_t bitstimes;     /*first[15] 1 bit 1=high level  0=low level; 
-                                [8+BITS_COUNT_START-BITS_COUNT_START]8 bit =how many bits;
-                                [END_FLAG_START] 1=have end bits 0=not have end bits
-                                [2-0]3 bit=how many repeat times*/
-    uint16_t start1;        /*start mark first length */
-    uint16_t start2;        /*start mark second length*/
-    uint16_t interval;      /*interval for each times */
-
-    uint16_t bits[BLASTER_MAX_BITS];  	/*each bit length*/
-    uint16_t end[END_COUNT];
-};
-#endif
-
 struct blaster_data_pack {
     uint16_t bitstimes;       /*first[15] 1 bit 1=high level  0=low level; 
                                 [7+BITS_COUNT_START-BITS_COUNT_START]8 bit =how many bits;